JPH0331932A - Data processor - Google Patents

Abstract

PURPOSE:To extend the applied range of an instruction program by shifting a processing to an instruction subprogram composed of the instruction to be set beforehand at the time of indicating the non-execution of an exception processing to an exception detected with a hardware and/or farmware in the middle of executing the instruction program. CONSTITUTION:When an ordinary software and instruction program are executed, since an exception conditions detecting signal 100 is '0' and the contents of a mode register 2 are also '0', the output of an adder 7 is stored through a selector 4 to an instruction counter 5. Consequently, the contents of the instruction counter 5 are updated so as to indicate the next instruction address each time the instruction is executed. When the exception conditions are detected and the exception conditions detecting signal 100 goes to '1' in a condition in which the mode register 2 holds '0', the output of an AND gate 11 goes to 1, and as a result, an exception interruption processing mechanism 8 is activated, and the exception processing is executed. Thus, the applied range of the instruction program can be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data processing device, and more particularly to exception handling in a data processing device using a microprogram.

Prior Art Conventionally, in order to improve processing performance in this type of data processing device, the number of functions that the microinstructions that make up the microprogram execute in one step has been increased, parallelism has been increased, and the bit configuration has been changed. The large-scale shift to so-called horizontal micro-instructions is noticeable. In particular, for frequently used instructions such as basic arithmetic instructions, the hardware structure is optimized to maximize the features of the horizontal microinstructions mentioned above, so they can be realized with an extremely small number of microprogram steps. .

On the other hand, even if highly horizontalized microinstructions are used, many of which involve sequential processing, each insertion control instruction has a low degree of parallelism in functions executed in one step, resulting in a large number of unused microinstruction fields. The applicant of the present invention has proposed a method of increasing the utilization efficiency in the word direction of a control memory that stores microprograms by adopting a hierarchical structure in which the above-mentioned basic operation instructions are implemented using an instruction program. There is.

Such instruction programs are secured in a protected area and cannot be accessed by normal software, so even if the instruction program is being executed, the software may not be aware that the instruction program is being executed. It will not be done.

Among the instructions realized by the data processing device as mentioned above,
If an exception condition is detected during the operation, instead of (7) activating exception handling using the 1-outside index processing mechanism, the instruction is terminated after performing post-processing specific to that instruction, and the condition code is used to terminate the instruction. There is something that indicates that an exceptional condition has been detected.

For example, there is an instruction that converts a logical address indicated by an address syllable (a field indicating an operand address in an instruction word) into an absolute address and sets it in a general-purpose register.

During the execution of this instruction, in the process of converting the logical address indicated by the address syllable into an absolute address, if an exception condition such as segment out-of-line or missing page is detected, the following processing is performed without generating an exception. conduct.

That is, first, the absolute address of the page identifier is stored in the general-purpose register instead of the absolute address of the conversion result, and a condition code is written to indicate that an exception has been detected.
Set to 1″.

If no exceptional condition is detected during the execution of this instruction, the condition code is reset to “0”.
By referring to the condition code after executing this instruction, it is possible to know whether an exceptional condition has been detected.

Such conventional data processing devices did not have a function to suppress the reporting of exceptions detected during the execution of an instruction program, so the logical address indicated by the address syllable as described above is converted to an absolute address and stored in a general-purpose register. If the instruction to set the value is realized by an instruction program,
If an exception condition is detected by the hardware during the execution of this instruction, the exception handling mechanism will be activated and the exception will actually be reported. Therefore, when the exception condition is detected, the condition code is updated and the exception is reported. Since this violates the specification that the instruction is completed without any processing, the above-mentioned instructions cannot be realized by the instruction program, and the scope of application of the instruction program is narrowed.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the problems of the conventional ones as described above, and an object of the present invention is to provide a data processing device that can expand the scope of application of instruction programs.

Composition of the Invention A data processing device according to the present invention performs exception processing when an exception is detected by at least one of hardware and firmware during execution of an instruction program constituted by instructions implemented by a microprogram on a control storage. is configured by a mode flag set by the instruction program and the instruction set in advance when the exception is detected and the mode flag indicates non-execution of the exception handling. and means for transferring processing to an instruction subprogram.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a main memory 1 stores an instruction program 20 and an instruction subprogram 21.

Mode register 2 is SEM in instruction program 20.
(Set Exception Mask) instruction 201
is set to “1” by executing RE M (Re
set 1Exccpmouth.

nMask) is reset to “0” by executing the instruction 202.

The entry address of the instruction subprogram 21 to be activated when an exceptional condition is detected is set in the instruction subprogram address register (hereinafter referred to as address register) 3 by the SEM instruction instruction 202 line in the instruction program 20.

The selector 4 selects one of the output from the address register 3 and the output from the adder 7 according to the output of the AND gate 9 and outputs it to the instruction counter 5. That is, the selector 4 selects the output of the adder 7 if the output of the AND gate 9 is 0°, and selects the output of the address register 3 if the output of the AND gate 9 is "1".

The instruction counter 5 stores the instruction address of the currently executed software and instruction program, and the instruction length register 6 holds the length of the currently executed instruction.

The adder 7 adds the contents of the instruction counter 5 and the contents of the instruction length register 6, and outputs the addition result to the selector 4.

The exception identification processing mechanism 8 is activated in response to the output of the AND gate 11 and executes exception processing.

AND gate 9 is an exception condition detection signal 100 from at least one of hardware and firmware (not shown).
and the output from mode register 2, and
The result is output to the selector 4.

The AND gate 11 performs a logical AND operation between the exception condition detection signal 100 and the inverted value of the output from the mode register 2 inverted by the inverter 10, and outputs the result to the exception indexing process #1 structure 8.

When normal software or instruction programs are executed, the exception condition detection signal 100 is "0" and the content of the mode register 2 is also "0", so the output of the adder 7 is passed through the selector 4 to the instruction counter 5. is stored in As a result, the contents of the instruction counter 5 are updated to indicate the next instruction address each time an instruction is executed.

When an exception condition is detected and the exception condition detection signal 100 becomes 1° while the mode register 2 holds “0”,
The output of the AND gate 11 becomes 1'', and as a result, the exception identification processing mechanism 8 is activated and exception processing is executed.

In order to suppress the activation of the exception identification processing mechanism 8 when an exceptional condition is detected, that is, to suppress the activation of the exception identification processing mechanism 8 in the instruction program 20, the SEM instruction 201 is executed.

This SEM instruction 201 is an instruction that can be executed only in the instruction program 20, and takes as an argument the entry address of the instruction subprogram 21 to be activated when an exceptional condition is detected.

1″ is set in mode register 2 by executing SEM instruction 201.
is set, and the entry address of the instruction subprogram 21 to be activated when an exceptional condition is detected is set in the address register 3.

Even if an exception condition is detected and the exception condition detection signal 100 becomes "1" after execution of the SEM instruction 201, the output of the AND gate 11 is "0" because the output of the inverter 10 is "0".
0'' remains, and the exception identification processing mechanism 8 is not activated.

On the other hand, when the exceptional condition detection signal 100 becomes 1", the output of the mode register 2 is "1", so the output of the AND gate 9 becomes "1", and the selector 4 sets the address in the address register 3 as the next instruction address. An entry address of the instruction subprogram 21 is selected, and the entry address is set in the instruction counter 5.

Therefore, reading of the instruction program is started at the address indicated by the instruction counter 5, and the processing moves to the instruction subprogram 21. As a result, the program branches to the instruction subprogram 21 instead of activating the exception identification processing mechanism 8.

When the processing requiring the suppression of activation of the exception indexing processing mechanism 8 is completed, the REV instruction 202 is executed.

By executing this REM instruction 202, the mode register 2 is reset to "0", and if an exception condition is detected thereafter, the exception identification processing mechanism 8 is activated.

In the above processing, for example, in the case of an instruction that converts a logical address indicated by an address syllable into an absolute address and sets it in a general-purpose register, when an exception condition is detected, activation of the exception allocation processing mechanism 8 is inhibited. At the same time, the absolute address of the page identifier is stored in the general-purpose register by the instruction subprogram 21, and a condition code is set to "1" to indicate that an exception has been detected. This instruction subprogram 2]
Similarly to the instruction program 20, the control memory (not shown)
This is realized by a microprogram stored in the .

In this way, the SEM instruction 201 in the instruction program 20
If an exception condition is detected by at least one of the hardware and software when the mode register 2 is set by By branching to the entry address of the instruction subprogram 21 set to
By setting/resetting the mode register 2, when an exception condition is detected during execution of the instruction program 20, it is possible to freely switch between activating the exception indexing processor fN 8 or branching to the instruction subprogram 21. .

This makes it possible to suppress reporting of exceptions detected during execution of the instruction program 20, and instead of starting exception handling by the exception processing mechanism 8 when an exception condition is detected, After post-processing, the instruction is terminated and the condition code indicates that an exception condition has been detected.This can be realized by an instruction program implemented by a microprogram in control memory, so application of the instruction program is possible. The range can be expanded.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the mode flag set by the instruction program is set by the hardware and firmware during the execution of the instruction program constituted by the instructions implemented by the microprogram on the control memory. Expands the scope of application of the instruction program by shifting processing to an instruction subprogram consisting of preset instructions when indicating non-execution of exception handling for an exception detected by at least one of the two. The effect is that it can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1...Main memory 2...Mode register 3...Instruction subprogram address register 4...Selector 5... ...Instruction counter 7 ...Adder 8 ...Outside column index processing mechanism 911 ...AND gate 10 ...Inverter 20 ...Instruction Program 21...Instruction subprogram

Claims (1)

[Claims] (1) Indicates whether or not to execute exception handling when an exception is detected by at least one of the hardware and firmware during the execution of an instruction program composed of instructions implemented by a microprogram on the control memory. , a mode flag set by the instruction program, and when the exception is detected and the mode flag indicates non-execution of the exception handling, processing is transferred to an instruction subprogram configured by the instruction set in advance. 1. A data processing device comprising means for: