JPH0240722A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To carry on previous processing by providing a storage device outside, saving held contents when an interruption processing is generated during an instruction holding period, and reading them out after the interruption processing. CONSTITUTION:An instruction code which is taken out of an instruction queue 101 is sent to a reset code detector 102 and held temporarily according to the indication of a sequencer 103. If an operand latch load/store controller 115 receives an interruption signal during the holding period, a control signal is sent to an operand latch 107 or 108 where an instruction signal is held. Then the held contents are transferred temporarily to a latch register 114 and then sent to the external storage device and the interruption processing is performed. After the interruption processing, the controller 115 sends a control signal to the storage device. Its contents are read out by a latch register 113 and sent to the latch 107 or 108 where the contents are held before the interruption processing to carry on the operation.

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to an arithmetic processing device. More specifically, the present invention relates to the configuration of a novel arithmetic processing device that executes processing based on an instruction word consisting of one instruction code field and a plurality of operand fields. BACKGROUND OF THE INVENTION In this specification, an instruction code field is a field that specifies the contents of an operation to be processed by a processing device. Further, the operand field means a field that specifies data area information necessary for acquiring data used in this calculation process and storing calculation result data. An example of an instruction executed using such a format field is a transfer instruction. That is, register R
The instruction to transfer data from O to register R1 is CMO
V RO, R1). Here, "MOV" is the operation content to be written in the instruction code field.
"Transfer" and "ROlRl" represents data area information to be written in the operand field. Incidentally, the repertoire of instructions to be processed by an arithmetic processing unit (processor), the types of addressing modes, and the arithmetic execution environment (resources such as accumulator registers) tend to expand and become more diverse in accordance with user needs. As an instruction set handles more complex functions, the amount of information held by one instruction increases, and as a result, the length of the instruction code becomes longer. The following three points are particularly important for the increase in functionality. (1) Increase in the types of calculations and controls (2) Increase in data types (3) Increase in addressing modes How can we encode this information in a shorter way to cope with the increase in instruction functions, that is, the increase in the amount of instruction information? has become an important issue. In other words, the reasons why shortening the instruction length is effective are: ・Reducing the code size of the entire program ・Reducing the time to fetch instruction codes to the processor ・Increasing the effect on instruction queue/instruction cache capacity and hit rate ・Shortening the decoding cycle This is because many advantages such as From this point of view, an arithmetic processing device having a function of retaining a part of instructions has already been proposed (Japanese Patent Application No. 60-2
88778). When this arithmetic processing unit repeatedly executes instructions that involve the same calculation or data,
The instructions are shortened by keeping the same parts. For example, by holding "MOV" when a sequence of instructions such as [MOV #1, C0n5t1] [MOV #8, C0n5t2] [MOV #128, const 3] continues [

[Fixed instructions] MOV #1, constl #8, C0n5t2 #128, cons t 3 [Fixed release instructions] The processing can be simplified as a non-repetitive instruction sequence. FIG. 3 is a diagram illustrating an example of the configuration of a conventional arithmetic processing device having such fixed instructions. As shown in FIG. 3, this device includes an instruction key 301 that stores read instruction codes, a detector 302 that detects a code that releases instruction retention, a sequencer 303 that controls the overall order, According to instructions from the sequencer 303, a demultiplexer 304 separates the instruction code into its fields, an opcode latch 306, a first
Second operand latch 307, 308, instruction code decoder 311, operand decoder 312, selector 310 that selects whether to decode the first or second operand of the instruction, and indicator 309 that issues an instruction to hold the instruction. , a latch strobe signal generator 305 that generates a control signal to the latch, and the like. The operation of the conventional arithmetic processing device shown in FIG. 3 is as follows. That is, the instruction code taken out from the queue 301 according to the instruction of the sequencer 303 is sent to the release code detector 302 via the line 321, but when a release code is detected during the instruction holding period, the sequencer 303 is notified and the instruction code is sent to the release code detector 302. The hold is released. Other than that, the data is sent as is to the demultiplexer 304, and is also supplied to the decoder that deals with the field of the instruction code while following the instructions of the sequencer 303. If the field is an instruction code, it is transferred to the instruction code dedicated decoder 311 and the decoding result is output via line 322. If the field is the first or second operand,
- Once transferred to the operand selector 310, the operand decoder 31
2 and the decoding result is output via line 323. The basic operation of the apparatus shown in FIG. 3 is as described above, but special operations are performed in the following two cases. That is, the first case is when the instruction code decoder 311 detects a fixed instruction code or a fixed operand instruction. At this time, the instruction code decoder 311 notifies the fixed field indicator 309 of the event. Next, the operand decoding of the fixed instruction is performed by the operand decoder 312, and when the result of what is to be fixed is obtained, the contents are stored in the fixed field indicator 309. The decoding sequence of the next instruction (fixed instruction) after the fixed instruction is the same as in the normal case. However, according to the instructions from the fixed field indicator 309 and the sequencer 303, a part of the field of the fixed instruction is fixed. More specifically, a latch strobe signal generator 305 that controls latches (instruction code latch 306, first operand latch 307, second operand latch 308) corresponding to each field of an instruction is connected to a fixed field indicator 309 and a sequencer 303. generates a signal that fixes the specified command field according to the instruction. When decoding instructions after the fixed instruction, there is no need to consider the decoding wait time (delay due to decoding) of the fixed part, so the decoding cycle of that part can be omitted. The sequencer 303 is a fixed field indicator 309
Based on this information, the sequence control cycle is shortened. The second special operation occurs when the release code detector 302 detects an instruction code unfixing instruction or an operand unfixing instruction. That is, at this time, the release code detector 302 notifies the sequencer 303 of the event. Sequencer 303 returns the decode sequence to its original state, releases all latch functions for latch strobe signal generator 305, and allows instructions to flow through all decode paths again. As a result, normal instruction decoding is performed from the next instruction onward. Problems to be Solved by the Invention However, in the configuration of the conventional arithmetic processing device as described above, if an interrupt occurs during the instruction holding period, the held contents are lost, and after the interrupt processing is completed, the interrupt processing still occurs. The disadvantage is that the instruction execution cannot be resumed. for example〔

[Fixed instructions] MOV'#1, constl #8 const2/#128, const 3 [Fixed release instruction] An interrupt occurs while executing the instruction sequence, (MOV)#
8. If interrupt processing is executed after executing cons t 2, the contents of the instruction code latch will change and "MOV" will be lost. Therefore, after the interrupt processing, the next instruction (#128, c
ons t 3], resulting in an instruction without an instruction code, which makes it impossible to execute. Therefore, in order to solve the above-mentioned drawbacks of the conventional technology, the present invention saves and reads the contents held in the storage device during interrupt processing, thereby making it possible to observe the processing even after interrupt processing while instructions are being held. The purpose is to provide a new arithmetic processing device. Means for Solving the Problems According to the present invention, when decoding and executing an instruction having a plurality of areas including an arithmetic instruction area for instructing processing contents, at least one of the plurality of areas is held and multiple processing is performed. In an arithmetic processing device configured to execute, when an interrupt process occurs during an instruction holding period in which at least one of the plurality of areas is held, means for saving the held contents to a storage device; There is provided an arithmetic processing device characterized by comprising means for reading out the saved contents from a storage device and restarting the processing before the interruption after the separate processing is completed. The present invention will be described in more detail below with reference to the drawings, but the following disclosure is only one example of the present invention and does not limit the technical scope of the present invention in any way. Embodiment FIG. 1 shows a case where an arithmetic processing device according to the present invention is constructed corresponding to the conventional arithmetic processing device shown in FIG. 3 described above. Therefore, in the following description, the present invention will be explained in detail, focusing on the differences between FIG. 1 and FIG. 3. First, an embodiment of the present invention shown in FIG. 1 will be described. In FIG. 1, 101 is an instruction queue that stores read instruction codes, 102 is a release code detector that detects instruction code fix release instructions, 103 is a sequencer that controls the overall order, and 104 is a system that follows instructions from the sequencer 103. a demultiplexer that separates the instruction code into each field; 106 a latch that holds the instruction code; 10;
7 ・108 is a latch that holds the first and second operands, 111 is a decoder dedicated to instruction code, 112
110 is an operand-only decoder; 110 is a selector that selects whether to decode the first operand or second operand of the instruction; 109 is an indicator that issues an instruction to hold the instruction;
105 is a latch strobe signal generator that generates a signal to control the latch. 101.102 in Figure 1
．． 103.104.105.106.107.108.
109.110.111.112 are respectively 301 in Figure 1
．． 302.303.304.305.306.307.
308.309.3 JO, 311. 312. The operation shown in FIG. 1 will be explained. The instruction code taken out from the queue 101 according to the instructions of the sequencer 103 is
The signal is sent to the release code detector 102 via the line 121, and if a release code is detected during the instruction holding period, the sequencer 103 is notified and the instruction holding is released. Otherwise, the data is sent as is to the demultiplexer 104, and is also supplied to a decoder that deals with the instruction code field while following instructions from the sequencer 103. If the field is an instruction code, it is transferred to the instruction code dedicated decoder 111 and the decoding result is output via line 122. If the field is the first or second operand, -dan operand selector 1
10 and then to the operand decoder 112 according to the first/second operand, and the decoding result is output via line 123. The operation in FIG. 1 will be explained focusing on the characteristic parts that are different from those in FIG. 3. In FIG. 1, the operation when no command is held is the same as the operation of the conventional example shown in FIG. Third
The operation differs from that shown in the figure when an interrupt signal is input during the period in which an instruction is held. At this time, in Figure 3,
Instruction code latch 106 ・Operand latch 110
7. Operand latch ■ The contents held in 108 are lost. However, in FIG. 1, when the operand latch load/store controller 115 receives an interrupt signal, it sends a control signal to the latch holding the value among the instruction code latch 106, operand latch 107, and operand latch 108. is sent, the held contents are once transferred to the hold register 114, and then sent to the external storage device before interrupt processing is performed. After the interrupt processing is completed, the operant latch load/store controller 115 sends a control signal to the -H border register 11 to store the contents previously sent to the external storage device.
13, instruction code latch 106 ・operand latch 1107 ・operand latch ■10
8, the read content is sent to the latch that was holding it, and the operation before the interrupt is continued. FIG. 4 shows a flowchart of operations during the instruction holding period. FIG. 2 is a diagram showing the configuration of another embodiment of the present invention. This embodiment corresponds to a method in which a retention period can be specified in an instruction code/operand fixed instruction. In FIG. 2, 202 is omitted and 216 is added compared to FIG. 1. In FIG. 2, 216 is a counter, which stores a holding period specified as an operand in an instruction code/operand fixed instruction when the instruction is decoded. The counter 216 is decremented every time one instruction is decoded, and if it is not 0, it instructs the latch strobe signal generator 205 to hold it, and if it is 0, it notifies the sequencer 203 that the holding period has ended. This is the same as the notification given by the release code detector 102 in FIG. 1 to release the command hold. As described in detail of the invention, in the prior art, when interrupt processing occurs during an instruction holding period, the held contents are lost, so there is a problem that the operation before the interrupt cannot be resumed after the interrupt processing is completed. Ta. On the other hand, in the arithmetic processing device according to the present invention, since the retained contents are saved in the storage device when an interrupt process occurs, the contents can be read out after the interrupt process is completed and the process can be resumed continuously.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a specific configuration example of the present invention, and corresponds to the configuration of the conventional device shown in FIG. 3, and FIG. 2 is a diagram showing another embodiment of the present invention. FIG. 3 is a diagram showing a configuration example of a conventional arithmetic processing device, and FIG. 4 is a diagram explaining the operation of the device shown in FIG. 3. [Main reference numbers] 101...Instruction queue, 102...Instruction unfixing code detector, 103...
Decode sequencer, 104... Demultiplexer, 105... Instruction fixed latch strobe signal generator, 1
06... Instruction code fixing latch, 107... First operand fixing latch, 108...
2nd operand fixed latch, 109... fixed field indicator, 110... operand selector, 111... instruction code decoder, 112... operand decoder, 216... counter 301... instruction queue, 302... Instruction fixation release code detector, 303...
Decode sequencer, 304... Demultiplexer, 305... Instruction fixed latch strobe signal generator, 3
06 ... 307 ... 308 ... 309 ... 310 ... 311 ... 312 ... Instruction code fixed latch, first operand fixed latch, second operand fixed latch, fixed field indicator, Operand selector, instruction code decoder, operand decoder

Claims (1)

[Scope of Claims] When decoding and executing an instruction including a plurality of areas including an operation instruction area for instructing processing contents, at least one of the plurality of areas is retained to execute multiple processes. In the arithmetic processing device configured, when an interrupt process occurs during an instruction holding period in which at least one of the plurality of areas is held, a means for saving the held contents to a storage device, and a means for saving the held contents to a storage device, and a means for saving the held contents in a storage device, , means for reading the saved contents from a storage device and restarting the processing before the interruption.