JPH0675789A - Information processor - Google Patents

Abstract

PURPOSE:To provide the information processor improving the system efficiency. CONSTITUTION:The device is provided with a memory access section 5 detecting the failure in acquiring the semaphore on a memory by the execution of a test and set instruction for acquiring the semaphore and an exception processing section 7 generating exceptions by the information. Thus, the wasteful processing based on the failure in acquiring the semaphore is reduced, resulting in improving the system efficiency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for performing queuing control for obtaining processing or area access right among a plurality of processes.

[0002]

2. Description of the Related Art A conventional information processing apparatus (for example, Japanese Patent Laid-Open No.
(See Japanese Patent No. 271859).
FIG. 3 shows a schematic configuration of a conventional information processing apparatus. In FIG. 3, an instruction decoding unit 1 decodes the instruction 10. A control unit 2 generates a control signal from the decoded instruction. Reference numeral 3 is a register unit, 4 is an address calculation unit for calculating an address for data memory access, and 5 is a memory access unit for accessing data with a memory. 6 is a memory.

The operation of the information processing apparatus configured as described above will be described below. First, the acquired access to the semaphore on the memory is performed as follows,
During this access, the semaphore is controlled so that no other access is allowed.

(1) The designated 1 byte (semaphore) on the memory is read. (2) Hold the read 1 byte.

(3) The read 1 byte is set to 0xff and written in the byte designated in (1) on the memory.

(4) If the value held in (2) is 0x00, the acquisition is successful, and if 0xff, the acquisition is unsuccessful.

The instructions for accessing (1), (2) and (3) are called test and set instructions. The semaphore release access is performed by writing 0x00 to the address of the semaphore on the memory. This is done by a store instruction.

[0008]

However, in the above configuration, the process that failed to acquire the semaphore is
There is a problem in that the efficiency of the system is lowered because a process that executes a wasteful execution of a processor runs repeatedly by repeatedly accessing a semaphore that fails in acquisition until the semaphore is released.

In view of the above problems, the present invention provides an information processing apparatus which improves the efficiency of the system.

[0010]

In order to solve the above problems, an information processing apparatus according to the present invention includes a memory access unit for detecting that a test and set instruction has failed to acquire a semaphore, and a memory access unit for the memory access unit. An exception processing unit that detects an unsuccessful acquisition of the detected semaphore as an exception.

[0011]

According to the present invention, with the above-described configuration, the memory access unit notifies the exception processing unit that the acquisition of the semaphore has failed by executing the test and set instruction, and the exception processing unit generates an exception and the exception processing handler. Then, the exception handling handler improves the efficiency of the system by putting the process that failed to acquire the semaphore into the sleep state.

[0012]

【Example】

(Embodiment 1) An information processing apparatus according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of an information processing apparatus in an embodiment of the present invention.

In FIG. 1, 1 is an instruction decoding unit for decoding an instruction 10 and 2 is a control unit for controlling each unit of the processor with the instruction decoded by the instruction decoding unit as an input.
3 is a general-purpose register unit, 4 is an address calculation unit for calculating an address for memory access with the address source 15 read from the register unit 3 as an input, and 5 is a register unit using the address 16 calculated by the address calculation unit 4. A memory access unit for accessing data between the memory 3 and the memory 6, a memory unit 6 and an exception processing unit 7 for detecting an exception and shifting execution to an exception handler.

The operation of the information processing apparatus configured as described above will be described below with reference to FIG.

Execution of the test and set instruction is performed as follows. When the test and set instruction appears in the instruction 10, the instruction decoding unit 1 decodes the test and set instruction and requests the control unit 2 to process the test and set instruction. The control unit 2 reads the source data of the access address of the test and set instruction from the register unit 3. The read source data 15 is added in the address calculator 4 and output as the access address 16 of the test and set instruction. The memory access unit 5 is instructed by the control unit 2 to execute the test and set instruction, outputs the access address 16 to the address 11, and instructs the memory 6 to read using the memory control signal 12.

The memory 6 outputs the byte designated by the address indicated by the address 11 to the data 13, and uses the memory control signal 12 to instruct the completion of reading. The memory access unit 5 outputs the read data 13 to the data 14, and at the same time, uses the control signal 17 to instruct the control unit 2 to complete the reading of the test and set instruction from the memory. After the reading is completed, the memory access unit 5 controls to write the value of 0xff to the access address of the test and set instruction indicated by the address 16.
That is, the address used for reading is output to the address 11, 0xff is output to the data 13, and the memory control signal 12 instructs writing. The control unit 2 recognizes the completion of the reading from the memory and stores the data 14 in the register unit 3.
Instruct writing.

The memory access unit 5 compares the data read by the test and set instruction with 0x00, and if it is not 0x00, the control signal 18 is used to notify the exception handling unit 7 that the test and set instruction is a semaphore. Indicates that acquisition failed. However, the read data is 0
If x00, no exception occurs.

When the exception processing unit 7 knows from the control signal 18 that the test and set instruction has failed to acquire the semaphore, it uses the control signal 19 to inform the control unit 2 that
Instruct to move to exception handler. The exception handling handler switches the processes so that the currently executing process is put in a waiting state and another waiting process is run. The process in the waiting state resumes execution from the test-and-set instruction in which acquisition of the semaphore failed due to later process switching.

Therefore, the semaphore reacquisition trial can be performed without describing in the program the process of reacquisition trial when the acquisition of the semaphore fails.
The program size can be reduced. Also, in the case of a single processor configuration, if process switching is not performed, the semaphore will not be released by other processes. Therefore, after semaphore acquisition fails, process switching is performed immediately, improving system efficiency. To do.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of an information processing apparatus showing a second embodiment of the present invention. In the figure, 1 is an instruction decoding unit, 2 is a control unit, 3 is a general-purpose register unit, 4 is an address calculation unit, 5 is a memory access unit, 6 is a memory unit, and 7 is an exception processing unit. The configuration is similar. The difference from FIG. 1 is that the control signal 18
Indicates the completion of the instruction to release the semaphore in addition to the failure to acquire the semaphore due to the execution of the test and set instruction, and the control signal 18 holds the access address where the acquisition of the semaphore failed or the access address which released the semaphore. In addition, the register 14 whose content can be read by the register access instruction is provided.

The operation of the information processing apparatus configured as described above will be described below. The test and set instruction is executed as follows. Similar to the first embodiment, the data indicated by the access address of the test and set instruction is read into the data 13, and the memory access unit 5 compares the data 13 with 0x00. If they do not match, it is determined that the acquisition of the semaphore has failed. , To the control signal 18. Here, the exception handling unit 7 instructs the transition to the exception handler as in the first embodiment. At the same time, the register 8 holds the access address 11 of the test and set instruction. The exception handling handler activated by the failure to acquire the semaphore due to the execution of the test and set instruction switches the process so as to put the currently executing process, which has failed to acquire the semaphore, into the waiting state, as in the first embodiment. , At the same time, issued an instruction to read register 8 and read the contents of register 8 and entered the waiting state The currently executing process failed to acquire the semaphore at the access address of the test and set instruction held in register 8. Register it in the kernel data as the reason for waiting.

Execution of the semaphore release instruction is performed as follows. When the semaphore release instruction appears in the instruction 10, the instruction decoding unit 1 decodes the semaphore release instruction and requests the control unit 2 to process the semaphore release instruction. The control unit 2 reads the source data of the access address of the semaphore release instruction from the register unit 3. The read source data 15 is added in the address calculator 4 and output as the access address 16 of the semaphore release instruction. The memory access unit 5 is instructed by the control unit 2 to execute the semaphore release instruction, outputs the access address 16 to the address 11, outputs 0x00 to the data 13, and outputs the memory control signal 1
2 is used to instruct the memory 6 to write. The memory access unit 5 outputs the completion of execution of the semaphore release instruction to the control signal 18 and indicates to the exception processing unit 7 that the semaphore release instruction has released the semaphore. When the exception handling unit 7 knows from the control signal 18 that the semaphore release instruction has released the semaphore, it uses the control signal 19 to instruct the control unit 2 to shift to the exception handling handler. At the same time, the register 8 holds the access address 11 of the semaphore release instruction. The exception handling handler reads the access address of the semaphore release instruction from the register 8 and releases the wait reason of the process waiting for the release of the semaphore held by the register 8 in the process currently in the wait state in the kernel data. Then, if there is a process waiting for the release of the semaphore at the access address held in the register 8, the process is selected from that process, and if there is not, the process in the waiting state other than the semaphore waiting state is selected to enter the running state. To do. When the process that has released the semaphore and entered the waiting state becomes the running state due to the subsequent process switching, execution resumes from the instruction following the semaphore release instruction.

The process selection here may be performed by appropriately selecting the process to be executed next from the process group excluding the process waiting for the release of the semaphore from all the processes, and setting the process-specific priority. You can follow the order, you can choose from processes released from waiting to release the semaphore, or you can return to the process that released the semaphore, which is operating system dependent.

The process released from the wait for the semaphore resumes execution from the test and set instruction in which acquisition of the semaphore failed. Therefore, in addition to the effect similar to that of the first embodiment, it becomes possible to immediately bring a process having a high priority for waiting for a semaphore into a running state after the semaphore is released, thereby improving system efficiency. Although the semaphore has a byte size in the embodiment, this is the minimum memory access unit, or the test and set instruction and the semaphore release instruction specify which bit in the byte is the semaphore. Any size will do as long as the function to add is added. In the embodiment, the set state of the semaphore is 0xff and the reset state is 0x0.
Although it is set to 0, this may be any other two fixed values.

[0025]

As described above, the present invention according to claim 1 is
By providing a data access unit that detects that the test and set instruction has failed to acquire the semaphore and an exception processing unit that detects the failure to acquire the semaphore detected by this data access unit as an exception, the data access unit Execution of the test and set instruction notifies the exception processing unit that acquisition of the semaphore has failed, the exception processing unit generates an exception, and transfers processing to the exception processing handler. Putting the dormant into sleep can improve the efficiency of the system.

According to a second aspect of the present invention, a memory access unit for detecting failure of acquisition of a semaphore and completion of release of a semaphore by execution of a test and set instruction, and exception processing for generating an exception according to the information. Sections and registers that hold access addresses for those semaphores make it possible to put a process with a high priority waiting for a semaphore into a running state immediately after the semaphore is released, improving system efficiency. can do.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an information processing device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an information processing device according to a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a conventional information processing device.

[Explanation of symbols]

 1 instruction decoding unit 2 control unit 3 register unit 4 address calculation unit 5 memory access unit 6 memory 7 exception processing unit 8 register 10 instruction 11, 16 address 12, 17, 18, 19 control signal 13, 14 data 15 source data

Claims (2)

[Claims] 1. Information comprising a memory access unit for detecting that a test and set instruction has failed to acquire a semaphore, and an exception processing unit for detecting a failure of acquisition of the semaphore detected by this memory access unit as an exception. Processing equipment. 2. A memory access unit for detecting failure in acquisition of a semaphore and completion of release of a semaphore due to execution of a test and set instruction, an exception processing unit for generating an exception according to the information, and generation of the exception. An information processing apparatus, comprising: a register that detects and saves an address on the memory of the semaphore.