JPS6238738B2 - - Google Patents
Info
- Publication number
- JPS6238738B2 JPS6238738B2 JP55104820A JP10482080A JPS6238738B2 JP S6238738 B2 JPS6238738 B2 JP S6238738B2 JP 55104820 A JP55104820 A JP 55104820A JP 10482080 A JP10482080 A JP 10482080A JP S6238738 B2 JPS6238738 B2 JP S6238738B2
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- memory
- program
- stored
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000009499 grossing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Description
【発明の詳細な説明】
本発明はバンクスイツチング方式のメモリにお
いて、割込が発生したときの処理を円滑にする割
込制御方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt control method for smoothing processing when an interrupt occurs in a bank switching type memory.
メモリの構成としてバンクスイツチング方式は
容量を拡大することができるため第１図に示すよ
うに行なわれている。共通部メモリCMMとバン
クメモリBNKとを有し、バンク部については
BNK０，BNK１，……BNKnまでｎ個のバンクが
切替スイツチSWを介してプロセツサCPUと接続
されている。メモリのアドレスの例は16進法で示
すと共通部メモリが“0000”から“0FFF”まで
で、容量は4KB、バンク部メモリのアドレスはそ
れぞれ“1000”から“1FFF”までで、容易は
4KBとなつている。動作プログラムが或バンクに
格納されていて走行中に、入出力装置から割込が
発生した場合、その後の処理は共通部メモリ
CMMに割込制御用プログラムIRCPを格納してお
いて、共通部メモリCMMにジヤンプさせ所定の
制御を行なつていた。これはバンクBNKには割
込処理に関係のないデータが格納されているのみ
で、また処理中のバンクが共通部メモリCMMか
ら見て何番であるか不定であるため、バンク
BNKに割込制御用プログラムIRCPを格納してお
くことはできなかつた。そのため共通部メモリ
CMMのアドレスを入出力装置が多量に使うと
か、割込のときは必ず共通部メモリにジヤンプさ
せ処理を終らせることを要し、メモリ容量が不足
したり、プログラム作成者にとつて不自由さがあ
つた。 As a memory structure, the bank switching method is used as shown in FIG. 1 because it can expand the capacity. It has a common part memory CMM and a bank memory BNK.
n banks BNK0, BNK1, . . . BNKn are connected to the processor CPU via changeover switches SW. Examples of memory addresses are shown in hexadecimal notation: common part memory is from "0000" to "0FFF" and has a capacity of 4KB, bank part memory addresses are from "1000" to "1FFF", and it is easy to
It is 4KB. If an operation program is stored in a certain bank and an interrupt occurs from an input/output device while it is running, subsequent processing will be performed in the common memory.
An interrupt control program IRCP was stored in the CMM, and was jumped to the common memory CMM to perform predetermined control. This is because bank BNK only stores data unrelated to interrupt processing, and the number of the bank being processed from the common memory CMM is uncertain.
It was not possible to store the interrupt control program IRCP in BNK. Therefore, common part memory
If the input/output device uses a large amount of the CMM address, or if an interrupt occurs, it is necessary to jump to the common memory to finish processing, which may cause insufficient memory capacity or be inconvenient for the program creator. It was hot.
本発明の目的は前述の欠点を改善し比較的簡易
な手段で割込まれたときの処理を円滑にし、プロ
グラム作成の自由度を大にできる割込制御方式を
提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt control system that can improve the above-mentioned drawbacks, smoothen processing when an interrupt occurs using relatively simple means, and increase the degree of freedom in program creation.
以下図面に示す本発明の実施例について説明す
る。第２図はメモリに関連する本発明の実施例を
主として示す図である。今ｎ番目のバンクBNKn
に割込制御プログラムIRCPを格納しておく。第
０番目バンクBNK０においてプログラム走行中
（符号）星印の所で割込が発生すると、共通メ
モリCMMにジヤンプする（符号）。共通部メモ
リにある割込用バンク制御プログラムBCPにプロ
グラムカウンタPCが設定され、カウンタの制御
により割込制御プログラムIRCPの格納されてい
るバンクBNKnを選択する。選択結果によりバン
ク切替スイツチSWがｎの位置に切替えられ、バ
スBSの接続を行ない書込み制御プログラムIRCP
へジヤンプする（符号）。ここでバンクBNKn
における割込制御プログラムが終ると、共通部メ
モリCMMの割込用バンク制御プログラムBCPに
戻るようにジヤンプする（符号）。このプログ
ラムBCPの処理において切替スイツチSWを零と
してバンクBNK０と接続し、当初の割込発生点
（星印）へ戻して（符号）割込処理を完了し、
従前のプログラムを続行する。 Embodiments of the present invention shown in the drawings will be described below. FIG. 2 is a diagram mainly showing an embodiment of the present invention related to memory. Now the nth bank BNKn
Store the interrupt control program IRCP in . When an interrupt occurs at the point marked with an asterisk (sign) while the program is running in the 0th bank BNK0, the program jumps to the common memory CMM (sign). A program counter PC is set in the interrupt bank control program BCP in the common part memory, and the bank BNKn in which the interrupt control program IRCP is stored is selected under control of the counter. Depending on the selection result, the bank selection switch SW is switched to the n position, the bus BS is connected, and the write control program IRCP is activated.
Jump to (sign). Bank BNKn here
When the interrupt control program in is completed, it jumps back to the interrupt bank control program BCP of the common part memory CMM (code). In the processing of this program BCP, the changeover switch SW is set to zero, connects to bank BNK0, returns to the original interrupt generation point (star mark), and completes the interrupt processing (sign).
Continue with previous program.
このようにして本発明によるとバンクに割込制
御プログラムを格納してプログラマのプログラム
作成上の制約を除き自由度を増すことができるた
め、装置も使い易くなる等の効果を有する。 In this manner, according to the present invention, it is possible to store an interrupt control program in a bank, thereby removing restrictions on the programmer's program creation and increasing the degree of freedom, thereby making the device easier to use.
第１図は従来のバンクスイツチング方式のメモ
リ構成図、第２図は本発明の実施例を示す図であ
る。
CMM……共通部メモリ、BNK０，BNK１……
バンク部メモリ、SW……切替スイツチ、CPU…
…プロセツサ、IRCP……割込制御用プログラ
ム、BCP……割込用バンク制御プログラム、BS
……バス。
FIG. 1 is a diagram showing the configuration of a conventional bank switching type memory, and FIG. 2 is a diagram showing an embodiment of the present invention. CMM……Common part memory, BNK0, BNK1……
Bank memory, SW...switch switch, CPU...
...Processor, IRCP...Interrupt control program, BCP...Interrupt bank control program, BS
……bus.
Claims (1)
当てられたバンクメモリにより構成され処理プロ
グラムと割込制御プログラムの格納されるメモリ
と、該処理プログラム及び割込制御プログラムに
従つて動作する処理装置と、該処理装置に割込信
号を発生する割込信号発生源とを有し、処理プロ
グラムの遂行中に該割込信号が発生した際、該処
理プログラムの遂行を中止して該割込制御プログ
ラムに従つて、処理装置が割込処理する割込制御
方式において、所定のバンクメモリに該割込処理
プログラムを、該共通部メモリに該割込制御プロ
グラムの格納されるバンクメモリを指定する指定
データを各々格納するとともに、所定のバンクメ
モリに格納されるプログラムを該処理装置が走行
中に割込信号が発生した際該共通部メモリの該指
定データにより該処理装置が遂行するべき割込制
御プログラムの格納されるバンクメモリに該走行
中にあるバンクメモリを切替えさせる手段を具備
し、該割込処理を所定のバンクメモリに格納され
る割込制御プログラムを遂行して行う事を特徴と
する割込制御方式。1. A common part memory, a memory configured with a bank memory to which the same address is assigned and stores a processing program and an interrupt control program, and a processing device that operates according to the processing program and the interrupt control program; The processing device has an interrupt signal generation source that generates an interrupt signal, and when the interrupt signal is generated during execution of the processing program, the execution of the processing program is stopped and the interrupt control program is executed. Therefore, in an interrupt control method in which a processing device processes interrupts, the interrupt processing program is stored in a predetermined bank memory, and the specification data specifying the bank memory in which the interrupt control program is stored is stored in the common memory. At the same time, when an interrupt signal is generated while the processing device is running, the program stored in a predetermined bank memory is executed by the processing device based on the specified data in the common part memory. An interrupt characterized in that the bank memory in which the stored bank memory is stored is provided with means for switching the bank memory currently running, and the interrupt processing is performed by executing an interrupt control program stored in a predetermined bank memory. control method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10482080A JPS5730050A (en) | 1980-07-30 | 1980-07-30 | Interruption control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10482080A JPS5730050A (en) | 1980-07-30 | 1980-07-30 | Interruption control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5730050A JPS5730050A (en) | 1982-02-18 |
| JPS6238738B2 true JPS6238738B2 (en) | 1987-08-19 |
Family
ID=14391030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10482080A Granted JPS5730050A (en) | 1980-07-30 | 1980-07-30 | Interruption control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5730050A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59136860A (en) * | 1983-01-27 | 1984-08-06 | Matsushita Electric Ind Co Ltd | Disk controller |
| JPS60191335A (en) * | 1984-03-13 | 1985-09-28 | Canon Inc | Interruption processing system and its memory cartridge |
| JPS6314241A (en) * | 1986-07-04 | 1988-01-21 | Hitachi Ltd | Memory expansion system |
| US5146581A (en) * | 1988-02-24 | 1992-09-08 | Sanyo Electric Co., Ltd. | Subprogram executing data processing system having bank switching control storing in the same address area in each of memory banks |
| JPH01237732A (en) * | 1988-03-17 | 1989-09-22 | Sharp Corp | Controller |
| JPH0289144A (en) * | 1988-09-26 | 1990-03-29 | Toshiba Corp | Data processor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5384631A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Address assigning system of memory unit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4839836U (en) * | 1971-09-14 | 1973-05-18 |
-
1980
- 1980-07-30 JP JP10482080A patent/JPS5730050A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5384631A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Address assigning system of memory unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5730050A (en) | 1982-02-18 |
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