KR100208281B1 - Peripheral processor in the switching system - Google Patents

Abstract

The present invention provides a subprocessor having a local bus control structure having a local bus and a processor separately for an upper processor and a telephony processor in an exchange system. The lower processor according to the present invention performs a matching process with an upper processor. A main processor for controlling; A first local bus for transmitting address, data and control signals generated by the main processor; An auxiliary processor for controlling a matching process with a telephony device by a control signal of a main processor transmitted through a first local bus; An interface unit for exchanging data and messages of the main processor and data and messages generated from the coprocessor transmitted through the first local bus; And a second local bus for transmitting address, data, and control signals generated by the coprocessor during data registration with the telephony device, and data transmitted from the interface unit. Therefore, it is possible to prevent the degradation of the lower processor due to arbitration when matching with the upper processor or the device.

Description

Subprocessors in Switching Systems

1 is a block diagram of a subprocessor in accordance with the present invention in an exchange system;

* Explanation of symbols for main parts of the drawings

100: first CPU (Central Processing Unit) 101: the first local bus

102: first memory 103: first local controller

104: node matching controller 105: node bus matching unit

106: interface unit 107: second CPU

108: second local bus 109: device control unit

110: second memory 111: second local control unit

112: device matching unit 113: redundancy control unit

114: alarm processing unit 115: external I port

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral processor in an exchange system, and more particularly to a subprocessor having an efficient local bus control structure.

In a conventional exchange system, a lower processor connects an IPC matching processor for matching with a higher processor and a device matching device for matching with a TD (Telephony Device) on one local bus, and transmits data by arbitration using one processor. Configured.

However, in this data transfer process, the matching with the upper processor is made up of a global bus structure, which may cause a heavy load. When the load is severely loaded, a processor provided in the lower processor Due to the arbitration process, the device matching process is relatively delayed.

Accordingly, an object of the present invention is to provide a subprocessor having a local bus control structure in which a local bus and a processor are separately divided for an upper processor and a telephony device in an exchange system. There is a purpose.

In order to achieve the above object, an apparatus according to the present invention will be described in detail below with reference to the accompanying drawings.

1 is a block diagram of a subprocessor according to the present invention in an exchange system, which is a main processor of a subprocessor, in particular a central processing unit (CPU) for controlling overall functions related to registration with a node to which an upper processor is connected; 100, a first local bus 101 for transmitting the address, data and control signals used for node matching, a ROM, a RAM, and a DRAM structure, and a program used for node matching. A first memory 102 for storing data, a first local controller 103 for performing a control process for a local device provided in the subprocessor by a signal transmitted from the first local bus 101 at node matching, The node bus matching unit 105 and the first local bus 101 are configured to perform matching processing with higher-level processors (not shown) connected to the node bus. The node matching controller 104 for controlling node matching according to the control signal of the first CPU 100, the second CPU 107 for controlling the overall function related to the TD (Telephony Device, hereinafter abbreviated as TD) matching, and the TD matching. The second local bus 108, ROM, RAM, and DRAM structure for transmitting the address, data and control signals used in the process, the second memory 110, TD for storing the program and data generated during TD matching The second local control unit 111 and the second local bus 108 which are transmitted through the second local bus 108 to control the local device included in the lower processor by the signal transmitted from the second local bus 108 during matching. The device matching controller 112 and the dual port RAM (DPRAM) for controlling device matching according to the control signal of the 2 CPU 107 are implemented to provide data and messages between the first local controller 103 and the second local controller 111. Exchange for It consists of the interface unit 106, the local device, the redundancy controller 113, the alarm processing unit 114 and external I port 115 in the sub-processor to. Here, the message between the first local control unit 103 and the second local control unit 111 transmitted through the interface unit 106 is composed of a message for status management (for example, a message indicating an abnormal state occurrence), and the data Consists of signals that require TD matching and higher processor matching processing.

The operation of the subprocessor configured as described above is performed as follows.

First, when matching with other processors through the node bus (here, the upper processor), the first CPU 100 which is the main processor of the lower processor is a signal for matching to the node matching controller 104 through the first local bus 101. Send it. The node matching controller 104 controls the node bus matching unit 105 according to the transmitted control signal to perform matching processing with an upper processor (not shown).

At this time, a necessary program is supplied from the first memory 102, and a signal, which is required to be stored, of data generated during the matching process is stored in a predetermined area of the first memory 102. In addition, various local functions (eg, alarm collection, board status management, inter-bus information processing, interrupt processing, redundancy management, etc.) required in the matching process with the upper processor (not shown) are the first local bus. The first local control unit 103 is controlled and processed through the reference numeral 101. When data exchange with the TD is required in the matching process with the upper processor, the first CPU 100 exchanges data with the interface unit 106 through the first local bus 101 and the first local control unit 103. .

The interface unit 106 exchanges data and messages to be transmitted between the first local control unit 103 and the second local control unit 111 to be described later. As described above, the interface unit 106 exchanges data from the first local control unit 103. When the request signal is transmitted to the second local control unit 111. At this time, if a message indicating that an abnormality has occurred in the TD matching is transmitted from the second local controller 111, the interface unit 106 transmits to the first local controller 103 so that the first CPU 100 has an abnormal state in the TD matching. To recognize that a has occurred.

When there is no abnormality in TD matching, the second local controller 111 transmits the data transmitted from the interface unit 106 to the second CPU 107 through the second local bus 108. The second CPU 107 is a subprocessor of the subprocessor which performs all control processing performed by the subprocessor during the matching process with the TD. When the TD matching request signal is transmitted, the second CPU 107 transmits an address for TD matching to the second local bus 108. Output data and control signals.

The second local bus 108 transmits a signal output from the second CPU 107 to the device controller 109. The device control unit 109 controls the device matching unit 112 to perform a matching process with the TD.

The second memory 110 stores a program necessary for the TD matching process and stores data generated by the request of the second CPU 107 or generated during the matching process, and the second local controller 111. ) Controls a local device in the lower processor or transmits a higher processor matching request signal and a TD matching status management message, such as the first local control unit 103 described above, by a control signal transmitted from the second local bus 108. Play a role.

As described above, according to the present invention, the local bus and the processor provided in the subprocessor of the exchange system are independently configured for the upper processor and the device, and operated independently, so that the lower processor due to arbitration during the matching process with the upper processor or the device There is an effect that can prevent the performance degradation.

Claims (2)

A subprocessor having a matching function with an upper processor and a telephony device in a switching system, the lower processor comprising: a main processor for controlling a matching process with the upper processor; A first local bus for transmitting address, data, and control signals generated by the main processor; An auxiliary processor for controlling a matching process with the telephony device according to a control signal of the main processor transmitted through the first local bus; An interface unit for exchanging data and messages of the main processor and data and messages generated from the coprocessor, transmitted through the first local bus; And a second local bus for transmitting address, data and control signals generated by the coprocessor and data transmitted from the interface unit during the matching process with the telephony device. . The processor of claim 1, wherein the lower processor comprises: a first local controller configured to perform local control processing required for matching processing between the first local bus and the interface unit with the upper processor; A first memory for storing a program used in the matching process with the upper processor and data generated; A second local controller configured to perform local control processing required for the matching process with the telephony device between the interface unit and the second local bus; And a second memory for storing a program and data to be used during a matching process with the telephony device.