KR940017549A - Message transmission method in signal bus matching board connected to signal terminal network of all electronic switch - Google Patents

Message transmission method in signal bus matching board connected to signal terminal network of all electronic switch Download PDF

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Publication number
KR940017549A
KR940017549A KR1019920026065A KR920026065A KR940017549A KR 940017549 A KR940017549 A KR 940017549A KR 1019920026065 A KR1019920026065 A KR 1019920026065A KR 920026065 A KR920026065 A KR 920026065A KR 940017549 A KR940017549 A KR 940017549A
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South Korea
Prior art keywords
transmission
signal
message
chip
controller
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KR1019920026065A
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Korean (ko)
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KR950010483B1 (en
Inventor
임옥수
정부금
조주현
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양승택
재단법인 한국전자통신연구소
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Publication of KR940017549A publication Critical patent/KR940017549A/en
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Publication of KR950010483B1 publication Critical patent/KR950010483B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 전전자 교환기의 주프로세서 및 종속프로세서로 구성되는 공통선 신호 메시지 처리부에서 전송 요구된 사용자 메시지들을 내부 프로토콜 없이 신호단말망을 통해 다른 신호단말 프로세서들로 송신하는 방법에 관한 것이다.The present invention relates to a method for transmitting user messages required for transmission in a common line signal message processing unit consisting of a main processor and a subordinate processor of an electronic switching system to other signal terminal processors through a signal network without an internal protocol.

본 발명은 전전자 교환기의 신호단말기 망에 접속된 신호메시지 처리 프로세서(SMHP)와 그룹화되는 다수의 신호단말제어보드(STCA)들이 상호 통신을 할때 신호처리프로세서에서 타 신호제어 단말보드들로 메시지 송신을 신뢰성 보장과 함께 최단 시간내에 수행 완료하게 하는 메시지 송신 방법을 제공한다.According to the present invention, when a plurality of signal terminal control boards (STCA) grouped with a signal message processing processor (SMHP) connected to a signal terminal network of an electronic switchgear communicate with each other, a message is transmitted from a signal processor to other signal control terminal boards. Provided is a message transmission method that allows transmission to be completed in the shortest time with reliability guarantee.

Description

전전자교환기의 신호단말망에 접속된 신호버스정합보드에서의 메시지 송신 방법Message transmission method in signal bus matching board connected to signal terminal network of all electronic switch

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 송신측 전체 흐름도 및 송신측 초기화 흐름도, 제 3 도는 송신 정합 및 처리 및 송신 구동기 흐름도, 제 4 도는 송신측 통신칩 인터럽트 구동기 흐름도, 제 5 도는 송신측 타임아웃 인터럽트 구동기 흐름도.2 is a flow diagram of a transmission side overall and a flow diagram of a transmission initialization; FIG. 3 is a flow diagram of a transmission matching and processing and transmission driver; FIG. 4 is a flow diagram of a transmission chip interrupt driver;

Claims (1)

중앙처리장치(4), 공유기억장치(5). 국부기억장치(6), DMA제어기(7), 다중프로토콜 통신제어기(8), 다기능주변제어기(9),FIFO(10)를 구비한 전전자교환기의 신호버스정합보드(3 : SBIA)에 적용되는 메시지송신방법에 있어서, 공유기억장치(5)의송신큐를 순환방식으로 운영하면서 메시지 태그와 송신 칩의 유휴상태에 따라 송신을 결정하는 제 1 단계(11 내지 14)와,상기 제 1 단계(11 내지 14) 수행후, 송신 칩이 유휴이고 전송할 메시지가 존재하는 경우 DMA제어기(7)을 구동함과 동시에 송신측 전송 두절을 막기 위해 타임아웃을 설정하는 제 2 단계(20 내지 23)와, 상기 제 2 단계(20 내지 23) 수행후,다중프로토콜 통신제어기(8)의 전송완료후 타임아웃 카운터를 정지하고 송신상에 에러가 발생했을때 송신측 칩을 복구시키고 재전송을 위한 절차를 수행한뒤 칩의 상태를 유휴로 두는 제 3 단계(40 내지 47)와, 상기 제 2 단계(20 내지 23) 수행후, DMA제어기(7)의 이상 및 다중프로토콜 통신제어기(8) 이상현상으로 송신이 진행중이거나 이상 상태에 있는 경우 다기능주변제어기(9)의 타임아웃에 의해 송신 칩을 복구시키고 재전송을 위한 절차를 수행한뒤 칩의 상태를 유휴로 두는 제4 단계(50 내지 54)를 구비하여 수행되는 것을 특징으로 하는 메시지 송신방법.Central processing unit (4), shared storage unit (5). Applied to the signal bus matching board (3: SBIA) of all electronic switchboards having local memory (6), DMA controller (7), multiprotocol communication controller (8), multifunction peripheral controller (9), and FIFO (10). In the message transmission method, the first step (11 to 14) to determine the transmission in accordance with the idle state of the message tag and the transmission chip while operating the transmission queue of the shared storage device 5 in a circular manner, and the first step After performing (11 to 14), when the transmitting chip is idle and there is a message to be transmitted, the second step (20 to 23) of driving the DMA controller 7 and setting a timeout to prevent transmission side transmission loss at the same time; After the second steps 20 to 23 are performed, the timeout counter is stopped after the transmission of the multiprotocol communication controller 8 is completed, and when an error occurs in the transmission, a procedure for recovering the transmitting chip and performing retransmission is performed. And a third step (40 to 47) of leaving the state of the chip idle. After performing the second steps 20 to 23, if the transmission is in progress or abnormal due to the abnormality of the DMA controller 7 and the multi-protocol communication controller 8, the time-out of the multifunction peripheral controller 9 may occur. And a fourth step (50 to 54) of restraining the state of the chip after restoring the transmitting chip and performing a procedure for retransmission. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920026065A 1992-12-29 1992-12-29 The method transmitting a message for an electronic exchanger KR950010483B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026065A KR950010483B1 (en) 1992-12-29 1992-12-29 The method transmitting a message for an electronic exchanger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026065A KR950010483B1 (en) 1992-12-29 1992-12-29 The method transmitting a message for an electronic exchanger

Publications (2)

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KR940017549A true KR940017549A (en) 1994-07-26
KR950010483B1 KR950010483B1 (en) 1995-09-18

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KR1019920026065A KR950010483B1 (en) 1992-12-29 1992-12-29 The method transmitting a message for an electronic exchanger

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100293363B1 (en) * 1997-12-27 2001-07-12 박종섭 Method for managing inter processor communication transmission queue of processor communication controller board assembly in full electronic telephone exchange
CN117956054A (en) * 2024-03-26 2024-04-30 上海云豹创芯智能科技有限公司 Method, system, chip and storage medium for realizing timer processing in RDMA
CN117956054B (en) * 2024-03-26 2024-06-11 上海云豹创芯智能科技有限公司 Method, system, chip and storage medium for realizing timer processing in RDMA

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100293363B1 (en) * 1997-12-27 2001-07-12 박종섭 Method for managing inter processor communication transmission queue of processor communication controller board assembly in full electronic telephone exchange
CN117956054A (en) * 2024-03-26 2024-04-30 上海云豹创芯智能科技有限公司 Method, system, chip and storage medium for realizing timer processing in RDMA
CN117956054B (en) * 2024-03-26 2024-06-11 上海云豹创芯智能科技有限公司 Method, system, chip and storage medium for realizing timer processing in RDMA

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KR950010483B1 (en) 1995-09-18

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