KR950022514A - Communication port control method of a single processor communicating with a plurality of systems and apparatus therefor - Google Patents

Communication port control method of a single processor communicating with a plurality of systems and apparatus therefor Download PDF

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Publication number
KR950022514A
KR950022514A KR1019930030064A KR930030064A KR950022514A KR 950022514 A KR950022514 A KR 950022514A KR 1019930030064 A KR1019930030064 A KR 1019930030064A KR 930030064 A KR930030064 A KR 930030064A KR 950022514 A KR950022514 A KR 950022514A
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KR
South Korea
Prior art keywords
message
transmission
reception
input
interrupt
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KR1019930030064A
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Korean (ko)
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KR0143970B1 (en
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이현철
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정장호
금성정보통신 주식회사
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Priority to KR1019930030064A priority Critical patent/KR0143970B1/en
Publication of KR950022514A publication Critical patent/KR950022514A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques

Abstract

본 발명은 전자교환기 시스템의 프로세서에 관한 것으로, 단일 프로세서의 모듈이 복수개의 프로세서와 통신하는 경우 상대 프로세서의 수보다 적은 입출력수단 및 DMA수단을 이용하여 신뢰성있는 통신 프로토콜을 수행하도록 한 것이다. 본 발명은 시간관리 프로세서에 의한 선로의 관리로 원활한 통신포트 운용을 확보하고 통신 선로의 이상으로 인한 메시지의 블럭현상 및 교착상태로의 진입을 배제하며 적은 하드웨어의 사용으로 소형화 경량화되고 설치공간을 효율적으로 사용한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor of an electronic exchange system, wherein a module of a single processor communicates with a plurality of processors so as to perform a reliable communication protocol using fewer input / output means and DMA means than the number of counterpart processors. The present invention ensures smooth communication port operation by managing the line by the time management processor, eliminates the block phenomenon of the message due to the error of the communication line and entry into the deadlock state, and reduces the size and weight of the installation by using less hardware and saves the installation space. Used as

Description

복수의 시스템과 통신하는 단일 프로세서의 통신포트제어방법 및 그 장치Communication port control method of a single processor communicating with a plurality of systems and apparatus therefor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 단일프로세서의 복수 통신포트 접속장치 구조도.1 is a structure diagram of a plurality of communication port connection device of a single processor according to the present invention.

제2도는 본 발명에 따른 DMA(Direct Memory Access)부의 인터럽트 처리 흐름도.2 is a flowchart of interrupt processing of a direct memory access (DMA) unit according to the present invention;

제3도는 본 발명에 따른 SIO(Serial Input/Output)부의 인터럽트 처리 흐름도.3 is an interrupt processing flowchart of a SIO (Serial Input / Output) unit according to the present invention.

Claims (4)

전자교환기 시스템의 통신방법에 있어서, 비가용 상태에 있는 모든 통신포트를 가용상태로 전환시키고 해당 포트가 사용할 최대 통신 허용시간을 설정한 후 상기 해당 포트를 통해 메시지를 송수신하는 제1과정과, 상기 제1과정 수행후 입출력 수단을 통해 상대측 시스템으로 메시지가 전송되고 상기 상대측 시스템으로부터 전송된 메시지에 대응되는 메시지의 수신이 완료되면 이를 통보하는 인터럽트를 발생하는 제2과정과, 상기 제2과정 수행후 발생된 인터럽트가 정상적인 인터럽트 인지의 여부를 판단하기 위해 전송완료 플러그가 리셋되었는가를 검출하는 제3과정과, 상기 제3과정 수행후 대국측으로부터 메시지가 수신되면 입출력 수단은 제어수단측에 이를 통보하기 위하여 인터럽트를 발생시키는 제4과정과, 상기 제4과정 수행후 인터럽트가 발생하면 상기 제1과정에서 설정된 최대통신 허용시간을 리셋시키는 제5과정 및, 상대측 시스템으로부터 상기 제1과정에서 설정된 최대 통신허용 시간내에 응답메시지의 수신이 없으면 선택된 해당포트를 초기화시키는 제6과정을 포함하는 것을 특징으로 하는 복수의 시스템과 통신하는 단일 프로세서의 통신포트 제어방법.A communication method of an electronic switching system, comprising: a first process of switching all communication ports in an unavailable state to an available state, setting a maximum communication allowable time for the corresponding port, and transmitting and receiving a message through the corresponding port; After performing the first process, a message is transmitted to the counterpart system through the input / output means, and a second step of generating an interrupt for notifying when the reception of the message corresponding to the message transmitted from the counterpart system is completed; A third step of detecting whether the transmission completion plug is reset to determine whether or not the generated interrupt is a normal interrupt; and if the message is received from the power station after performing the third step, the input / output means notifies the control means. A fourth process for generating an interrupt for performing the A fifth process of resetting the maximum communication allowable time set in the first process, and a sixth process of initializing the selected corresponding port if no response message is received within the maximum communication allowable time set in the first process from the counterpart system. Communication port control method of a single processor for communicating with a plurality of systems comprising a. 제1항에 있어서, 상기 제1과정은 입출력수단 및 멀티플랙싱 스위치수단의 송수신을 위한 해당 접점 포트를 동작모드로 리셋시키는 단계와, 상기 단계 수행후 상기 해당 접점포트의 DMA수단 전송동작이 증복되지 않았는가를 확인하기 위하여 DMA수단을 전송동작 완료 플러그를 세트하고 입출력수단을 통해 대국측으로 메시지를 수신하기 위해 수신완료 플러그를 세트시키는 단계를 포함하는 것을 특징으로 하는 복수의 시스템과 통신하는 단일 프로세서의 통신포트 제어방법.The method of claim 1, wherein the first process comprises the steps of: resetting the corresponding contact port for the transmission / reception of the input / output means and the multiplexing switch means to the operation mode, and the DMA means transfer operation of the corresponding contact port is increased after performing the step. And a step of setting the transfer completion plug in the DMA means to check whether it has not been set, and setting the received completion plug to receive the message to the counterpart through the input / output means. Communication port control method. 제1항에 있어서, 상기 제3과정에서 비정상적인 인터럽트의 발생으로 판단되면 DMA수단은 비정상 인터럽트 발생을 통보하는 플러그를 세트하며 메인프로세서 수단은 이에 적절한 루틴을 수행하는 단계와, 정상적인 인터럽트의 발생으로 판단되면 정상적인 송신으로 판단하여 DMA수단을 전송완료 플러그를 세트하고 입출력수단은 수신완료 플러그를 리셋한 후 송신버퍼를 갱신하는 단계를 포함하는 것을 특징으로 하는 복수의 시스템과 통신하는 단일 프로세서의 통신포트 제어방법.The method of claim 1, wherein if it is determined that an abnormal interrupt is generated in the third process, the DMA means sets a plug for notifying the occurrence of the abnormal interrupt, and the main processor means performs an appropriate routine thereto and determines that the normal interrupt is generated. If it is determined that the transmission is normal, the DMA means sets the transmission completion plug, and the input / output means resets the reception completion plug, and then updates the transmission buffer. Way. 전자교환기 시스템에 있어서, 시스템 전체의 메시지 송수신에 대한 프로토콜을 제어하는 제어수단과, 상기 송수신에 대한 메시지를 저장하는 저장수단, 상기 송수신에 대한 메시지를 저장하는 저장수단과, 상기 제어수단의 제어신호에 따라 스위칭되어 송수신 접점포트를 접속하는 멀티플랙싱 스위치수단과, 상기 접속된 송수신 접점포트를 통해 메시지를 송수신하는 입출력 수단 및 상기 입출력수단을 통해 송수신 데이타를 구동시키는 DMA수단을 구비하는 것을 특징으로 하는 복수의 시스템과 통신하는 단일 프로세서의 통신포트 제어장치.An electronic switching system comprising: control means for controlling a protocol for message transmission and reception of a system, storage means for storing a message for transmission and reception, storage means for storing a message for transmission and reception, and a control signal of the control means And multiplexing switch means switched according to the connection, and connecting and receiving contact ports, input and output means for transmitting and receiving messages through the connected transmitting and receiving contact ports, and DMA means for driving transmission and reception data through the input and output means. Communication port control device of a single processor for communicating with a plurality of systems. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930030064A 1993-12-27 1993-12-27 Telecommunication part control system KR0143970B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100995025B1 (en) * 2002-12-09 2010-11-19 엘지전자 주식회사 method for connecting communication port between server and client

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100995025B1 (en) * 2002-12-09 2010-11-19 엘지전자 주식회사 method for connecting communication port between server and client

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