KR0143970B1 - Telecommunication part control system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor of an electronic exchange system, wherein a module of a single processor communicates with a plurality of processors so as to perform a reliable communication protocol by using an input / output means and a DMA means less than the number of counterpart processors.

The present invention ensures smooth communication port operation by managing the line by the time management processor, eliminates the block phenomenon and the entry into the deadlock state due to the error of the communication line, miniaturization, light weight and efficient installation space using less hardware. Used as

Description

Communication port control method of a single processor communicating with a plurality of systems and apparatus therefor

1 is a structure diagram of a plurality of communication port connection device of a single processor according to the present invention.

2 is a flowchart illustrating interrupt processing of a DMA (Direct Menory Access) unit according to the present invention.

3 is an interrupt processing flow diagram of a serial input / out put (SIO) unit according to the present invention.

4 is a flow chart of a processor timeout in accordance with the present invention.

* Description of the symbols for the main parts of the drawings *

1: CPU 2: Memory section

3: first DMA 4: first SIO

5: second DMA 6: second SIO

7: First multiplexing switch section 8: Second multiplexing switch section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor of an electronic exchange system, and in particular, when a module of a single processor communicates with a plurality of processors, communicating with a plurality of systems for performing a reliable communication protocol using an input / output means less than the number of counterpart processors A communication port control method of a single processor and an apparatus thereof are provided.

In general, the electronic exchange system is provided with a plurality of communication ports provided with input / output means as many as the number of communication ports and direct channel access (DMA) means with the same number of channels in order to communicate with the counterpart system. In this case, all the control regarding the transmission and reception is performed by the central processing unit to perform communication by making the communication ports available sequentially so as to prevent the loss of messages simultaneously transmitted and received from the plurality of communication ports. Such communication is performed by enabling the communication channel of the SIO for the port that the central processing unit needs to communicate with, and then transmitting the message transmission request data to the counterpart and expecting a response message for a predetermined time. If a response message for the transmission request data is received at a predetermined time, the transmission sequence is transferred to the next port. If no response message is received within the predetermined time, the message is re-transmitted a predetermined number of times.

If the message is not transmitted due to the abnormality of the line or the abnormal status of the other station while receiving the message by the start flag when the message is transmitted by the flag indicating the start and end of the received message, the module does not transmit or receive the deadlock. -Lock) state is entered. Also, for other reasons, the port that is available by the status information indicating that the message is being received gives up access to further message reception when the status information on the port being available is left and the processing such as interrupt is returned.

As described above, the conventional message transmitting / receiving protocol apparatus requires space for a complex configuration such as a common data transmission bus, a bus occupancy controller, a control signal generator, and a node matching unit regardless of the number of modules. For a small processor, there was an uneconomic problem.

In addition, there is a problem in that each port can not be prevented from entering a deadlock state that can not transmit a message when sending and receiving messages.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to ensure smooth operation of a communication port by using SIO means and DMA means which are smaller than the number of communication ports when a single processor module communicates with a plurality of systems. The operation of the management processor prevents the entry of deadlocks of incoming and outgoing messages due to abnormal conditions on the line and makes the system smaller and lighter.

In order to achieve the above object, the present invention relates to a communication method of an electronic switching system, wherein all communication ports in an unusable state are switched to an available state, and the corresponding port is set after setting a maximum communication allowable time for the corresponding port. A first process of transmitting and receiving a message through the first process, and generating an interrupt for notifying when the message is transmitted to the counterpart system through the input / output means after the first process is performed and the reception of the message corresponding to the message transmitted from the counterpart system is completed. And a third step of detecting whether the transmission completion flag is reset to determine whether the interrupt generated after performing the second step is a normal interrupt, and receiving a message from the counterpart after performing the third step. The input / output means generates an interrupt to notify the control means of this. Receiving the response message within the maximum communication allowance time set in the first process from the fifth process and the fifth process of resetting the maximum communication allowable time set in the first process if an interrupt occurs after performing the fourth process and the fourth process. If not there is provided a communication port control method of a single processor for communicating with a plurality of systems, characterized in that it comprises a sixth process of initializing the selected corresponding port.

The present invention also provides an electronic exchange system comprising: control means for controlling protocol processing for message transmission and reception; Storage means for storing transmission and reception messages; Multiplexing switch means for switching under a control of the control means to connect a transmission / reception port for a power station to input / output a message transmitted to or received from the power station; Input / output means for transmitting and receiving a message to and from the large station through the multiplexing switch means by transmitting and receiving a message to and from the multiplexing switch means via a channel selected by the control means; And a DMA means for directly transmitting and receiving messages to and from the storage means by means of the control means to transmit and receive messages to and from the storage means and to transmit and receive messages between the storage means and the input / output means. It provides a communication port control device of a single processor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a structure diagram of a plurality of communication port connection apparatus of a single processor according to the present invention, FIG. 2 is an interrupt processing flowchart of the DMA unit according to the present invention, and FIG. 3 is an interrupt processing flowchart of the SIO unit according to the present invention. 4 is a flowchart of a timeout of a processor according to the present invention.

As can be seen from FIG. 1, the present invention includes a CPU 1, a memory unit 2, a first DMA 3, a first SIO 4, a second DMA 5, and a second SIO. (6), the first multiplexing switch section 7 and the second multiplexing switch 8.

The CPU 1 controls protocol processing for message transmission and reception of the entire system. The memory unit 2 stores a program for transmitting and receiving protocol processing, a message to be transmitted, and a received message. The first and second DMAs 3 and 5 directly access the memory unit 2 according to the instruction of the CPU 1, and input and receive messages to and from the memory unit 2 to thereby output the first and second SIOs 4. , 6) transmits and receives messages. The first and second SIOs 4 and 6 select a channel under the control of the CPU 1 and transmit and receive a message through the first and second multiplexing switch units 7 and 8. The first and second multiplexing are performed. The message received through the switch unit 7, 8 is output to the first and second DMAs 3 and 5, and the message applied from the first and second DMAs 3 and 5 is first and second multiplexed. Transmission is performed via the switch units 7 and 8. The first and second multiplexing switch units 7 and 8 are switched under the control of the CPU 1 to connect the transmission / reception ports for the large stations to input and output messages transmitted to and received from the large stations.

An operation of the transmission and reception protocol of the present invention configured to have such a function will be described.

As can be seen in FIG. 4, when the CPU 1 generates a timeout signal when all ports are initially unavailable (step 30), the corresponding port is reset to the operation mode (step 31) and the predetermined time is reached. In accordance with the control signal applied from the CPU 1, the transfer operation completion flag of the first and second DMAs 3 and 5 for each port and the reception completion flag of the first and second SIOs 4 and 6 are set. After setting to (Set) state (step 32), the operation returns to the state (step 33). At this time, when the CPU 1 transmits a message allowing the message to be sent to the other party, the CPU 1 checks whether the transfer operation of the first DMA 3 or the second DMA 5 to the corresponding port is duplicated. Reception completion to confirm that the first DMA 3 or the second DMA 5 transfer operation completion flag is set, and to confirm that the first SIO 4 or the second SIO 6 is also not in the reception state. After checking the set state of the flag, the first multiplexing switch unit 7 or the second multiplexing switch unit 8 is switched to receive the message from the counterpart side, so that the first SIO 4 or the second SIO is switched. A message is transmitted through the transmission channel of the first SIO 4 or the second SIO 6 by switching the reception channel of (6) and the first DMA 3 or the second DMA 5 linked with the channel to a reception state. Send it. At this time, the CPU 1 sets the transfer completion flag of the first DMA 3 or the second DMA 5 to the reset state and sets the maximum communication allowable time to be used by the corresponding port.

The first DMA 3 or the second DMA 5 and the first SIO 4 or the second SIO 6 are then contacted through the contacts of the first multiplexing switch unit 7 or the second multiplexing switch unit 8. The message is sent to the system side, and a message corresponding to the message is received from the counterpart system side. When the reception of the message is completed, as shown in FIG. 2, the first DMA 3 or the second DMA 5 completes the transmission and generates an interrupt for notifying it (step 10). When an interrupt is generated, it is determined whether the first DMA 3 or the second MDA 5 is in the transmission mode in order to confirm whether the interrupt occurs when the first DMA 3 or the second MDA 5 is in a normal state (step). 11).

If it is determined in step 11 that the transmission mode is not in the transmission mode, it is processed as an abnormal interrupt and the first DMA 3 or the second MDA 5 sets a flag for notifying occurrence of abnormal interrupt and stops the transmission operation (step 13). At this time, the CPU 1 performs a processing operation corresponding thereto.

If it is determined in step 11 that the transmission mode is normal, a transmission completion flag indicating that the first DMA 3 or the second MDA 5 has normally transmitted a message is set, and the first SIO 4 or the second SIO 6 is set. In order to notify that is in the reception state, the SIO reception completion flag is reset and terminated, and then the transmission buffer is updated (step 12). In this state, the message has been normally transmitted to the counterpart side, and the host waits for a reception message to arrive within a predetermined time set from the counterpart side. If the message transmitted from the station side is normally received in the reception channel of the first SIO 4 or the second SIO 6, the first SIO 4 or the second SIO 6 notifies the CPU 1 of this. As shown in FIG. 3, an SIO interrupt is generated (step 20). If an SIO interrupt occurs, it is determined whether or not an error for transmission / reception has occurred (step 21). If an error occurs, the error processing counter is incremented (step 25) and the error processing counter is terminated. If it is determined that normal reception has not occurred, it is determined whether the reception of the message has been completed (step 22). When the reception is completed, the timer set to the maximum allowable time value of the communication is reset, the SIO reception completion flag is set, the buffer to be used next is specified, and the process ends (step 23).

If the reception is not completed and an error, for example, a CRC error, etc. occurs, the reception completion flag is reset (step 24). Then, the CPU 1 increments a counter for handling the generated error (step 25).

If the message waits for a response message from the other party and the transmission of the message is terminated because the maximum wait time has elapsed, as shown in FIG. 4, the first SIO 4 or the second SIO 6 and the first DMA of the port are shown. (3) Alternatively, the second DMA 5 is reset so that it can be used next time (step 31), and the transfer operation completion flag of the first DMA 3 or the second DMA 5 is set and the first SIO 4 is set. Alternatively, the reception completion flag of the second SIO 6 is set (step 32) to initialize the port itself until the next turn.

Therefore, the block phenomenon and deadlock of the message caused by expecting a random response message are prevented.

As described above, in the present invention, when a single processor module communicates with a plurality of systems, the operation of the communication port is facilitated by using SIO or DMA less than the number of communication ports. It is useful to save space because the system is light and small by using SIO and DMA.

Claims (4)

A communication method of an electronic switching system, comprising: a first process of switching all communication ports in an unavailable state to an available state, setting a maximum communication allowable time for the corresponding port, and transmitting and receiving a message through the corresponding port; A second process of generating an interrupt for notifying when a message is transmitted to the counterpart system through the input / output means and receiving the message corresponding to the message transmitted from the counterpart system after the first process is performed, and after performing the second process A third step of detecting whether the transmission completion flag is reset to determine whether or not the generated interrupt is a normal interrupt; and if the message is received from the power station after performing the third step, the input / output means notifies the control means. A fourth process for generating an interrupt for performing the A fifth process of resetting the maximum communication allowable time set in the first process when the first process occurs; and a sixth process of initializing the selected corresponding port if no response message is received within the maximum communication allowable time set in the first process from the counterpart system. Communication port control method of a single processor for communicating with a plurality of systems comprising a. The method of claim 1, wherein the first process comprises the steps of: resetting the corresponding contact port for the transmission and reception of the input / output means and the multiplexing switch means to the operation mode, and whether the DMA means transfer operation of the corresponding contact port is not duplicated after performing the step. And setting a reception completion flag to receive a message from the power supply side via the input / output means to confirm the communication with a single processor. Port control method. The method of claim 1, wherein if it is determined that an abnormal interrupt has occurred in the third process, the DMA means sets a flag for notifying the occurrence of the abnormal interrupt, and the main processor means performs a processing routine corresponding thereto, and generates a normal interrupt. If it is determined that the normal transmission, the DMA means sets the transmission completion flag, and the input and output means for updating the transmission buffer after resetting the reception completion flag, the communication of a single processor to communicate with a plurality of systems Port control method. An electronic exchange system comprising: control means for controlling protocol processing for message transmission and reception; Storage means for storing transmission and reception messages; Multiplexing switch means which is switched under the control of the control means and connects a transmission / reception port for the power station to input / output a message transmitted / received to the power station; Input / output means for transmitting and receiving a message to and from the large station through the multiplexing switch means by transmitting and receiving a message to and from the multiplexing switch means via a channel selected by the control means; And a DMA means for directly transmitting and receiving messages to and from the storage means by means of the control means to transmit and receive messages to and from the storage means and to transmit and receive messages between the storage means and the input / output means. Communication port control device of a single processor.