KR20010020005A - Error repair and initialize apparatus of cell bus interface - Google Patents

Abstract

PURPOSE: An apparatus for restoring error and initializing in cell bus interface is provided to implement error restoring and initializing process generated in cell bus interface between control boards easily and rapidly and apply it to large volume of system easily. CONSTITUTION: A cell bus error monitor(130,230) determines which error is generated in cell bus and inform an interrupt processing part of error generation. The interrupt processing part(120,220) request interrupts for main controller depending on current error states. The main controller(310,410) certificates the error states through state values from the interrupt processing part. One or more control boards(100,200) make a cell bus controller(320,420) execute initialization of cell bus reset controller(150,250). One or more clock boards(300,400) transmits an initialization signal to the control boards. The clock boards have the cell bus controller which transmits the initialization signal the cell bus error monitor by main controller.

Description

Error repair and initialize apparatus of cell bus interface

The present invention relates to an error recovery and initialization device of a cell bus interface, and more particularly, an error of a cell bus interface for implementing error recovery and initialization that occurs while performing a cell bus interface between internal control boards of a DSLAM system, which is an ADSL device. It relates to a recovery and initialization device.

As is well known, ADSL (Asymmetric Digital Subscriber Line) is a technology that realizes asymmetrical communication of 1.5Mbit / sec downward and 16Kbit / sec upward from the telephone company to the home using the existing telephone line. It is a high-speed communication technology that can coexist with existing telephone and integrated service digital network (ISDN) basic interface (2B + D) by line.

On the other hand, the conventional DSLAM (DSL Access Multiplexer) system, which is an equipment for implementing such an ADSL, can recover from error recovery and initialization during the execution of the cell bus interface between various internal control boards such as CSMB, CSUB, and CSDB. The device for implementation was not designed.

Therefore, since there is no method of detecting and transmitting an error generated while performing the cell bus interface to the operation management system, the operation management system periodically reads the operation state of the DSLAM system in a polling manner and there is no M & A response signal. The DSLAM system operator was able to initialize the cell bus interface through a system reset process that powers the system on and off.

However, in the prior art of initializing the cell bus interface as described above, repair and initialization time for errors occurring during the execution of the cell bus interface is very delayed, and the operation thereof is inconvenient. It was not possible to apply conventional cell bus interface initialization techniques.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, the object of which is to quickly and easily implement the error recovery and initialization operations generated during the cell bus interface between the internal control board of the ADSL equipment DSLAM system It is an object of the present invention to provide an error recovery and initialization device for a cell bus interface that can be easily applied to a system.

1 is a control block diagram showing a preferred embodiment of the error recovery and initialization device of a cell bus interface according to the present invention;

<Description of the code | symbol about the principal part of drawing>

100,200: control board 110,210: main fisherman

120,220: interrupt processing unit 130,230: cell bus error monitoring unit

140,240: cell bus controller 150,250: cell bus reset controller

300,400: Clock board 310,410: Main control part

320,420: cell bus controller 330,430: cell bus clock board monitoring unit

The feature of the error recovery and initialization device of the cell bus interface according to the present invention for achieving the above object is to determine the abnormality of the cell bus through the cell bus error monitoring unit and to notify the interrupt processing unit when an error occurs, the interrupt processing unit Requests the interrupt to the main control unit according to the current error state, and the main control unit checks the error state through the status value of the interrupt processing unit and makes an exception to cause the cell bus control unit to initialize the cell bus reset controller. At least one control board, and at least one clock board for transmitting an initialization signal to the control board.

The clock board may further include a cell bus controller which transmits an initialization signal to the cell bus error monitor of the control board when the initial power is applied.

In addition, the clock board inputs a cell bus clock board monitor for transmitting a current status signal to another clock board when a cell bus error occurs while one clock board is active, and a status signal of the cell bus clock board monitor. And a main controller to transmit an initialization signal to the control board through a cell bus controller.

The control board transmits a status signal to the other control board through the cell bus controller and transmits an initialization signal to the cell bus reset controller when the initialization operation is determined from the main controller. The cell bus error monitoring unit may be configured to initialize the cell bus reset controller according to the status signal.

Therefore, the error recovery and initialization work occurring during the cell bus interface between the internal control boards of the DSLAM system, which is ADSL equipment, is performed according to the cell bus initialization operation according to the initial power-up of the CSHK, and the transfer between the first clock board and the second clock board. It can be quickly and easily implemented through various operations such as cell bus initialization operation and cell bus initialization operation by the CSMB board itself, and thus can be easily applied to a large capacity system.

Hereinafter, with reference to the accompanying drawings a preferred embodiment of the error recovery and initialization device of the cell bus interface according to the present invention will be described in detail, the present invention is a device corresponding to each of the CSHK and MSHK of the DSLAM system, here for convenience CSHK Explain only.

1 is a control block diagram illustrating an exemplary embodiment of an error recovery and initialization device of a cell bus interface according to the present invention.

As shown in the drawing, the control board 100 or 200 provided with at least one determines whether there is an abnormality of the cell bus through the cell bus error monitoring unit 130 and 230 and interrupts it when an error occurs. Notify the processing unit 120, 220, the interrupt processing unit 120, 220 requests the interrupt to the main control unit 110, 210 according to the current error state, the main control unit 110, 210 Check the error state through the state value of the interrupt processing unit (120) 220 and perform an exception process to cause the cell bus control unit (140) 240 to initialize the cell bus reset controller (150) (250). do.

In addition, the clock boards 300 and 400 provided with at least one transmit an initialization signal to the control boards 100 and 200, and for this purpose, the clock boards 300 and 400 may be initially supplied with power. In this case, an initialization signal is transmitted to the cell bus error monitoring unit 130 or 230 of the control board 100 or 200 under the control of the main controller 310 or 410.

In addition, the clock boards 300 and 400 may transmit a current state signal to another clock board 400 or 300 when a cell bus error occurs while either clock board 300 or 400 is active. A bus clock board monitor 330 and 430 and a state signal of the cell bus clock board monitor 330 and 430 are inputted to the control board 100 through cell bus controllers 320 and 420. Main controller 310 and 410 for transmitting an initialization signal to the 200.

According to the present invention, the cell bus initialization operation according to the initial power-up of the CSHK, the cell bus initialization operation according to the transfer between the first clock board and the second clock board, and the cell bus initialization operation by the CSMB board itself are various. Through operation, cell bus initialization may be performed.

Here, the cell bus initialization operation according to the initial power-up of the CSHK will be described first. When the initial power is applied in the CSHK, the / CB_CB_RST signal is transmitted from the first clock board 300 or the second clock board 400 to the CSMB 100, It is transmitted to each control board, such as CSUB (200), CSDB (not shown).

The CSMB board 100 receives the / CB_CB_RST signal from the cell bus error monitoring unit 130 and transmits the / CB_RST signal to the interrupt processing unit 120, and the interrupt processing unit 120 transmits the / IRQ signal to the main control unit 110. do.

Therefore, the main controller 110 checks the state value of the interrupt processor 120 in an interrupt bus cycle and performs exception processing related to cell bus initialization, causing the cell bus controller 140 to reset the cell bus to the cell bus reset controller 150. Initialize the cell bus interface by sending the / CUBIT_RST signal for controller initialization.

In addition, the control boards such as the CSUB board 200 and the CSDB board (not shown) also perform a series of operations as described above, where the first clock board 300 and the second clock board 400 are used. The / CB_CB_RST signal is an open drain signal, and can be simultaneously output to each of the control boards 100 and 200 through a state signal bus.

Meanwhile, the cell bus initialization operation according to the switching between the first clock board 300 and the second clock board 400 will be described below.

If a cell bus error occurs when the first clock 300 is in an active state, the first clock board 300 transmits the FAILCB1 signal and the STATCB1 signal to the second clock board through the cell bus clock board monitoring unit 330. 400).

Therefore, the main controller 410 of the second clock board 400 receives the signal through the cell bus clock board monitor 430 and receives the / CB_CB_RST signal for initializing the cell bus through the cell bus controller 420. Generate.

As described above, the / CB_CB_RST signal generated from the first clock board 300 or the second clock board 400 is the control boards of the CSMB 100, the CSUB 200, the CSDB (not shown), and the like. The cell bus initialization operation is performed in the same manner as the cell bus initialization operation according to the initial power-up of the CSHK described above.

In addition, referring to the cell bus initialization operation by the CSMB board 100 itself, for example, if the cell bus clock is normal but the cell bus interface is in a dead state, that is, the CSMB board 100 for alarm and operation management signals and the like. When the CSUB 200 or CSDB board (not shown) fails after attempting a polling cell bus interface, the main control unit 110 of the SCMB board 100 transmits the / MB_CB_RST signal through the cell bus controller 140 to the CSUB board ( 200) and the CSDB board (not shown). It also sends a / CUBIT_RST signal to the cell bus reset controller 150.

Accordingly, the CSUB board 200 and the CSDB board (not shown) receive the / MB_CB_RST signal from the cell bus error monitoring unit 230 and pass it to the interrupt processing unit 220, and the interrupt processing unit 220 transmits the / IRQ signal to the main control unit. Transmit to 210.

The main controller 210 checks the state value of the interrupt processor 220 in an interrupt bus cycle and performs exception processing related to cell bus initialization so that the cell bus controller 240 initializes the cell bus reset controller to the cell bus reset controller 250. Initializes the cell bus interface by sending a / CUBIT_RST signal.

As described above, according to the error recovery and initialization device of the cell bus interface according to the present invention, the error recovery and initialization operations occurring during the performance of the cell bus interface between the internal control boards of the DSLAM system, which is an ADSL device, are performed according to the initial power-up of CSHK. It can be quickly and easily implemented through various operations such as cell bus initialization operation, cell bus initialization operation according to switching between the first clock board and the second clock board, and cell bus initialization operation by the CSMB board itself, so that it is easy to carry out a large-capacity system. There is an effect that can be applied.

Claims (4)

A cell bus error monitoring unit determines whether there is an abnormality in the cell bus and notifies the interrupt processing unit when an error occurs. The interrupt processing unit requests an interrupt to the main control unit according to the current error state, and the main control unit transmits the status value of the interrupt processing unit. At least one control board for checking an error state and performing an exception to cause the cell bus controller to initialize the cell bus reset controller, and at least one clock board for transmitting an initialization signal to the control board. Error recovery and initialization device for cell bus interfaces. The method of claim 1, wherein the clock board And a cell bus controller for transmitting an initialization signal to the cell bus error monitoring unit of the control board when the initial power is applied. The method of claim 1, wherein the clock board When a cell bus error occurs while one clock board is active, a cell bus clock board monitoring unit which transmits a current status signal to another clock board, and receives a status signal of the cell bus clock board monitoring unit through a cell bus controller. And a main control unit for transmitting an initialization signal to the control board. The method of claim 1, wherein the control board When the initialization operation is determined from the main controller, a status signal is transmitted to another control board through the cell bus controller, and an initialization signal is transmitted to the cell bus reset controller. And error initialization and initialization of a cell bus reset controller according to the status signal.