CN100370756C - Reset processing method and device for system - Google Patents
Reset processing method and device for system Download PDFInfo
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- CN100370756C CN100370756C CNB2005100720094A CN200510072009A CN100370756C CN 100370756 C CN100370756 C CN 100370756C CN B2005100720094 A CNB2005100720094 A CN B2005100720094A CN 200510072009 A CN200510072009 A CN 200510072009A CN 100370756 C CN100370756 C CN 100370756C
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Abstract
The present invention relates to a reset treatment method of a system and a device, and the method comprises the following steps: a. waiting time is preset when the system resets; B. an interruption request is transmitted to a CPU when a control unit detects a reset signal; C. the CPU receives the interruption request, collects and stores fault information of the corresponding equipment; D. the interruption request is cleared so as to carry out reset of the system when the control unit reaches the waiting time of the reset of the system. The device comprises a CPLD with non-shielding interruption pipe feet, the CPU and a storage unit, wherein the non-shielding interruption is transmitted or cleared according to the level of the reset signal so as to enable the system to reset; the CPU presets the waiting time when the system resets and collects fault information of the corresponding equipment when the non-shielding interruption is received; the storage unit is used for storing the fault information collected by the CPU. The present invention collects and stores the fault information in time when the system is abnormal, positions the fault equipment and is convenient for maintenance and treatment for research and development personnel in the future.
Description
Technical field
The present invention relates to the reset processing technology, particularly relate to a kind of reset processing method and device of system.
Background technology
Continuous expansion along with network size, problems such as network congestion goes offline are more and more, the probability that equipment breaks down is increasing, its fault data quantity also expands rapidly, because there is very strong incidence relation in each network element in the network on business, the fault of a network element may cause that other system reports a large amount of fault messages, and this situation has brought great inconvenience for attendant's alarm location and failure diagnosis.
In present field of telecommunications, artificial intelligence technology is used widely in network management system, describe as rule-based event correlation, fault location etc., the association of rule-based fault message and analysis mechanisms can effectively utilize the network model that includes that fault is carried out correlation analysis, and early monitoring, diagnosis influence the network abnormal factors of network service, the crux that must go wrong, reduce operating personnel's overload work, improve failure diagnosis efficient.
Particularly, when system's (such as Ethernet switch or router) when moving on the net, because network condition is very complicated, described system may be in operation and unusual or fault occur.Be that example illustrates below with the Ethernet switch, after Ethernet switch breaks down, will directly adopt the mode of device reset to solve problem.Described device reset schematic diagram as shown in Figure 1, this equipment comprises CPLD, reset key.When fault takes place, get used to producing reset signal for certain skinny device (such as switch) user with reset key, CPLD (CPLD in equipment, when ComplexProgrammable Logic Device) detecting described reset signal, directly equipment is resetted.Perhaps, if comprise main control device and the controlled plant that links to each other with main control device in a system.When main control device takes place when unusual, described controlled plant can not be worked normally, recovers professional in order to be eager, and solves by the mode that resets usually.And under the operating state when reseting period can not be unit exception preserves, be not easy to location, to tackle the problem at its root to faulty equipment.Therefore,, when equipment is resetted, do not collect fault message, when occurring same fault once more, can only solve yet by resetting from present technology.Though this technical scheme can temporarily solve the fault of equipment, can not avoid same fault to take place once more from basic solution obstacle that equipment brings.
As the above analysis, the shortcoming of prior art is: when system or equipment breaks down, the user gets used to directly system or equipment being resetted, do not collect fault message at reseting period, can not in time position faulty equipment, be not easy in the future attendant or research staff and fundamentally solve failure problems.
Summary of the invention
The technical problem that the present invention solves provides a kind of reset processing method and device of system.Occur when unusual in system, in time collect and storage failure information, so that come fault location equipment.Being convenient in the future attendant or research staff tackles the problem at its root.
For addressing the above problem, the invention provides a kind of reset processing method of system, comprise step:
A, the stand-by period when predetermined system resets;
B, when control unit detects reset signal, send interrupt requests to processor;
C, processor are received interrupt requests, collect and store the fault message of relevant device;
D, the described control unit stand-by period when described system reset is sent reset signal when arriving, and system is resetted.
In the stand-by period described in the steps A is the time of estimating to collect fault message according to the complexity of system.
In step B, described interrupt requests comprises non-shielding interruption, is according to reset signal the highest interruption of priority to be set.
At fault message described in the step C is when system breaks down, the operating state of other unit in related register, veneer and the system.
Also comprising step before the steps A: when system occurs when unusual, start reset key, the reset signal of output is sent to control unit.
In addition, the present invention also provides a kind of reset processing device of system, and described device comprises:
Control unit is used for the reset signal of detection system, and sends interrupt requests or remove interrupt requests according to the level of reset signal, and the stand-by period when a predetermined system resets is sent reset enable signal system reset after arriving;
Processor links to each other with control unit, the stand-by period during default described system reset, and when receiving interrupt requests, collect the fault message of relevant device;
Memory cell links to each other with processor, is used for the fault message that storage of processor is collected.
Described control unit comprises at least:
The I/O pin links to each other with processor, and described pin is exclusively used in the transmission interrupt requests;
Register links to each other with the I/O pin, the default stand-by period when being used for storage system and resetting;
The time of the collection fault message that the described stand-by period, to be systems soft ware estimated according to the complexity of system.
Described fault message is when system breaks down, the operating state of other unit in related register, veneer and the system.
Compared with prior art, the present invention has following beneficial effect: the stand-by period when the present invention resets by non-shielding interrupt pin and predetermined system are set in CPLD, when system occurs unusually, export reset signal when the user starts reset key and give CPLD; When CPLD detects reset signal (described reset signal is a high level), send non-shielding by non-shielding interrupt pin to processor and interrupt; Processor is received in the non-shielding and is had no progeny, and collects and store corresponding fault message, and described fault message is the operating state of other unit in register, veneer and the system thereof; After the stand-by period of when CPLD is reaching system reset, presetting, remove non-shielding and interrupt, system is resetted.This shows that during system reset, the fault message that system can be occurred when unusual is collected and preserved, and promptly faulty equipment is in time positioned.Tackle the problem at its root according to collected fault message for attendant in the future or research staff, avoid the appearance once more of same problem, thereby increase customer satisfaction degree.
Description of drawings
Fig. 1 is the single-board device schematic diagram that resets in the prior art;
Fig. 2 is the flow chart of the reset processing method of system of the present invention;
Fig. 3 is the structural representation of the reset processing device of system of the present invention.
Embodiment
Core of the present invention is (following will be with CPLD (CPLD at control unit, Complex Programmable Logic Device is that example illustrates) non-shielding interrupt pin of middle increase, and stand-by period of resetting of initialization system, and the described stand-by period is stored in the register of CPLD.When system occurs when unusual, start reset key, and with output reset signal send to CPLD, when CPLD detects reset signal, by non-shielding interrupt pin to processor (CPU, Center Processing Unit) sends non-shielding and interrupt (NMI, Non maskable Interrupt); Processor is received when non-shielding is interrupted, is collected and store corresponding fault message (being the operating state of relevant device); After the stand-by period that CPLD is preset when reaching system reset, remove non-shielding and interrupt, system is resetted.The present invention has used CPLD to come the collection of control system reseting period fault message.Because CPLD is a widely used logical device in hardware designs, described device can be realized simple decoding logic, simple functions control logic or the like by programming.So that the present invention occurs when unusual in system, the user solves problem usually with resetting, in the stand-by period of when system reset, presetting, processor is collected and is stored corresponding fault message, when promptly breaking down in system, collects and preserve the operating state of other unit in related register, veneer and the system, promptly faulty equipment is positioned, confession attendant or research staff safeguard and handle in the future, avoid same fault to take place once more, to tackle the problem at its root.
The present invention is described further below in conjunction with accompanying drawing.
See also Fig. 2, be the flow chart of the reset processing method of system of the present invention, described method comprises:
Step S11: the stand-by period when predetermined system resets;
Step S12: when control unit detects reset signal, send interrupt requests to processor;
Step S13: processor is received interrupt requests, collects and store the fault message of relevant device;
Step S14: the stand-by period of described control unit when described system reset sent reset signal when arriving, and system is resetted.
In above-mentioned steps, described control unit and to interrupt interrupting with CPLD and non-shielding respectively be that example illustrates below is not repeating.In described step S11, the stand-by period of processor when at first predetermined system resets, the described stand-by period be provided with software be by processor when non-shielding is interrupted to system in all devices collect and deposit the used time of its relevant information and be provided with.
Occur when unusual at veneer, the user presses reset key, and the reset signal that send reset key this moment sends to complex programmable logic device (CPLD).Described user presses reset key system is resetted, the output reset signal, and when complex programmable logic device (CPLD) detected reset signal, sending non-shielding by its non-shielding interrupt pin to processor interrupted, and it is the highest interruption of priority that CPU provides that described non-shielding is interrupted.Described non-shielding is interrupted being provided with according to reset signal, and high level represents NMI effective, and on behalf of operate as normal, low level do not interrupt.That is to say, when CPLD receives from reset signal that reset key is sent, non-shielding interrupt pin to CPU is sent high level, triggering NMI interrupts, do not carry out system reset this moment, just CPLD is when reaching the stand-by period of setting, just to system reset (step S12).The stand-by period of described system is the stand-by period that resets of the system that is provided with for CPLD in advance of processor just, promptly when CPLD detects reset signal, triggering non-shielding interrupts, in the stand-by period of when system reset, presetting, processor is in time collected fault message, and described fault message is stored in the memory cell.Described collection fault message is exactly that state to the key point of veneer and system reads.Just as the CPU of computer reads thing from internal memory.It is the same collecting the process of fault message and the process of storage, and collection is to read, and storage is to write.
And in step S13, receive in the non-shielding at processor and to have no progeny, in the stand-by period of system reset, collect fault message, and fault message write in the memory cell, and described memory cell is a non-volatile memory cells, in the process that system's power down or system restart, canned data can not lost.The operating state of miscellaneous equipment in each register, veneer and system when described fault message is system reset so that attendant or research staff analyze and handle described fault message in the future, and tackles the problem at its root.It is the highest interruption of priority that described NMI interrupts, and CPU has no progeny in receiving described NMI, can end the operation of other program.Then, when CPLD reaches system reset, during default stand-by period, remove non-shielding and interrupt, to system reset (step S14).It is invalid to be that Reset Board interrupts non-shielding to be changed to simultaneously, is about to pin and is changed to low level.The described stand-by period is notified CPLD by software by control bus.The described stand-by period is the used time of the collection of fault message to be decided during according to non-shielding Interrupt Process.That is to say that software is according to the complexity of system, estimate to collect the time of fault message, the register that CPLD is offered central processing unit writes then, and CPLD is according to the real-time adjustment stand-by period of the value of register.
Particularly when non-shielding was interrupted, processor was collected fault message and storage, so that software is for the needs of later analysis.Described fault message is the state that related register when unusual and veneer and other unit of system appear in system.The detailed process of described collection and handling failure information is:
Processor is collected fault message from ethernet device (such as switch or router); The fault message that receives is filtered, be about to receive the filtercondition that is provided with according to Fault Management System behind the fault message, the fault message that will meet filtercondition abandons, and remaining fault message is continued to report; The fault message normalization, because the form of the fault message that ethernet device reports is inequality, so the fault message unification of distinct device will be a kind of form, maintaining easily personnel or research staff carries out correlation analysis; Relative engines starts, and carries out correlation analysis for the fault message after the naturalization; Relative engines is the read failure association rules from rule-based knowledge base, this rule-based knowledge base has reflected the general fault interrelated logic of network, equipment and various hardware, and fault causes logical relation etc.: relative engines reads the topological structure at networking from topology information base, and this topology information base comprises the circuit, topological structure of the network information, positional information, locating information and the logical relation thereof of various device and various hardware devices etc.; According to the information in rule-based knowledge base and the topology information base fault data is comprehensively analyzed, reviewed the root information that fault causes, fault is positioned; Fault message behind the process correlation analysis is in interface display.
System supports static rule and dynamic programming definition mechanism fully, and the dynamic programming definition mechanism is added the information in rule-based knowledge base or the topology information base in real time, reduced or revise, real-time update when system moves.Attendant or research staff can fundamentally solve fault according to fault message, avoid the appearance once more of described fault, thereby have improved client's satisfaction.
In addition, the present invention also provides a kind of structural representation of reset processing device of system of the present invention, sees Fig. 3 for details.Described reset processing device comprises: control unit 11, processor 12 (for central processing unit), memory cell 13 and reset key 14.
Below described control unit 11 be that example describes with CPLD 11.
Described CPLD 11 is used for the reset signal of detection system, and sends interrupt requests or remove interrupt requests according to the level of reset signal, and the stand-by period when a predetermined system resets is sent reset enable signal system reset after arriving; Described interrupt requests is non-shielding interrupt requests.Do not produce interruption this moment, described non-shielding is interrupted being provided with according to reset signal, and high level represents NMI effective, and on behalf of operate as normal, low level do not interrupt; When detecting the control command that reaches the default stand-by period, to remove non-shielding and interrupt, CPLD 11 is sent reset enable signal system reset.When the described stand-by period is a processor according to non-shielding Interrupt Process all fault messages being collected all time is provided with.
Described processor 12 links to each other with CPLD 11, the stand-by period during default described system reset, and when receiving interrupt requests, collect the fault message of relevant device.When receiving that non-shielding is interrupted, collect fault message, described non-shielding interrupts being the highest interruption of priority, processor receives in the non-shielding and has no progeny, can end the operation of other program, carry out the processing of fault message, the processing of described fault message mainly is a state of collecting fault each register when taking place, and the operating state of other unit in veneer and the system.Described processor only is to collect fault message, uses for later analysis.In addition, when reaching Preset Time, send the control command that reaches the default stand-by period to programmable logic device.
Described memory cell 13 links to each other with processor 11, is used for the fault message that storage of processor is collected, described storage element 13 is a nonvolatile memory cell, such as flash memory, electrically alterable storage, in the process that system's power down or system restart, canned data can not lost.
Wherein, described CPLD comprises at least: I/O pin and register.Described I/O pin links to each other with processor, is exclusively used in non-shielding and interrupts, and when CPLD detects reset signal, interrupts the I/O pin by non-shielding and sends non-shielding interruption to processor; Described register links to each other with the I/O pin, the default stand-by period when being used for storage system and resetting.
Described reset key 14 links to each other with the I/O pin of CPLD 11, and when system occurs when unusual, the user presses reset key, and reset key was sent reset signal and given CPLD 11 this moment.Before the user presses reset key, at first anticipate the stand-by period of device predetermined system when resetting, and the described stand-by period is placed in the CPLD, the software that is provided with of described stand-by period is to be provided with the memory time to register by processor.
In addition, described system reset can adopt CPU to automatically reset or the mode of manual reset system (as above-mentioned use reset key).Described CPU automatically resets and just is meant that CPU receives by the I/O mouth on the pin of CPLD, and when the processor output low level, CPLD output reset signal resets to system.Lifting an example below describes, CPU receives on the MR pin of special-purpose CPLD (such as ADM706) by the I/O mouth, when low level of CPU output, the RESET pin of ADM706 chip will be exported the reset signal of an above pulsewidth of 200ms, system equipment is resetted, when CPLD received reset signal, the I/O mouth by special use sent non-shielding to processor and interrupts.Described manual reset starts reset key exactly.Of the present invention automatically reset and manual reset all be equivalent to PC from menu select computer restart, by the reset key of PC and start main control device.
Complex programmable logic device (CPLD) of the present invention, it is a kind of than the logic module of PLD for complexity.And described CPLD is the higher logic module of a kind of conformability.Owing to have high conformability, so it has performance boost, reliability increases, degradation advantage under minimizing of circuit board PCB area and the cost.The CPLD assembly is combined by many logical blocks (Logic Blocks).And each logical block homogeneous phase is similar to a simple PLD assembly (as 22V10).Correlation between logical block is then by programmable online framework, forms overall logic is synthetic.But the present invention promptly can adopt CPLD to realize; Also can be combined into the device with logic function by simple logic chip realizes.Therefore, no matter the present invention is to adopt CPLD, still adopts simple logic chip to be combined into the device with logic function, can both realize function of the present invention, its implementation procedure is identical with described CPLD, here repeats no more.
For clearer the present invention is described below, please refer to application example as described below.
Metropolitan area network in certain typical operator; certain equipment is through the delay problem of machine of regular meeting, and just can deal with problems in the back but each user oneself resets, when the existing reset schemes of use; relevant fault message can't be collected, and attendant or research staff can't be located at all.After using reset schemes of the present invention, processor has in time been collected relevant fault message when going wrong, and the fault message of collecting is stored in the memory cell, for attendant or research staff's later analysis and processing, that is to say, after research staff's process anatomizes collected fault message, discovery is because certain special configurations causes the leakage of Installed System Memory, therefore, and behind the software of the described problem of upgrading, just address this problem, equipment will recover stable operation.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. the reset processing method of a system is characterized in that, comprising:
A, the stand-by period when predetermined system resets;
B, when control unit detects reset signal, send interrupt requests to processor;
C, processor are received interrupt requests, collect and store the fault message of relevant device;
D, the described control unit stand-by period when described system reset is sent reset signal when arriving, and system is resetted.
2. according to the reset processing method of the described system of claim 1, it is characterized in that, is the time of estimating to collect fault message according to the complexity of system in the stand-by period described in the steps A.
3. according to the reset processing method of the described system of claim 1, it is characterized in that in step B, described interrupt requests comprises non-shielding interruption, described non-shielding is interrupted being provided with according to reset signal.
4. according to the reset processing method of the described system of claim 1, it is characterized in that, is when system breaks down at fault message described in the step C, the operating state of other unit in related register, veneer and the system.
5. according to the reset processing method of the described system of claim 1, it is characterized in that, also comprising step before the steps A: when system occurs when unusual, start reset key, the reset signal of output is sent to control unit.
6. the reset processing device of a system is characterized in that, comprising:
Control unit is used for the reset signal of detection system, and sends interrupt requests or remove interrupt requests according to the level of reset signal, and the stand-by period when a predetermined system resets is sent reset enable signal system reset after arriving;
Processor links to each other with control unit, the stand-by period during default described system reset, and when receiving interrupt requests, collect the fault message of relevant device;
Memory cell links to each other with processor, is used for the fault message that storage of processor is collected.
7. according to the reset processing device of the described system of claim 6, it is characterized in that described control unit also comprises:
The I/O pin links to each other with processor, and described pin is exclusively used in the transmission interrupt requests;
Register links to each other with the I/O pin, the default stand-by period when being used for storage system and resetting;
8. according to the reset processing device of claim 6 or 7 described systems, it is characterized in that the time of the collection fault message that the described stand-by period, to be systems soft ware estimated according to the complexity of system.
9. the reset processing device of described system according to Claim 8 is characterized in that, described fault message is for when system breaks down, the operating state of other unit in related register, veneer and the system.
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| CNB2005100720094A CN100370756C (en) | 2005-05-24 | 2005-05-24 | Reset processing method and device for system |
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| CNB2005100720094A CN100370756C (en) | 2005-05-24 | 2005-05-24 | Reset processing method and device for system |
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| CN100370756C true CN100370756C (en) | 2008-02-20 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100397353C (en) * | 2006-07-26 | 2008-06-25 | 华为技术有限公司 | System and method for raising single-board exception handling ability |
| CN101206516B (en) * | 2006-12-19 | 2012-05-30 | 鸿富锦精密工业（深圳）有限公司 | Computer system resetting device |
| TWI403885B (en) * | 2006-12-22 | 2013-08-01 | Hon Hai Prec Ind Co Ltd | Computer system reset device |
| CN101895440B (en) * | 2010-07-22 | 2012-07-04 | 北京天融信科技有限公司 | Security gateway and failure detection method thereof |
| CN103118240A (en) * | 2011-11-17 | 2013-05-22 | 上海贝尔股份有限公司 | Method and device for monitoring reset signal of each module in a system |
| CN103248507B (en) * | 2012-02-08 | 2018-10-26 | 南京中兴新软件有限责任公司 | Single-board power-down device and method |
| CN103019870A (en) * | 2012-12-14 | 2013-04-03 | 大唐移动通信设备有限公司 | Method and communication equipment for processing reset signal |
| CN104978001A (en) * | 2014-04-09 | 2015-10-14 | 中兴通讯股份有限公司 | Reset management method and device |
| CN104317728B (en) * | 2014-10-13 | 2018-03-23 | 大唐移动通信设备有限公司 | A kind of method and apparatus of safety reset storage device |
| CN105824381A (en) * | 2015-01-07 | 2016-08-03 | 中兴通讯股份有限公司 | Single board power down restart adjustment method, apparatus and system |
| CN104899125B (en) * | 2015-06-04 | 2019-01-29 | 新华三技术有限公司 | A kind of the operation information acquisition methods and device of single board system |
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