CN104978001A - Reset management method and device - Google Patents
Reset management method and device Download PDFInfo
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- CN104978001A CN104978001A CN201410140131.XA CN201410140131A CN104978001A CN 104978001 A CN104978001 A CN 104978001A CN 201410140131 A CN201410140131 A CN 201410140131A CN 104978001 A CN104978001 A CN 104978001A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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Abstract
The invention provides a reset management method and device. A reset control module judges whether a reset-ready notice is received or not; if the reset-ready notice is received, a reset triggering signal used for triggering a reset operation is sent to a processor module; the processor module receives a reset notice to make a reset preparation; after the reset preparation is made, the reset-ready notice is sent to the reset control module, wherein the reset-ready notice is used for prompting the reset control module to send the reset trigger signal used for triggering the reset operation to the processor module; and after the reset trigger signal is received, the reset operation is carried out. The reset management method and device can carry out real-time triggering without waiting for set fixed time and carries out real-time triggering after a preparation-ready notice sent from the processor module is received, unnecessary time delay wait can be reduced, reset duration is controllable and optimal, and the system can restore business as quickly as possible.
Description
Technical field
The present invention relates to the communications field, particularly relate to a kind of management method and apparatus that resets.
Background technology
Cause reset to be restarted if there is fault in veneer operational process, need the reason that can have means recording reset, facilitate consequent malfunction to locate, more need the time that can shorten reseting stage, allow veneer resume operation as early as possible.Prior art is for the process comparative maturity resetted, such as one section of Chinese patent disclosed in 22 days July in 2009, patent publication No. is CN100517177C, the time-delay reset time arranged in technical scheme disclosed in this sharp document is regular time length, each reset just can trigger after all will arriving regular time, but in fact do not need to wait for the so long time under many circumstances, so just delay the time of business recovery.
Summary of the invention
The main technical problem to be solved in the present invention is, solves in prior art the problem that there is timing reset and cause resetting not in time.
For solving the problem, the invention provides a kind of reset management method, comprising:
Reset control module judges whether to receive the ready notice that resets, and in this way, sends the reset trigger signal for triggering reset operation to processor module.
In an embodiment of the present invention, described reset control module judges whether that receiving the ready notice of reset comprises:
Described reset control module starts timing when described processor die BOB(beginning of block) resets and prepares, and judges in Preset Time, whether receive the ready notice that resets.
In an embodiment of the present invention, when described reset control module judges not receive the ready notice of described reset in described Preset Time, reset trigger signal is sent to described processor module.
For solving the problem, the present invention also provides a kind of reset management method, comprising:
Processor module receives reset notice and carries out reset preparation;
Described processor module completes to reset and prepares to send to reset control module the ready notice that resets, and the ready notice of described reset sends the reset trigger signal for triggering reset operation for pointing out described reset control module to described processor module;
Described processor module receives described reset trigger signal and carries out reset operation.
In an embodiment of the present invention, described processor module carries out reset preparation and comprises: preserve current operational factor.
In an embodiment of the present invention, described processor module carry out reset prepare also comprise: preserve notify corresponding reset circuit with described reset.
For solving the problem, the present invention also provides a kind of reset management devices, comprises reset control module, described reset control module comprise judge submodule and send submodule:
Described judgement submodule is used for judging whether to receive the ready notice that resets;
Described transmission submodule is used for judging to receive the ready notice of described reset at described judgement submodule, sends the reset trigger signal triggering reset operation to processor module.
In an embodiment of the present invention, described reset control module also comprises timing submodule:
Described timing submodule is used for starting timing when described processor die BOB(beginning of block) resets and prepares; Described judgement submodule judges whether to receive the ready notice that resets and is included in Preset Time and judges whether to receive the ready notice that resets.
In an embodiment of the present invention, described transmission submodule also for judging not receive the ready notice of described reset in Preset Time during at described judgement submodule, the reset trigger signal triggering reset operation is sent to processor module.
For solving the problem, the present invention also provides a kind of reset management devices, comprises processor module, described processor module comprise receive submodule, prepare submodule, the ready notice that resets transmission submodule and reset operation submodule:
Described reception submodule is for receiving reset notice and reset trigger signal;
Described preparation submodule is used for receiving described reset at described reception submodule and notifies that laggard horizontal reset prepares;
The ready notice of described reset sends submodule and is used for sending to reset control module the ready notice that resets after described preparation submodule completes the preparation that resets; The ready notice of described reset sends the reset trigger signal for triggering reset operation for pointing out described reset control module to described processor module;
Described reset operation submodule is used for receiving the laggard horizontal reset operation of reset trigger signal at described reception submodule.
In an embodiment of the present invention, described preparation submodule comprises parameter preservation submodule, for preserving current operational factor.
In an embodiment of the present invention, described preparation submodule also comprises reason and preserves submodule, notifies corresponding reset circuit for preserving with described reset.
The invention has the beneficial effects as follows:
The method and apparatus of the management that resets provided by the invention, reset control module judges whether to receive the ready notice that resets, and in this way, sends the reset trigger signal for triggering reset operation to processor module.Receive reset notice with processor module and carry out reset preparation; Processor module completes to reset and prepares to send to reset control module the ready notice that resets, and the ready notice of this reset sends the reset trigger signal for triggering reset operation for pointing out reset control module to processor module; Processor module receives this reset trigger signal and carries out reset operation.Compared with prior art, the present invention can not need the set time by the time arranged to trigger constantly, but trigger in real time after the Notice of Readiness of processor module transmission can being received one, unnecessary time delay can be reduced wait for, realize reset duration controlled with optimum, make system can recover business as early as possible.
Accompanying drawing explanation
The reset management method flow schematic diagram that Fig. 1 provides for the embodiment of the present invention one;
The reset management method flow schematic diagram that Fig. 2 provides for the embodiment of the present invention two;
The resetting means structural representation one that Fig. 3 provides for the embodiment of the present invention three;
The reset management apparatus structure schematic diagram two that Fig. 4 provides for the embodiment of the present invention three;
The reset management apparatus structure schematic diagram one that Fig. 5 provides for the embodiment of the present invention four;
The reset management apparatus structure schematic diagram two that Fig. 6 provides for the embodiment of the present invention four;
The reset management apparatus structure schematic diagram that Fig. 7 provides for the embodiment of the present invention five.
Embodiment
In order to make technical matters solved by the invention, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.
Embodiment one:
Reference Fig. 1, this figure are the reset management method flow schematic diagram that the embodiment of the present invention one provides, and the method comprises the steps:
Step 101: reset control module judges whether to receive the ready notice that resets;
In this step, the mode that reset control module receives reset ready signal comprises any mode that can be used to receive the ready notice of reset.The ready notice that resets be all can make reset control module learn processor module complete reset prepare announcement information.Be interpreted as reset control module receive reset ready notice just think processor module complete reset prepare.Confiscate the ready notice that resets, then think that processor module does not complete to reset and prepare.Such as when using the ready flag that resets in advance as reset ready notice, reset control module judges whether to receive reseting mark in advance, as received reseting mark in advance, then think that processor module has completed to reset to prepare, if confiscate reseting mark in advance, then think that processor module does not complete to reset and prepare.
Step 102: in this way, sends the reset trigger signal for triggering reset operation to processor module.
In this step, be interpreted as reset control module in this way and receive the ready notice that resets.After reset control module receives the ready notice that resets, specifically how to receive and be interpreted as existing so the mode receiving reset ready signal all should be included.After reset control module to the ready notice of reset, send to processor module immediately and be used for the reset trigger signal that triggers processor module carries out reset operation.Here reset trigger signal is interpreted as allly to carry out the announcement information used of reset operation by triggers processor module.Such as when taking reset pulse as reset trigger signal, reset control module sends reset pulse to processor module after receiving the ready notice that resets immediately, and processor module just carries out reset operation after receiving this reset pulse.
In some cases, processor module sends the ready notice that resets cannot to reset control module, or its ready notice of reset control module that is not reset sent receives; Such as, when processor module runs and flies.In order to normally carrying out of resetting under ensureing these situations, step 103: reset control module can judge whether to receive the ready notice that resets in Preset Time.Also namely judge whether to receive reset ready signal, if confiscate just judge whether arrive Preset Time, if be less than Preset Time return continue to judge whether reset ready signal until arrive Preset Time.Concrete operations are that reset control module starts timing when processor die BOB(beginning of block) resets and prepares, and judge whether to receive the ready notice that resets in Preset Time.Here timing can adopt timer to carry out timing, and certain existing all modes that can be used for timing all should be included in the implementation of the application.Here Preset Time is interpreted as generally completing than processor module the length of the time needed for preparing that resets, namely can complete to reset in this Preset Time inner treater module and prepare, and to have over head time i.e. Preset Time be here cannot accept to prevent cannot sending reset ready notice or reset control module to reset control module at processor module the ready notice that resets, but processor module has completed to reset and has prepared and be provided with, and can ensure that processor carries out normal reset operation like this.
Step 104: complete reset when preparing the ready notice of the reset that sends if reset control module does not receive processor module in Preset Time, reset control module also can think that processor module sends reset trigger signal, make processor module carry out reset operation, ensure normally carrying out of reset.Judge whether to receive the ready notice that resets in Preset Time, judge always, until arrive the schedule time, if also confiscate reset ready signal after when arriving predetermined, reset control module just sends to processor module and triggers the notice that resets.Be interpreted as, prepare because processor module has completed to reset, but due to some fault or unexpected cause reset control module to learn processor module has completed to reset prepares, so reset control module can send to processor module the reset trigger signal that triggers processor module carry out reset operation after arriving Preset Time.
Embodiment two:
Reference Fig. 2, this figure are the reset management method flow schematic diagram that the embodiment of the present invention one provides, and the method comprises the steps:
Step 201: processor module receives reset notice and carries out reset preparation;
In this step, processor module receive reset notice can comprise any mode to receive reset notice.Reset notice for all can make processor module learn need carry out reset prepare announcement information.Be interpreted as, processor module receives the notice that resets and then thinks that needs carry out reset and prepare.Time such as using interrupt request as reset notice, processor module transmitting-receiving interrupt request is just carried out reset and is prepared.
Step 202: processor module completes to reset and prepares to send to reset control module the ready notice that resets, and the ready notice that resets sends the reset trigger signal for triggering reset operation for pointing out described reset control module to processor module;
In this step, processor module sends to reset control module the ready notice that resets, and is interpreted as by existing all modes of carrying out sending.The ready notice that resets, with the same in above-described embodiment one, is no longer described in detail at this.Reset trigger signal also with in above-described embodiment one record, no longer describe in detail at this.
Step 203: processor module receives reset trigger signal and carries out reset operation.
In this step, how processor module receives reset trigger signal is interpreted as existing all receive modes and all can realizes, and reset trigger signal, as recorded in above-described embodiment, is no longer described in detail at this.
In above-mentioned steps 201, processor module carries out resetting preparing to comprise and preserves current operational factor, preferably preserves the operational factor of current key further.These parameters can be saved in storer further and be convenient to follow-up use.Here operational factor comprises processor utilization, program process running status, key chip critical registers, the operational factors such as temperature of single plate voltage.
For the ease of searching reset circuit below and carrying out the location of reset circuit, the processor module in the present embodiment carries out can also preserving reset circuit corresponding to this reset notice in the process of reset preparation, the reset circuit that also namely current reset request is corresponding.Wherein, processor module obtains the mode of this reset circuit can be directly obtain from reset circuit recorded above.In the present embodiment, different values can be adopted to distinguish different reset source, also namely represent different reset circuits.Such as 1 represents electrification reset, and 2 represent watchdog reset, and 3 represent partner's sheet reset etc.Also by arranging multiple register record reset circuit several times recently.Such as arrange 8 registers, register adopts the mode of the first in first out of similar queue to upgrade when there being reset request, then described device can record the reset circuit of nearest 8 times.All right setup times register, is used for recording each time occurred that resets.
Embodiment three:
Be depicted as with reference to Fig. 3, this figure the reset management apparatus structure schematic diagram that the embodiment of the present invention three provides, this reset management devices comprises reset control module, and this reset control module comprises and judges submodule and transmission submodule.Judge that submodule is used for judging whether to receive the ready notice that resets; Send submodule to be used for, judging that submodule judges to receive the ready notice that resets, sending the reset trigger signal triggering reset operation to processor module.
In this example, judge that submodule judges whether to receive mode that reset ready signal is interpreted as judging that submodule receives reset ready signal and comprises and anyly can be used to receive the mode of ready notice of resetting.The ready notice that resets be all can make judgement submodule learn processor module complete reset prepare announcement information.Be interpreted as judging that submodule receives the ready notice that resets and just thinks that processor module completes the preparation that resets.Confiscate the ready notice that resets, then think that processor module does not complete to reset and prepare.Such as when using the ready flag that resets in advance as reset ready notice, judge that submodule judges whether to receive reseting mark in advance, as received reseting mark in advance, then think that processor module has completed to reset to prepare, if confiscate reseting mark in advance, then think that processor module does not complete to reset and prepare.
In this enforcement, send submodule to be used for judging that submodule judges to receive the ready notice that resets, send to processor module the reset trigger signal triggering reset operation to be interpreted as, after judging that submodule receives the ready notice that resets, specifically how receiving and being interpreted as existing so the mode receiving reset ready signal all should be included.After judging submodule to the ready notice of reset, allow immediately and send submodule carries out reset operation for reset trigger signal from triggers processor module to processor module transmission.Here reset trigger signal is interpreted as allly to carry out the announcement information used of reset operation by triggers processor module.Such as when taking reset pulse as reset trigger signal, judge to allow transmission submodule send reset pulse to processor module immediately after submodule receives the ready notice that resets, processor module just carries out reset operation after receiving this reset pulse.It should be noted that reset control module is here construed as all modules that can control the reset operation of processor module.Such as this reset control module can be time-delay reset control module, certainly time-delay reset control module is not limited only to, this delays time to control module also can comprise the pulse generating module that can produce reseting pulse signal and reception can be had to reset in advance the signal detection module of mark and other modules be associated.
Further, the reset management devices of the application also can comprise reset notification module, and this reset notification module is for generation of reset notice, and this reset notice is used for notification processor module and carries out reset preparation.Such as this reset notification module can be reset interrupt generation module, is certainly not limited only to reset interrupt generation module, also comprises other and can realize all modules that notification processor module carries out reset preparation.
Further, the reset management devices of the application also can comprise the reset circuit module for generation of reset signal, this reset circuit module for after receiving reset request marking signal, generating reset signal, and this reset signal is sent to reset control module and reset notification module.Such as this reset circuit module can be Special reset chip, is certainly not limited only to Special reset chip, also comprises other and can realize generating reset signal and all modules sending to reset control module and reset notification module.
Further, the reset management devices of the application also can comprise reset source processing module, this reset source processing module for producing reseting mark signal after receiving reset request and this reset request marking signal being sent to reset circuit module, notice reset circuit CMOS macro cell reset signal.And this reseting mark signal is sent to reset circuit logging modle.
Further, the reset management devices of the application also comprises reset circuit logging modle, this reset circuit logging modle for after the reseting mark signal that receives reset source processing module and send according to the concrete reason of reset source record current reset.The reset management devices that it should be noted that in the application is not limited only to above-mentioned cited module, also can comprise other modules be associated, and can be associated between modules and also can independently exist.
As shown in Figure 4, reset control module also comprises timing submodule: timing submodule is used for starting timing when described processor die BOB(beginning of block) resets and prepares; Further, judge that submodule is used for judging whether to receive the ready notice that resets in Preset Time.Specifically be interpreted as that timing submodule starts timing when processor die BOB(beginning of block) resets and prepares, judge that submodule is judging whether to receive in Preset Time the ready notice of reset.Here timing can adopt timer to carry out timing, and certain existing all modes that can be used for timing all should be included in the implementation of the application.Here Preset Time is interpreted as generally completing than processor module the length of the time needed for preparing that resets, namely can complete to reset in this Preset Time inner treater module and prepare, and to have over head time i.e. Preset Time be here cannot accept to prevent cannot sending reset ready notice or reset control module to reset control module at processor module the ready notice that resets, but processor module has completed to reset and has prepared and be provided with, and can ensure that processor carries out normal reset operation like this.
If judge that submodule does not receive processor module and completes and reset when preparing the ready notice of the reset that sends in Preset Time, send submodule and also can think that processor module sends reset trigger signal, make processor module carry out reset operation, ensure normally carrying out of reset.Be interpreted as, prepare because processor module has completed to reset, but because some fault or unexpected causing judge that submodule cannot be learnt that processor module has completed to reset and prepare, so judge that submodule can send to processor module the reset trigger signal that triggers processor module carries out reset operation after arriving Preset Time.
Embodiment four:
With reference to Fig. 5, this figure is depicted as the reset management apparatus structure schematic diagram that the embodiment of the present invention four provides, this reset management devices comprises processor module, this processor module comprise receive submodule, prepare submodule, the ready notice that resets sends submodule and reset operation submodule: receive submodule and notify for receiving to reset; Prepare submodule to be used for carrying out reset preparation; The ready notice that resets sends submodule and sends to reset control module the ready notice that resets for preparing after submodule completes the preparation that resets; The ready notice that resets sends the reset trigger signal for triggering reset operation for pointing out reset control module to processor module; Receive submodule also for receiving reset trigger signal; Reset operation submodule receives the laggard horizontal reset operation of reset trigger signal for receiving submodule.
As shown in Figure 6, the preparation submodule of this reset management devices also comprises parameter and preserves submodule, and this parameter preserves submodule for preserving current operational factor, can be used for the operational factor of preferably preserving current key further.Also be convenient to follow-up use for these parameters being saved in storer further.Here operational factor comprises processor utilization, program process running status, key chip critical registers, the operational factors such as temperature of single plate voltage.
For the ease of searching reset circuit below and carrying out the location of reset circuit, the preparation submodule in the present embodiment comprises reason and preserves submodule, for preserving reset circuit corresponding to this reset notice, the reset circuit that also namely current reset request is corresponding.Wherein, processor module obtains the mode of this reset circuit can be directly obtain from reset circuit recorded above.In the present embodiment, different values can be adopted to distinguish different reset source, also namely represent different reset circuits.Such as 1 represents electrification reset, and 2 represent watchdog reset, and 3 represent partner's sheet reset etc.Also by arranging multiple register record reset circuit several times recently.Such as arrange 8 registers, register adopts the mode of the first in first out of similar queue to upgrade when there being reset request, then described device can record the reset circuit of nearest 8 times.All right setup times register, is used for recording each time occurred that resets.
Embodiment five:
In order to make the present invention program clearer and more definite, the present embodiment composition graphs 7 pairs of this programme conduct further description, as shown in Figure 7, the resetting means that the present embodiment provides mainly comprises with lower module: reset source processing module, reset circuit book of final entry module, reset interrupt generation module, time-delay reset control module, Special reset circuit module, programmable logic device (PLD) module, processor module.Reset source processor module, reset circuit logging modle, reset interrupt generation module, time-delay reset control module are realized by programmable logic device (PLD) (CPLD), and Special reset circuit module is realized, as MAX706, MAX813 etc. by special reset chip.
Reset control method of the present invention comprises the following steps:
Step one: reset source processing module carries out the work for the treatment of such as filtering, Effective judgement to reset signal, after the reset request that filtering is illegal, produces reset request mark RST_REQ_FLAG;
Step 2: reset request is marked RST_REQ_FLAG and gives module causality classification logging modle by reset source processing module, reset circuit book of final entry module is according to the concrete reason of reset source record current reset;
Step 3: reset request is marked RST_REQ_FLAG and gives Special reset circuit module by reset source processor module;
Step 4: Special reset circuit module produces reset output signal RST_OUT to reset interrupt generation module and time-delay reset control module;
Step 5: reset interrupt generation module produces reset interrupt signal RST_INT notification processor module veneer and will reset, and asks the good reset circuit of processor module record namely to keep the key parameter of reset circuit and current operation with the on-the-spot key parameter run;
Step 6: processor module sends out reset ready signal RST_READY_FLAG to time-delay reset module after keeping operational factor;
Step 7: time-delay reset module starts timer after receiving reset signal RST_OUT, compares with the delay time preset, if timing time arrives, directly sends reseting signal reset processor and peripheral hardware.If gate time does not arrive, but have received the reset ready signal RST_READY_FLAG that processor module sends, send reseting signal reset processor and other peripheral hardware to be immediately interpreted as processor module and to comprise processor and other peripheral hardwares, thus realize the object that shortens reset time.
Further detailed description is:
For the veneer of complexity, reset source can comprise watchdog reset, button reset, partner's sheet reset, electrification reset, veneer positive return etc. usually.The unification of these reset source is delivered to programmable logic device (PLD) and is processed, after programmable logic device (PLD) receives the reseting request signal that these reset source send here, first send into reset processing module and carry out pre-service, comprise and filtering is carried out to signal, with filtering burr, prevent from resetting by mistake; Determine the need of shielding this kind of reset request according to arranging of reset mask register.After treatment, if there is legal reset request, reset processing module sends out reset request marking signal RST_REQ_FLAG to reset circuit logging modle and Special reset circuit module.
Reset circuit logging modle after receiving reset request marking signal, by the reset source that reset circuit register record is current.Different reset source is distinguished by different values, also namely different reset circuits in reset circuit register; Such as 1 represents electrification reset, and 2 represent watchdog reset, and 3 represent partner's sheet reset etc.Reset circuit register can arrange multiple, is used for recording reset circuit several times recently.Such as arrange 8 reset circuit registers, register adopts the mode of the first in first out of similar queue to upgrade when there being reset request marking signal RST_REQ_FLAG, then described device can record the reset circuit of nearest 8 times.All right setup times register in reset circuit logging modle 20, is used for recording each time occurred that resets.
Special reset circuit produces to reset and exports reset pulse RST_PULSE and give reset interrupt generation module and time-delay reset control module receiving reset request marking signal RST_REQ_FLAG.
Reset interrupt module is after receiving reset pulse RST_PLUSE, produce the interrupt request singal RST_INT requiring with processor module to match, notification processor module veneer will reset, please reset circuit and the on-the-spot key parameter run be saved in memory device, for subsequent analysis fault processor module.
Processor module, after receiving reset interrupt request signal RST_INT, enters reset interrupt program, reads the reset circuit register in programmable logic device (PLD), is saved in storer.System core operational factor is also saved in storer, for subsequent analysis by processor module.After processing these tasks, processor module sends reset ready signal RST_READY_FLAG to time-delay reset control module.
Timer, delay time register, in advance reseting mark register are set in time-delay reset control module.The value of delay time register is used for setting the timing time of timer.The value of delay time register arranges a relatively long set time, this time value be greater than processor module under normal circumstances carry out reset circuit and on-the-spot operational factor preserve needed for time.The reset ready signal RST_READY_FLAG that reseting mark register is sent here by processor module in advance carries out set, represent that processor module has been ready to accept reset, time-delay reset control module can send reset signal in advance, need not wait until that the value of delay time register remembered by timer, so just just achieve the function shortening reset time.In some cases, such as processor runs fly completely, and when cannot send reset ready signal, time-delay reset control module forces to send reset signal after the full delay time of timer, ensures that processor module can reset.
The all or part of step that one of ordinary skill in the art will appreciate that in said method is carried out instruction related hardware by program and is completed, and said procedure can be stored in computer-readable recording medium, as ROM (read-only memory), disk or CD etc.Alternatively, all or part of step of above-described embodiment also can use one or more integrated circuit to realize.Correspondingly, each module/unit in above-described embodiment can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
Above embodiment only in order to technical scheme of the present invention and unrestricted to be described, only with reference to preferred embodiment to invention has been detailed description.Those of ordinary skill in the art should be appreciated that and can modify to technical scheme of the present invention or equivalent replacement, and does not depart from the spirit and scope of technical solution of the present invention, all should be encompassed in the middle of right of the present invention.
Claims (12)
1. a reset management method, is characterized in that, comprising:
Reset control module judges whether to receive the ready notice that resets, and in this way, sends the reset trigger signal for triggering reset operation to processor module.
2. reset management method as claimed in claim 1, it is characterized in that, described reset control module judges whether that receiving the ready notice of reset comprises:
Described reset control module starts timing when described processor die BOB(beginning of block) resets and prepares, and judges in Preset Time, whether receive the ready notice that resets.
3. reset management method as claimed in claim 2, it is characterized in that, when described reset control module judges not receive the ready notice of described reset in described Preset Time, sends reset trigger signal to described processor module.
4. a reset management method, is characterized in that, comprising:
Processor module receives reset notice and carries out reset preparation;
Described processor module completes to reset and prepares to send to reset control module the ready notice that resets, and the ready notice of described reset sends the reset trigger signal for triggering reset operation for pointing out described reset control module to described processor module;
Described processor module receives described reset trigger signal and carries out reset operation.
5. reset management method as claimed in claim 5, it is characterized in that, described processor module carries out reset preparation and comprises: preserve current operational factor.
6. reset management method as claimed in claim 5, it is characterized in that, described processor module carries out resetting and prepares also to comprise: preserve and notify corresponding reset circuit with described reset.
7. a reset management devices, is characterized in that, comprises reset control module, described reset control module comprise judge submodule and send submodule:
Described judgement submodule is used for judging whether to receive the ready notice that resets;
Described transmission submodule is used for judging to receive the ready notice of described reset at described judgement submodule, sends the reset trigger signal triggering reset operation to processor module.
8. resetting means as claimed in claim 7, it is characterized in that, described reset control module also comprises timing submodule:
Described timing submodule is used for starting timing when described processor die BOB(beginning of block) resets and prepares; Described judgement submodule judges whether to receive the ready notice that resets and is included in Preset Time and judges whether to receive the ready notice that resets.
9. reset management devices as claimed in claim 8, it is characterized in that, described transmission submodule also for judging not receive the ready notice of described reset in Preset Time during at described judgement submodule, send the reset trigger signal triggering reset operation to processor module.
10. a reset management devices, is characterized in that, comprises processor module, described processor module comprise receive submodule, prepare submodule, the ready notice that resets transmission submodule and reset operation submodule:
Described reception submodule is for receiving reset notice and reset trigger signal;
Described preparation submodule is used for receiving described reset at described reception submodule and notifies that laggard horizontal reset prepares;
The ready notice of described reset sends submodule and is used for sending to reset control module the ready notice that resets after described preparation submodule completes the preparation that resets; The ready notice of described reset sends the reset trigger signal for triggering reset operation for pointing out described reset control module to described processor module;
Described reset operation submodule is used for receiving the laggard horizontal reset operation of reset trigger signal at described reception submodule.
11. reset management devices as claimed in claim 10, it is characterized in that, described preparation submodule comprises parameter and preserves submodule, for preserving current operational factor.
12. reset management devices as claimed in claim 11, it is characterized in that, described preparation submodule also comprises reason and preserves submodule, notifies corresponding reset circuit for preserving with described reset.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410140131.XA CN104978001A (en) | 2014-04-09 | 2014-04-09 | Reset management method and device |
| PCT/CN2014/082785 WO2015154344A1 (en) | 2014-04-09 | 2014-07-23 | Reset management method and device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410140131.XA CN104978001A (en) | 2014-04-09 | 2014-04-09 | Reset management method and device |
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| WO (1) | WO2015154344A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115220373A (en) * | 2021-04-19 | 2022-10-21 | 合肥本源量子计算科技有限责任公司 | Quantum measurement and control system and method and quantum computer |
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| CN1725706A (en) * | 2005-05-24 | 2006-01-25 | 杭州华为三康技术有限公司 | Reset processing method and device for system |
| CN1945555A (en) * | 2006-11-01 | 2007-04-11 | 华为技术有限公司 | Method and device for preventing internal storage data from losing |
| CN101149636A (en) * | 2007-10-23 | 2008-03-26 | 华为技术有限公司 | Repositioning system and method |
| CN101661318A (en) * | 2009-09-23 | 2010-03-03 | 中兴通讯股份有限公司 | System reset method, equipment, programmable logic device and CPU |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1851612A (en) * | 2006-01-06 | 2006-10-25 | 华为技术有限公司 | System and method for recording reset types |
| CN100397353C (en) * | 2006-07-26 | 2008-06-25 | 华为技术有限公司 | System and method for raising single-board exception handling ability |
| CN100517177C (en) * | 2006-10-19 | 2009-07-22 | 中兴通讯股份有限公司 | Combined type reset system processing method and device |
-
2014
- 2014-04-09 CN CN201410140131.XA patent/CN104978001A/en not_active Withdrawn
- 2014-07-23 WO PCT/CN2014/082785 patent/WO2015154344A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1725706A (en) * | 2005-05-24 | 2006-01-25 | 杭州华为三康技术有限公司 | Reset processing method and device for system |
| CN1945555A (en) * | 2006-11-01 | 2007-04-11 | 华为技术有限公司 | Method and device for preventing internal storage data from losing |
| CN101149636A (en) * | 2007-10-23 | 2008-03-26 | 华为技术有限公司 | Repositioning system and method |
| CN101661318A (en) * | 2009-09-23 | 2010-03-03 | 中兴通讯股份有限公司 | System reset method, equipment, programmable logic device and CPU |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115220373A (en) * | 2021-04-19 | 2022-10-21 | 合肥本源量子计算科技有限责任公司 | Quantum measurement and control system and method and quantum computer |
| CN115220373B (en) * | 2021-04-19 | 2024-04-05 | 本源量子计算科技（合肥）股份有限公司 | Quantum measurement and control system and method and quantum computer |
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| WO2015154344A1 (en) | 2015-10-15 |
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