CN103118240A - Method and device for monitoring reset signal of each module in a system - Google Patents
Method and device for monitoring reset signal of each module in a system Download PDFInfo
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- CN103118240A CN103118240A CN2011103662908A CN201110366290A CN103118240A CN 103118240 A CN103118240 A CN 103118240A CN 2011103662908 A CN2011103662908 A CN 2011103662908A CN 201110366290 A CN201110366290 A CN 201110366290A CN 103118240 A CN103118240 A CN 103118240A
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Abstract
The invention aims at providing a method and a device used for a reset signal of each module of a monitoring system. A signal monitoring device further comprises an edge detection device, a sampling device and a storage control device. The edge detection device is used for detecting whether the reset signal of each module of the system changes or not. When the edge detection device detects that the reset signal changes, the edge detection device triggers the sampling device to operate, and when the edge detection device is used for triggering the storage control device to carry out operation when meeting a preset trigger condition. The sampling device is used for collecting corresponding value of each reset signal and recording collected value in a log register. The storage control device is used for reading value in the log register into a storer. The signal monitoring device has the advantages of being capable of quickly positioning a fault module and improving error diagnosis efficiency..
Description
Technical field
The present invention relates to electronic applications, relate in particular to a kind of method and apparatus of the reset signal for the supervisory control system modules.
Background technology
In current hardware circuit, usually can use the integrated circuit of many complexity, wherein there is the reset signal of the corresponding disparate modules of a plurality of difference, be used for system is recovered from abnormal conditions.But the user can only obtain simple log information at present, and can't determine which module is abnormal conditions specifically occur in, can only be by after external analytical instrument, wait for passively the generation again of abnormal conditions in system, with the orientation problem module.The mode of this orientation problem module need to be used multiple analytical instrument, and operation is comparatively complicated, and the user can only wait for passively that abnormal conditions occur, and efficient is very low.
Summary of the invention
The method and apparatus that the purpose of this invention is to provide a kind of reset signal for the supervisory control system modules.
According to an aspect of the present invention, provide a kind of signal monitoring apparatus of the reset signal for the supervisory control system modules, comprise daily record register and memory, wherein, described signal monitoring apparatus also comprises:
Whether edge detecting device changes for detection of the reset signal of the modules of described system, with when reset signal having been detected and change, trigger the sampling apparatus executable operations, and, be used for triggering the memory control device executable operations when satisfying preset trigger condition;
Sampling apparatus, be used for to gather the corresponding value of each reset signal and with the value record that gathers in the daily record register;
Memory control device is used for the value write memory with the daily record register.
According to another aspect of the present invention, also provide a kind of method of the reset signal for the supervisory control system modules, wherein, said method comprising the steps of:
Whether the reset signal that a detects the modules of described system changes;
B when reset signal having been detected and changed, the operation of the corresponding value of each reset signal of triggering collection;
C gather the corresponding value of each reset signal and with the value record that gathers in the daily record register;
D triggers the operation with the value write memory in the daily record register when satisfying preset trigger condition;
E is with the value write memory in the daily record register.
Compared with prior art, the present invention has the following advantages: the user does not need to rely on other analytical equipments again, directly basis is determined the module of the reset signal of transmission saltus step by the value of the daily record register of reading in memory, further, when also comprising temporal information in the value of daily record register, which module what can determine fast also that different time points makes mistakes is respectively.Not only improve the efficient of diagnostic error, also simplified greatly operation.And, the solution of the present invention also can be applicable under the scene of the multiple operation that triggers based on the signal saltus step, for example, in the warning system that adopts a plurality of detectors such as a plurality of temperature, power supply, sound, monitor respectively the signal that each detector sends, to determine fast being signal generation saltus step of which detector etc.
Description of drawings
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 is the structural representation of a kind of reset signal for the supervisory control system modules of the present invention;
Fig. 2 is the method flow diagram of a kind of reset signal for the supervisory control system modules of the present invention;
Fig. 3 is the schematic diagram of the daily record register in a specific embodiment of the present invention.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Fig. 1 is the structural representation of the signal monitoring apparatus of a kind of reset signal for the supervisory control system modules of the present invention.Signal monitoring apparatus according to the present invention comprises daily record register and memory, and wherein, described signal monitoring apparatus also comprises edge detecting device 1, sampling apparatus 2 and memory control device 3.Wherein, according to each device of the present invention, can be integrated in same circuit module, also can be contained in respectively in different circuit modules and realize.
Wherein, described system comprises a plurality of modules, when modules sends reset signal to the component application circuit of system, self reset signal is sent to described signal monitoring apparatus, records the situation of change of the reset signal of modules for signal monitoring apparatus.Preferably, described system includes but not limited to lower module: 1) power reset module; 2) push-button reset module; 3) monitor reseting module; 4) software reset's module; 5) hardware reset module; 6) other reseting modules.
Wherein, whether edge detecting device 1 reset signal that detects the modules of described system changes.
Wherein, the variation of described reset signal includes but not limited to: 1) upwards saltus step; 2) saltus step downwards; 3) change waveform.Preferably, described edge detecting device 1 detects the whether saltus step downwards of reset signal of the modules of described system.
When edge detecting device 1 has detected reset signal and changes, trigger sampling apparatus 2 executable operations.
For example, when edge detecting device 1 detects the downward saltus step of reset signal of the push-button reset module that system comprises, send triggering signals to trigger sampling apparatus 2 executable operations to sampling apparatus 2.Wherein, described triggering signal includes but not limited to pulse signal.
Then, sampling apparatus 2 gather the corresponding values of each reset signal and with the value record that gathers in the daily record register.
Wherein, described daily record register comprises a plurality of flag bits corresponding with the reset signal of modules respectively at least, and wherein, each flag bit is used for the value of the record reset signal corresponding with it.
Preferably, those skilled in the art can determine according to actual conditions and demand not repeat them here the flag bit number of described daily record register.
For example, system comprises 6 modules, and the daily record register comprises 8 bit flag positions, and wherein, front 6 flags are corresponding reset signal from 6 modules respectively, respectively is: 1) from the power reset signal of power reset module; 2) from the push-button reset signal of push-button reset module; 3) from the monitor reset signal of monitor; 4) from software reset's signal of software reset's module; 5) from the hardware reset signal of hardware reset module; 6) from other reset signals of other reseting modules.Wherein, default the corresponding value of reset signal is 1 when reset signal is normal, and when reset signal generation saltus step, the corresponding value of reset signal is 0.Edge detecting device 1 detects the downward saltus step of reset signal of push-button reset module, and triggers sampling apparatus 2 executable operations, and the corresponding value of each reset signal that collects of sampling apparatus 3 is as shown in table 1 below:
| The |
1 |
| The push- |
0 |
| The |
1 |
| Software reset's |
1 |
| |
1 |
| |
1 |
Table 1
Then, the value that sampling apparatus 2 is corresponding with each reset signal shown in table 1 begins to be recorded in the daily record register from a high position successively, and the value that obtains each flag in the daily record register is followed successively by 10111100, and namely the value of this daily record register is 0xBC.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention, those skilled in the art should understand that, the corresponding value of each reset signal of any collection and with the implementation of value record in the daily record register that gathers all should be within the scope of the present invention.
Then, when satisfying preset trigger condition, edge detecting device 1 triggers memory control device 3 executable operations.
Wherein, described preset trigger condition includes but not limited to following any one:
1) reset signal of modules gathers complete.
For example, edge detecting device 1 detects sampling apparatus 2 and has executed sampling operation, sends enabling signal to memory control device 3, to trigger memory control device 3 executable operations.
2) current time information belongs to scheduled time condition.
For example, the time difference that edge detecting device 1 obtains the current point in time of system and edge detecting device 1 when triggering sampling apparatus 2, and judge this time difference greater than the predetermined time threshold value, transmitted is to memory control device 3, to trigger memory control device 3 executable operations.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention, those skilled in the art should understand that, any when satisfying preset trigger condition, trigger the implementation of memory control device executable operations, all should be within the scope of the present invention.
Then, memory control device 3 is with the value write memory in the daily record register.
Particularly, storage control 3 reads the address information of front write-once in described memory, and according to the current address information of this address information generation for the content of depositing current daily record register, and the value of daily record register is write in the corresponding memory cell of current address information.
Wherein, different according to the type of memory, memory control device 3 adopts different writing modes with in the value write memory in the daily record register.
Preferably, described memory control device 3 by with lower device with the value write memory in the daily record register: the first address acquisition device (not shown), the second address acquisition device (not shown), the first writing station (not shown) and the second writing station (not shown).
Wherein, in the first address acquisition device read memory, memory address is the current address information of storing in 0 memory cell.
Particularly, it is memory contents in 0 memory cell that the first address acquisition device reads memory address, and with this memory contents as current address information.
For example, in current storage, memory address is that the memory contents in 0 memory cell is 14, with 14 as current address information.
The second address acquisition device adds that with current address information predetermined offset is to obtain new storage address information.Wherein, predetermined offset is predetermined fixed value.
For example, as described in precedent, current address information is 14, and predetermined offset is 1, and the second address acquisition device determines that new storage address information is 15.
Then, the first writing station writes the value of described daily record register in the described new corresponding memory cell of storage address information.
For example, as in aforementioned sample device 3 for example as described in, the value of daily record register is 0xBC, and the new storage address information that the second address acquisition device obtains is 15, the first writing station writes 0xBC in address information is 15 memory cell.
Then, the second writing station memory address that described new memory address is write to described memory is in 0 memory cell.
For example, to write memory address be in 0 memory cell to the second writing station new storage address information 15 that the second address acquisition device is obtained.
Need to prove, wherein, the execution of described the second writing station and the first writing station does not have sequencing.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention those skilled in the art should understand that, any implementation with the value write memory in the daily record register all should be within the scope of the present invention.
Then, the user can be by reading the value of daily record register in described memory, according to the flag bit of the corresponding daily record register of reset signal of predetermined modules, determines the module of abnormal situation according to the value of the daily record register of reading.
For example, be 0xBC by the value of reading in memory, user's 66 system modules that difference corresponding front according to predetermined daily record register, determine to have occured extremely corresponding to the push-button reset module of the second flag bit.
Wherein, write content and undertaken by different ports respectively by the operation that memory is read content to memory, for example, signal monitoring apparatus writes content by port one to memory, and the user reads content by port 0 by memory.
As one of the preferred embodiments of the present invention, wherein, described signal monitoring apparatus also comprises be used to the timer that obtains the current time value, and described daily record register also comprises for a plurality of flag bits of storage from the time value of described timer; Wherein, described sampling apparatus 2 also comprises timing sampling apparatus (not shown).
Wherein, the timing sampling apparatus gathers the corresponding value of each reset signal, and value and the current time value that gathers is recorded in the daily record register.
For example, with reference to daily record register shown in Figure 3, this daily record register comprises 32 flag bits, the value from the reset signal of 8 modules of system that the timing sampling apparatus obtains is sequentially respectively 10111111, the time value that timer obtains is 0x0000F7, and front 8 corresponding values of reset signal that are used for 8 modules of storage system of predetermined daily record register, rear 24 are used for value memory time, the timing sampling apparatus is recorded in value and the time value of front 8 bit flag positions in the daily record register, and the value that obtains the daily record register is 0xBF0000F7.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention, those skilled in the art should understand that, the corresponding value of each reset signal of any collection, and the value that gathers and current time value are recorded in implementation in the daily record register, all should be within the scope of the present invention.
According to the solution of the present invention, the user does not need to rely on other analytical equipments again, directly basis is determined the module of the reset signal of transmission saltus step by the value of the daily record register of reading in memory, further, when also comprising temporal information in the value of daily record register, which module what can determine fast also that different time points makes mistakes is respectively.Not only improve the efficient of diagnostic error, and simplified greatly operation.
Fig. 2 is the method flow diagram of a kind of reset signal for the supervisory control system modules of the present invention.The method according to this invention comprises step S1, S2, S3, S4 and S5.
In step S1, whether the reset signal that signal monitoring apparatus detects the modules of described system changes.
Wherein, the variation of described reset signal includes but not limited to: 1) upwards saltus step; 2) saltus step downwards; 3) change waveform.Preferably, described signal monitoring apparatus detects the whether saltus step downwards of reset signal of the modules of described system.
In step S2, when reset signal having been detected and changed, the operation of the corresponding value of each reset signal of signal monitoring apparatus triggering collection.
For example, when signal monitoring apparatus detected the downward saltus step of reset signal of push-button reset module, signal monitoring apparatus generated triggering signal with the operation of the corresponding value of each reset signal of triggering collection.Wherein, described triggering signal includes but not limited to pulse signal.
In step S3, signal monitoring apparatus gather the corresponding value of each reset signal and with the value record that gathers in the daily record register.
Wherein, described daily record register comprises a plurality of flag bits corresponding with the reset signal of modules respectively at least, and wherein, each flag bit is used for the value of the record reset signal corresponding with it.
Preferably, those skilled in the art can determine according to actual conditions and demand not repeat them here the flag bit number of described daily record register.
For example, system comprises 6 modules, and the daily record register comprises 8 bit flag positions, and wherein, front 6 flags are corresponding reset signal from 6 modules respectively, respectively is: 1) from the power reset signal of power reset module; 2) from the push-button reset signal of push-button reset module; 3) from the monitor reset signal of monitor; 4) from software reset's signal of software reset's module; 5) from the hardware reset signal of hardware reset module; 6) from other reset signals of other reseting modules.Wherein, default the corresponding value of reset signal is 1 when reset signal is normal, and when reset signal generation saltus step, the corresponding value of reset signal is 0.Signal monitoring apparatus detects the push-button reset module in step S1 reset signal sends saltus step, and the corresponding value of each reset signal that collects of signal monitoring apparatus is as shown in table 2 below:
| The power reset |
1 |
| The push- |
0 |
| The monitor reset |
1 |
| Software reset's |
1 |
| Hardware reset |
1 |
| Other reset signals | 1 |
Table 2
Then, the value that signal monitoring apparatus is corresponding with each reset signal shown in table 2 is begun to be recorded in the daily record register by a high position successively, and the value that obtains each flag in the daily record register is followed successively by 10111100, and namely the value of this daily record register is 0xBC.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention, those skilled in the art should understand that, the corresponding value of each reset signal of any collection and with the implementation of value record in the daily record register that gathers all should be within the scope of the present invention.
Then, in step S4, when satisfying preset trigger condition, signal monitoring apparatus triggers the operation with the value write memory in the daily record register.
Wherein, described preset trigger condition includes but not limited to following any one:
1) reset signal of modules gathers complete.
For example, signal monitoring apparatus detects sampling operation and is finished, and sends triggering signal, to trigger the operation with the value write memory in the daily record register.
2) current time information belongs to scheduled time condition.
For example, time difference when signal monitoring apparatus obtains the current point in time of system and execution in step S2, and judge this time difference greater than the predetermined time threshold value, transmitted is to memory control device 5, to trigger the operation with the value write memory in the daily record register.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention, those skilled in the art should understand that, any when satisfying preset trigger condition, triggering all should be within the scope of the present invention with the implementation of the operation of the value write memory in the daily record register.
In step S5, signal monitoring apparatus is with the value write memory in the daily record register.
Particularly, signal monitoring apparatus reads the address information of front write-once in described memory, and according to the current address information of this address information generation for the content of depositing current daily record register, and the value of daily record register is write in the corresponding memory cell of current address information.
Wherein, different according to the type of memory, signal monitoring apparatus adopts different writing modes with in the value write memory in the daily record register.
Preferably, in step S5, described signal monitoring apparatus is by carrying out following steps with the value write memory in the daily record register: step S51 (not shown), S52 (not shown), S53 (not shown) and S54 (not shown).
In step S51, in the signal monitoring apparatus read memory, memory address is the current address information of storing in 0 memory cell.
Particularly, it is memory contents in 0 memory cell that signal monitoring apparatus reads memory address, and with this memory contents as current address information.
For example, in current storage, memory address is that the memory contents in 0 memory cell is 14, signal monitoring apparatus with 14 as current address information.
In step S52, signal monitoring apparatus adds that with current address information predetermined offset is to obtain new storage address information.Wherein, predetermined offset is predetermined fixed value.
For example, as described in precedent, current address information is 14, and predetermined offset is 1, and signal monitoring apparatus determines that new storage address information is 15.
Then, in step S53, signal monitoring apparatus writes the value of described daily record register in the described new corresponding memory cell of storage address information.
For example, as in abovementioned steps S3 for example as described in, the value of daily record register is 0xBC, and the new storage address information that signal monitoring apparatus obtains is 15, signal monitoring apparatus writes 0xBC in address information is 15 memory cell.
Then, in step S54, the memory address that signal monitoring apparatus writes to described memory with described new memory address is in 0 memory cell.
For example, to write memory address be in 0 memory cell to the signal monitoring apparatus new storage address information 15 that will obtain in step S42.
Need to prove, the execution of described step S53 and step S54 does not have sequencing.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention those skilled in the art should understand that, any implementation with the value write memory in the daily record register all should be within the scope of the present invention.
Then, the user can be by reading the value of daily record register in described memory, according to the flag bit of the corresponding daily record register of reset signal of predetermined modules, determines the module of abnormal situation according to the value of the daily record register of reading.
For example, be 0xBC by the value of reading in memory, user's 66 system modules that difference corresponding front according to predetermined daily record register, determine to have occured extremely corresponding to the push-button reset module of the second flag bit.
Wherein, write content and undertaken by different ports respectively by the operation that memory is read content to memory, for example, signal monitoring apparatus writes content by port one to memory, and the user reads content by port 0 by memory.
As one of the preferred embodiments of the present invention, wherein, described daily record register also comprises for a plurality of flag bits of storage from the time value of described timer; Wherein, described method also comprises step S6 (not shown), and described step S3 comprises step S31 (not shown).
In step S6, signal monitoring apparatus obtains the current time value.
Then, in step S31, signal monitoring apparatus gathers the corresponding value of each reset signal, and value and the current time value that gathers is recorded in the daily record register.
For example, with reference to daily record register shown in Figure 3, this daily record register comprises 32 flag bits, the value from the reset signal of 8 modules of system that signal monitoring apparatus obtains is sequentially respectively 10111111, and the time value that timer obtains is 0x0000F7, and front 8 corresponding values of reset signal that are used for 8 modules of storage system of predetermined daily record register, rear 24 are used for value memory time, signal monitoring apparatus is recorded in value and the time value of front 8 bit flag positions in the daily record register, and the value that obtains the daily record register is 0xBF0000F7.
Need to prove, above-mentioned for example only for technical scheme of the present invention is described better, but not limitation of the present invention, those skilled in the art should understand that, the corresponding value of each reset signal of any collection, and the value that gathers and current time value are recorded in implementation in the daily record register, all should be within the scope of the present invention.
According to the solution of the present invention, the user does not need to rely on other analytical equipments again, directly basis is determined the module of the reset signal of transmission saltus step by the value of the daily record register of reading in memory, further, when also comprising temporal information in the value of daily record register, which module what can determine fast also that different time points makes mistakes is respectively.Not only improve the efficient of diagnostic error, and simplified greatly operation.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and in the situation that do not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, therefore is intended to be included in the present invention dropping on the implication that is equal to important document of claim and all changes in scope.Any Reference numeral in claim should be considered as limit related claim.In addition, obviously other unit or step do not got rid of in " comprising " word, and odd number is not got rid of plural number.A plurality of unit of stating in system's claim or device also can be realized by software or hardware by a unit or device.The first, the second word such as grade is used for representing title, and does not represent any specific order.
Claims (10)
1. a signal monitoring apparatus that is used for the reset signal of supervisory control system modules, comprise daily record register and memory, and wherein, described signal monitoring apparatus also comprises:
Whether edge detecting device changes for detection of the reset signal of the modules of described system, with when reset signal having been detected and change, trigger the sampling apparatus executable operations, and, be used for triggering the memory control device executable operations when satisfying preset trigger condition;
Sampling apparatus, be used for to gather the corresponding value of each reset signal and with the value record that gathers in the daily record register;
Memory control device is used for the value write memory with the daily record register.
2. signal monitoring apparatus according to claim 1, wherein, described preset trigger condition includes but not limited to following any one:
The reset signal of-modules gathers complete;
-current point in time belongs to predetermined amount of time.
3. signal monitoring apparatus according to claim 1 and 2, wherein, described memory control device also comprises:
The first address acquisition device is used for the read memory memory address and is the current storage address information of storing in 0 memory cell;
The second address acquisition device is used for current address information is added that predetermined offset is to obtain new storage address information;
The first writing station is for write the value of described daily record register in the described new corresponding memory cell of storage address information;
The second writing station, being used for the memory address that described new memory address writes to described memory is 0 memory cell.
4. the described signal monitoring apparatus of any one according to claim 1 to 3, wherein, described daily record register comprises a plurality of flag bits corresponding with the reset signal of modules respectively at least, and wherein, each flag bit is used for the value of the record reset signal corresponding with it.
5. signal monitoring apparatus according to claim 4, wherein, described signal monitoring apparatus also comprises be used to the timer that obtains the current time value, described daily record register also comprises for a plurality of flag bits of storage from the time value of described timer; Wherein, described sampling apparatus also comprises:
The timing sampling apparatus is used for gathering the corresponding value of each reset signal, and value and the current time value that gathers is recorded in the daily record register.
6. method that is used for the reset signal of supervisory control system modules wherein, said method comprising the steps of:
Whether the reset signal that a detects the modules of described system changes;
B when reset signal having been detected and changed, the operation of the corresponding value of each reset signal of triggering collection;
C gather the corresponding value of each reset signal and with the value record that gathers in the daily record register;
D triggers the operation with the value write memory in the daily record register when satisfying preset trigger condition;
E is with the value write memory in the daily record register.
7. method according to claim 6, wherein, described preset trigger condition includes but not limited to following any one:
The reset signal of-modules gathers complete;
-current point in time belongs to predetermined amount of time.
8. according to claim 6 or 7 described methods, wherein, described step e comprises the following steps:
In-read memory, memory address is the current storage address information of storing in 0 memory cell;
-current address information is added that predetermined offset is to obtain new storage address information;
-write the value of described daily record register in the described new corresponding memory cell of storage address information;
-memory address that described new memory address is write to described memory is in 0 memory cell.
9. the described method of any one according to claim 6 to 8, wherein, described daily record register comprises a plurality of flag bits corresponding with the reset signal of modules respectively at least, and wherein, each flag bit is used for the value of the record reset signal corresponding with it.
10. method according to claim 9, wherein, described daily record register comprises that also described method is further comprising the steps of for a plurality of flag bits of storage from the time value of described timer:
-obtain the current time value;
Wherein, described step c also comprises:
-gather the corresponding value of each reset signal, and value and the current time value that gathers is recorded in the daily record register.
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