JPS5963851A - Electronic exchange - Google Patents

Abstract

PURPOSE:To freeze temporally the status of the whole processors to collect necessary information by connecting plural processors by a common bus line and giving non-maskable interruption from a processor detected a fault to an other processor. CONSTITUTION:The titled device is provided with plural processors 10, 20, 30, 40 monitoring and controlling a channel switch 1, subscriber's circuits 11 (11-1-11-n) and trunk circuits 41(41-1-41-n) and a fault processor 50 processing a fault when an optional processor out of the plural processors detectes the fault is connected to the common bus line. Non-maskable interruption is applied from the processor detecting the fault to all the other processors to save the status of these processors, the processor detecting the fault sends fault information to the fault processor 50. The fault processor 50 analyzes the fault information and sends a command signal to the plural processors.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an electronic switching system consisting of a control system with functions distributed to a plurality of processors.Conventional configuration and problems with the conventional electronic switching system In most cases, there is only one processor, so even if a fault occurs, that processor will start processing the fault, and the state of the system will change during processing, so the state at the time of occurrence will not be lost. There were times when I got caught. However, in this case, it could be avoided relatively easily by ensuring priority processing.

In addition, in an electronic switching system that distributes the functions and loads of multiple control systems among multiple processors, multiple processors operate in parallel, so when a failure occurs in any processor, other processors can use the system's memory. There were problems such as the fact that the status had changed since then, making it difficult to collect information necessary for troubleshooting. - Purpose of the Invention In order to solve the above-mentioned problems, the present invention is designed to temporarily freeze the state of other processors and collect necessary information when a failure occurs in any processor. It is.

Structure 7 of the Invention In order to achieve the above object, the present invention connects a plurality of processors that control communication path switches, subscriber circuits, etc. and a fault processing processor by a common path line, and allows the processor that has detected a fault to The idea is to enable failure handling to occur after a non-maskable interrupt light is applied to the processor.

DESCRIPTION OF EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS. 1 and 2. Here, FIG. 1 is a block diagram of an electronic exchange having a functionally distributed control system, and FIG. 2 is a block diagram in which only the control system is extracted. Reference numeral 1 denotes a communication path switch for switching and connecting subscriber circuits, trunk circuits, etc., which will be described later. 2 is a common bus, 3 is a simultaneous interrupt line, and 4 is a common bus 2. −
The bus use contention arbitration line is connected to the simultaneous interrupt line 3, and its details will be explained with reference to FIG. 1o is a subscriber control processor connected to the common bus 2 and the simultaneous interrupt line 3, which monitors and controls a plurality of subscriber circuits 11-1 to 11-n connected to the communication path switch 1. be. 12
-1 to 12-n are telephones, 2o is a console control processor, and a plurality of console interface circuits 21-1 to 2'
22-1 to 22-n.
03o is a connection processor for controlling the communication path switch 1 and simultaneously connecting calls; 4o is a trunk control processor; Connected trunk circuit 41-
06o, which monitors and controls the processors 1 to 41-n, is a failure processing processor that handles a failure when a failure occurs in any processor, and has an input/output terminal 51.

Next, referring to FIG. 2, each of the aforementioned processors 10
, 20, 30, 40, and 50 are all connected by common bus 2 and simultaneous interrupt line 3.014゜24.34.4
4.54 is a request signal line for requesting the use of the simultaneous interrupt line 3 and the common bus 2; one end is connected to each processor 10;
, 20 , 30 , 40 .

5o, and the other end is connected to the bus use contention arbitration circuit 4. 15, 25, 35, 45.degree. 56 are bus use permission signal lines, which are similarly connected to the bus use contention arbitration circuit 4. Here, the bus use contention arbitration circuit 4 will be described in detail. The request signal lines 14, 24,
34, 44, and 54, select any one from among the requested ones, and send the permission signal lines 15.2B, 35.
, 45.55, the right to use the common bus 2 and the simultaneous interrupt line 3 is given to any one of the processors 10.20.30.40.50.

Next, the operation of one embodiment of the present invention having the above configuration will be explained.

First, in order to further clarify the effects of an embodiment of the present invention, a hypothetical case will be described in which, for example, the subscriber control processor 1o communicates with the trunk control processor 4o via the common bus 2.

At this time, if the subscriber control processor 1o detects a fault, if the subscriber control processor 1o simply notifies the fault processing processor 6o of the fault via the common bus 2, the trunk control processor 4o will process In addition, the other processors 30, 20, etc. proceed with their processing regardless of the abnormality detection of processor 1o, and when the fault is notified to the faulty processor 6°, the call status table etc. of the connected processor □30, etc. This may be different from what it was immediately after the failure was detected. In an embodiment of the present invention, in such a case, the subscriber control processor 1 which has detected the fault first requests the bus use contention arbitration circuit 4 via the request signal line 14 to use the simultaneous interrupt line 3 and the common bus 2. Request and permission signal line 1
After sensing the signal 5 and checking that permission is received, the simultaneous interrupt line 3 is activated to issue a masked interrupt to all other processors. Immediately after that, all processors other than the subscriber control processor 1o are interrupted simultaneously, so the state of the processors is saved and the fault handling processor 50
Wait for a treatment request to arrive via the common bus 2. On the other hand, the subscriber control processor 1o transmits the fault information to the fault processing processor 6o via the common bus 2 and sends the fault information to the request signal line 14.
is returned to inactive and waits for a treatment request from the fault processing processor 50. When the failure processing processor 5o receives the failure information, it analyzes the content, secures the right to use the bus through the request signal line 64, and requests reading of data and status on the memory of each processor 10, 20, 30, 40, etc. instructions to each processor 10.20,3
At 0.40, the necessary data was received through the transmission common bus 2, and the results were output to the input/output terminal 51 as necessary.Based on that, after receiving the operator's input instructions, each process , 20, 30, and 40 to resume operation and continue operation.

As an example, the operation when the subscriber control processor 1o detects a fault has been described, but even when another processor detects a fault, the same operation as described above is used to detect the fault information and take action.

Effects of the Invention As described above, according to the present invention, when a fault occurs in any processor, the state at the time of occurrence is temporarily frozen for all other processors, necessary information is collected, and the system is sent to the fault handling processor. It is capable of handling failures and issuing instructions appropriately.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an electronic exchange according to an embodiment of the present invention, and Fig. 2 is a block diagram of the main parts thereof. , 3... - simultaneous interrupt line, 10... subscriber control processor, 11-1 to 11-n... subscriber circuit, 2o...... Table control processor, 3o
... Connection processor, 40 ... Trunk control processor, 41-1 to 41-n ... Trunk circuit, 5o ... Failure processing processor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 2

Claims (1)

[Claims] At least a subscriber circuit and a trunk circuit are connected to a communication path switch for switching and connecting them, and a plurality of processors are provided for monitoring and controlling the communication path switch, the subscriber circuit, the trunk circuit, etc.; A plurality of processors and a fault processing processor that performs processing when a fault is detected by any processor among the plurality of processors are connected to a common path line, and all other processors from the processor that detected a fault among the plurality of processors are A non-maskable interrupt is issued to the processors, the states of those processors are saved, and the processor that detects the fault sends fault information to the fault processing processor, and the fault processing processor analyzes and processes the fault information and processes the fault information. An electronic exchange characterized in that it sends an instruction signal to a processor.