JPS6322676B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more particularly, the present invention relates to an information processing method, and more particularly, a method for processing information between a buffer memory in a peripheral processing unit connected to a bus of a central processing unit operating in a program mode and a main memory. It relates to an information processing method for transferring data.

Conventionally, when multiple central processing units (hereinafter referred to as CPUs) are combined into one system, main memory 1 is connected to multiple CPUs 2 as shown in Figure 1.
As shown in Figure 2, each CPU 2A-2D occupies its own memory 1A-1D, and the channels 4A-4D and the adapter There is a channel coupling method (loosely coupled multiprocessor) in which each of the CPUs 2A to 2D communicates with each other via the CPU 5.

In the shared memory combination method shown in FIG. 1, under the control of a common operating system stored in main memory 1, multiple CPUs 2A to 2D alternately use shared memory 1, or no one uses it. A method is adopted in which the shared memory 1 is used after confirming this.

On the other hand, in the channel coupling method shown in FIG. 2, each CPU 2A to 2D is
uses its own and other memory, or only a specific CPU2A uses all memory1
A to 1D are managed, and with permission from this CPU 2A, other CPUs 2B to 2D use their own or other memory.

For example, in a functionally distributed electronic exchange, there is a main memory that stores all information such as subscribers, lines, trunks, etc., a CPU, a processing device dedicated to call detection and dial reception, a processing device dedicated to internal connection, Processing is performed by separating into multiple peripheral processing units (hereinafter referred to as PPUs), such as processing units dedicated to input/output connections.

In this case, if the shared memory combination method shown in Figure 1 is used to combine information between one CPU and multiple PPUs, the memory bus Because delays can reduce the system's processing capacity,
If PPU is placed, it will be extremely disadvantageous.

On the other hand, in the case of a channel connection method using a channel bus as shown in Figure 2, if the CPU is 2A and the main memory is 1A, the other memory is 1B.
~1D can be treated as a buffer memory provided within PPU2B~2D. However, in a system using a channel bus, there is a fixed amount of time spent in starting up a channel, and this time cannot be ignored. That is, since the transfer of information from the CPU to the PPU is performed in response to an event (for example, a call), it is small-scale and frequent, and it is extremely disadvantageous that it takes time to start up a channel each time.

There is also a so-called program mode information transfer method, in which the parent device takes the initiative and executes the program.・It is an information transfer method performed between the CPU's main memory and input/output devices via a bus, and is not considered as information transfer between multiple CPUs.

The purpose of the present invention is to solve these problems by transferring multiple words of data between main memory and buffer memory, even when there are long distances between the CPU and PPU, and even when there are small and frequent requests. The object of the present invention is to provide an information processing method that can perform the following at high speed and easily.

The information processing method of the present invention connects the CPU and PPU with a bus that operates in program mode, and outputs the peripheral processing unit number and buffer memory read/write control codes from the CPU via the bus. After continuously transferring data for the number of transferred words, a transfer end code is output,
It is characterized by data transfer between the main memory and the buffer memory in the PPU.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is an operational block diagram of an information processing system for explaining an embodiment of the present invention.

The main memory 10 and the CPU 20 have a memory address bus 101 and a memory answer bus 102.
connected with. There are also buses connected to the CPU 20 and operating in program mode, namely an external address bus 201 and an external answer bus 20.
2, a plurality of PPUs 30A to 30N are connected in parallel. Each PPU 30A to 30N is provided with a buffer memory (BM) 301, a processor unit (PU) 302, and a buffer memory controller (BMC) 303. The buffer memory controller 303 is the CPU 20
The information line 304 controls access to the buffer memory 301 from the processor unit 302 and the processor unit 302, respectively.
This line connects the unit 302 and the buffer memory 301, and may be operated in either channel mode or program mode.

That is, as described above, when data is transferred between the processor unit 302 and the buffer memory 301, it is better to combine in channel mode if the frequency is infrequent but a relatively large amount of data is transferred. On the other hand, if the amount of data transferred is small but the frequency is high, it is better to combine in program mode, so either one may be selected depending on the main purpose function of the PPU 30. In other words, it is selected depending on the type of input/output device used as a terminal; for example, if it is to control a call detection device, a call path switch, a trunk, etc. of a functionally distributed electronic exchange, it is combined in program mode, while word processor Translation, Kanji conversion, etc. control often involves continuous processing, so they are combined in channel mode.

In FIG. 3, a data transfer request from CPU 20 to buffer memory 301 is accepted by a single instruction, a block transfer instruction.

FIG. 4 is an operational flow chart of a block transfer instruction.

The CPU 20 reads a program instruction from the main memory 10, decodes it with a decoder, and if it is a request for a block transfer instruction, the CPU 20
The number of words to be transferred, the destination peripheral processing device number, and the source or destination address in the main memory 10 are read from the work register in the main memory 10 or from a specific address in the main memory 10 (step 12).

Writing, that is, buffer data from main memory 10.
In the case of transfer to the memory 301, one word of the transfer data stored in the main memory 10 is fetched (step 16). Next, edit the transfer data, the transfer destination peripheral processing device number, the control code for writing to the buffer memory 301, and the code being transferred (step 17).
1 (step 18). The data sent to the external address bus 201 is received only by the device with the matching peripheral processing device number, and a write operation is executed in the buffer memory 301.

When the buffer memory 301 finishes writing one word, the buffer memory controller 303 immediately responds to the external answer bus 202 to that effect (step 19).

On the other hand, when the CPU 20 side receives the response signal from the PPU 30, it subtracts the number of transferred words (step
23), update memory address (step
twenty four).

Then, it is determined whether the number of transferred words has become "0" (step 25), and if the result is not "0", it is determined whether the number of transferred words has become one word remaining (step 13). If the number of transferred words is still more than one word, the next transferred data is subsequently fetched from the main memory 10 (step 16), and the CPU 20 and PPU 30 repeat the same process as described above (steps 17 to 25).

On the other hand, if the number of transferred words is one word,
The CPU 20 replaces the end display code indicating that the data is the final data with the code being transferred, and sends it to the external address bus 201 (step 14).
When the PPU 30 side receives the end code, it knows that the final data has been received, and the buffer memory 301 becomes full.
Whether the buffer memory 301 has become full can be easily determined by interrupting the processor unit 302, or conversely by scanning from the processor unit 302.

Next, in the case of a read by the CPU 20, that is, in the case of a transfer from the buffer memory 301 to the main memory 10, step 16 in FIG. The process is the same as in the case of . That is, there is no need to fetch transfer data from the main memory 10, but instead it is necessary to store the data read from the buffer memory 301 into the main memory 10 from the external answer bus 202. Also, step
At 18, the read code must be sent to the PPU 30.

Note that these series of instructions are executed by the CPU 20.
If it is controlled by a micro program, it can be realized using a micro program, and the CPU2
If 0 is a CPU with wired logic, it can be realized by adding hardware.

Additionally, if a failure interrupt, input/output interrupt, etc. occurs during the execution of a series of these instructions, it is only necessary to set whether or not to allow handling of the cause of the interrupt using other software. It is not necessary to provide any means for interrupts.

As explained above, according to the present invention, the CPU
Functionally distributed electronic If the processing method of the present invention is applied to an information processing system such as a switchboard that transfers a small number of words but transfers frequently,
This enables faster processing than the method that combines channels and buses, and can improve processing performance.

[Brief explanation of the drawing]

1 and 2 are diagrams each showing a conventional method for coupling multiple processing devices, FIG. 3 is an operational block diagram of an information processing method showing an embodiment of the present invention, and FIG. 4 is a block transfer according to the present invention. This is a flow chart of the instructions. 1, 1A to 1D, 10: Main memory, 2A to 2
D, 20: Central processing unit (CPU), 4A to 4D:
Channel, 5: Adapter, 30A to 30N: Peripheral Processing Unit (PPU), 301: Buffer Memory (BM), 302: Processor Unit (PU),
303: buffer memory controller (BMC), 101: memory address bus, 1
02: Memory answer bus, 201: External address bus, 202: External answer bus.

Claims (1)

[Claims] 1. In an information processing system equipped with a central processing unit and a main memory, the central processing unit and the peripheral processing unit are connected by a bus that operates in a program mode, and the peripheral processing unit number and the peripheral processing unit number are transmitted from the central processing unit via the bus. Reading buffer memory,
After outputting a write control code and continuously executing data transfer for the specified number of transfer words, output a transfer end code and transfer data between the main memory and the buffer memory in the peripheral processing unit. An information processing method characterized by: