JP2000284812A - Programmable controller and its input/output control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller capable of performing a data input/output processing by shortening the tact cycle comparatively even when the number of I/O modules increases. SOLUTION: A frame rotates on a serial link bus 1. A tact number is set on the starting part of the frame. The tact number is updated whenever rotation is completed. An I/O module as an input device (Di) 30 is provided with a serial link control LSI 31, a buffer 32, etc. Relating to the serial link control LSI 31, a cycle information storage area and a phase information storage area are included in a memory, etc., inside it, whether the frame is received in output timing of the present station or not is judged based on the 'tact number', its cycle information and phase information to be included in the frame when the frame is received and outputs data which is stored in the buffer 32 only when the frame is received in the output timing of the present station.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller and its input / output control method.

[0002]

2. Description of the Related Art In recent years, plants and factories have realized FA (factory automation) by using many programmable controllers (hereinafter referred to as PCs) for sequence control of machines and devices.

[0003] A certain PC system has a configuration in which a CPU module for executing programs, performing data arithmetic processing, and the like, and an I / O module for inputting and outputting process data to and from a control device are connected by a bus (such as a system bus). It has become. These modules exchange data with each other via a system bus, and perform control processing of connected devices.

When the PC system has a plurality of CPU modules, each CPU module asynchronously performs operation processing, and also performs input / output processing of process data to the I / O module asynchronously. If each of the CPU modules performs the processing asynchronously, a conflict may occur between the CPU modules for input / output processing. In this case, only one CPU module can perform input / output processing,
The other CPU modules wait for the execution of the process during that time.

Further, since each I / O module outputs process data from a connected device in real time and requires data from a CPU module,
When a plurality of CPU modules perform processing in cooperation with each other,
If synchronization is not performed between CPU modules or tasks, there may be a problem that different data is recognized and processed as the same data.

[0006] In response to such a problem, the applicant of the present invention disclosed in the prior application (Japanese Patent Application No. 10-148648)
A PC capable of synchronously exchanging data between PU modules and tasks during multitask processing and an input / output control method for the PC have been proposed.

[0007]

In the system of the prior application (Japanese Patent Application No. 10-148648) by the applicant of the present invention,
There were the following problems.

That is, in the above-mentioned prior application, data transfer for all I / O modules is performed during one tact cycle. Therefore, as the number of I / O modules connected to the system increases, the data amount increases. For example, if the tact cycle is not extended, processing cannot be performed within one tact cycle.

When a multi-CPU is constructed, each CPU operates in synchronization with the tact cycle in the method of the above-mentioned application, but does not synchronize until the operation of each CPU task.

[0010] An object of the present invention is to make it possible to shorten the tact cycle relatively even when the number of I / O modules increases, and to achieve synchronization between tasks of each CPU when a multi-CPU is constructed. An object of the present invention is to provide a programmable controller and an input / output control method thereof.

[0011]

A first programmable controller according to the present invention comprises at least one or more CPs.
In a programmable controller having a U module and a plurality of I / O modules connected to a bus, a frame used for data transfer on the bus is added with an identification number updated at a predetermined rule every tact cycle. Each I / O module determines whether or not it is the data output timing to the CPU module according to the identification number of the frame to be received, and if it is determined that the data output timing, the data is added to the frame. And data output control means for transferring the data.

According to the first programmable controller, for example, in the data transfer of the total frame system, each I / O module outputs the data at its own timing based on the identification number added to the frame. It is determined whether or not there is, and if so, data is added to the frame and output. in this way,
By not adding data of all I / O modules to a certain frame but adding and transferring data of some I / O modules, the amount of data flowing on the bus can be reduced. Therefore, even if the number of I / O modules is large, the cycle time of the tact can be set relatively short.

A second programmable controller according to the present invention is a programmable controller comprising at least one or more CPU modules and a plurality of I / O modules connected to a bus. To the I / O module upon receiving the token and outputting the data in accordance with the identification number added to the token. An output processing unit is provided for determining a target I / O module and outputting data to the data output target I / O module for each tact cycle.

According to the second programmable controller, for example, in the data transfer of the multicast method, the CPU module makes all the I / Os every tact cycle.
By outputting data to only some I / O modules instead of outputting data to O modules, the amount of data flowing on the bus can be reduced.
Accordingly, even if the number of I / O modules is large, the tact cycle can be set relatively short.

The data output by the output processing means of the CPU module is transferred on the bus in a frame to which the identification number has been added, and each of the I / O modules is addressed to its own module in the received frame. If the data exists, the data is fetched, and based on the identification number of the frame to be received and the output timing data set / stored in advance, the fetched data is extracted when a predetermined condition is satisfied. Output to control device of own module.

As described above, each I / O module side sets the data output timing to its own control device independently of the data output timing to each I / O module determined by the CPU module side. By making the determination, for example, even when a plurality of I / O modules need to synchronize and output data to the control device of the own module, the CP for each of these I / O modules
Even if the data output timing on the U module side is different, the data can be synchronously output regardless of the timing.

A third programmable controller according to the present invention is a programmable controller comprising a plurality of CPU modules and a plurality of I / O modules connected to a bus. To each of the CPU modules, an activation condition storing means for storing an activation condition of each task of the own module, and an activation condition stored in the activation condition storage means. Task activation control means for determining whether or not the activation condition is satisfied based on the identification number of the frame to be activated and activating the task for which the activation condition is satisfied.

According to the third programmable controller, especially when a multi-CPU is constructed, the operation of each CPU task can be performed in synchronization with the tact cycle.

Also, for example, the identification number is configured as bit pattern data, and each of the I / O modules or the CPU module sets / stores data set / stored for performing the determination or determination based on the identification number. As bit pattern data, the configuration for making the above-mentioned determination or determination can be realized with simpler hardware than in the case where the identification number is provided as numeric data.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of an entire PC system to which the present embodiment is applied.

The PC system shown in FIG. 1 has a network configuration in which one or a plurality of CPU modules 2 and a plurality of I / O modules 3 are connected by a serial link bus 1 having a ring-type transmission topology. Each module connected to the serial link bus 1 is set with a station number for uniquely identifying each module as a station on the network. In the figure, it is assumed that the CPU module 2 and the I / O module 3 are connected in total to 16 stations, and that each station is set to # 0 to # 16 as its station number.

The basic configuration / operation of the PC system shown in FIG. 1 is described in the above-mentioned prior application (Japanese Patent Application No. 10-14864).
Since the system is substantially the same as the system described in 8), only the outline will be described here.

First, each module in the PC, such as the CPU module 2 and the I / O module 3 serving as a station on the network, has a serial link control LSI (not shown) therein, and via this serial link control LSI. It is connected to the serial link bus 1.

A frame flowing on the network circulates in a certain direction on the serial link bus 1 (for example, in the direction indicated by an arrow in FIG. 1), and the serial link control LS
I takes in the frame transmitted from the upstream station into its own reception buffer, sends it to the downstream station as it is if there is no data for itself, and takes in the data if it has data for itself. In this way, the frame data circulates on the serial link bus 1 in a certain direction.

Data transfer at the time of "reception processing" in which the CPU module 2 receives data from the I / O module 3 or the like is performed by a total frame method. The data transfer at the time of “transmission processing” for outputting data from the CPU module 2 to the I / O module 3 and the like is performed by a multicast method.

In the total frame method, each station of the I / O module 3 adds its own data to one circulating frame on the serial link bus 1 having a topology on a ring, and the frame is transferred to the serial link bus. This is a transmission system in which own station data is transmitted and other station data is received by making two rounds of No. 1 so that each station can share data of other stations and increase transmission efficiency.

In the multicast method, a transmission token for circulating a free token for multicast communication on the serial link bus 1 and requesting data transmission (output data to be output to an output device) is prepared. The station for which transmission permission is set) secures a free token and transmits a multicast frame instead.
The multicast frame circulates on the serial link bus 1, and the station on the network that has received the multicast frame relays it to the downstream and circulates the same, and based on the setting contents of the output data in the frame, sends the multicast frame to its own station. Import data.

Since the details of the total frame system and the multicast system have been described in the above-mentioned prior application, the description is omitted here. Hereinafter, first, FIGS.
The data reception process of the CPU module 2 according to the total frame method in the present embodiment will be described with reference to FIG.

In the above-mentioned prior application, the time of the tact cycle is, for example, 1 msec * N (the value of N varies according to the number of stations on the serial link bus 1), and the time of the tact cycle increases as the number of stations increases. However, in the present embodiment, the tact cycle can be set relatively short even if the number of stations increases.

This is the first embodiment. Note that C
The PU module 2 defines four types of fixed-period tasks, each having a period of 1 ms, 2 ms, 5 ms, and 10 m.
s. In addition, the tact cycle is 1 ms. In other words, 1 time, 2 times, 5 times, 10 times of the tact cycle
There is a periodic task with a double cycle.

FIG. 2 is a diagram showing a control process for input data in the CPU module 2. That is, the configuration particularly related to the total frame system is shown. In FIG. 1, a CPU module 2 includes an input buffer 21 and an I / O as components for controlling data input.
It has an area 22, an input buffer transfer table 23, and an input data transfer table 24. The CPU module 2 includes a serial link control LSI 10, which has a reception buffer 11 as a component related to data input control.

The input buffer 21 is a buffer for taking in process data from the station required by the own module among the data flowing from the upstream station. I / O area 22
Is a memory area that can be directly accessed by each task 25 of the application program executed in the own station. An execution processor (not shown) for performing program processing in the CPU module 2 reads data required by itself from the I / O area 22,
Alternatively, the output data to the I / O module 3 is written to the I / O area 22.

When the serial link control LSI 10 receives a frame (total frame) transmitted from the serial link bus 1 by the total frame method,
This is taken into its own reception buffer 11 and sent to the downstream station module. Then, the CPU module 2 fetches necessary data from the reception buffer 11 to the input buffer 21 with reference to the input buffer transfer table 23. More specifically, of the data temporarily stored in the reception buffer 11, data required by the own station is transferred from the reception buffer 11 to the input buffer 21 in a tact cycle (the same cycle as the transfer cycle of the serial link bus 1). Will be transferred. Then, when the task 25 is activated, the input data transfer table 24 corresponding to the task is referred to transfer data required by the task from the input buffer 21 to the I / O area 22.

FIG. 3 is a diagram showing an example of the configuration of the I / O module 3, and particularly shows the configuration of the I / O module as the input device Di. Here, the role of the I / O module 3 includes a role as an input device Di for inputting data from a control device connected to the own station and passing the data to the CPU module 2, control instruction information from the CPU module 2, and the like. As an output device Do that transfers the control signal to a control device or the like to which the self device is connected. Here, the configuration / operation of the I / O module as the input device Di will be described with respect to the total frame method.

The input device (Di) 30 shown in FIG. 3 has a serial link control LSI 31, a buffer 32 and the like.
Further, a storage unit for storing “station number information” (of own station), “configuration information” and the like shown in FIG.

When the serial link control LSI 31 receives the frame of the total frame system (first frame) from the serial link bus 1, the serial link control LSI 31 only outputs data at its own station (data output to the CPU module) described later. Then, the data of the own station is added to the end of the received frame and output. This output data is generated in the output buffer 32 in advance based on input data from a control device connected to the input device (Di) 30. Also, the station number information and the configuration information (data size, status information, etc.) of the own station are added to this data.

The serial link control LSI 31 of the I / O module 3 is provided with a storage area for period information and phase information in a memory or the like (not shown) therein. NO. "(To be described later), and the period information and the phase information, to judge whether or not it is the output timing of the own station, and output the data only when it is. These pieces of information are set for each I / O module 3 by the CPU module 2 at the time of initial processing such as when the power is turned on or when a reset is started. The setting contents are automatically or manually created when a program is created by a program creation tool (loader) or when a system configuration is created.

In the "reception processing" of the present embodiment, attention is paid to the fact that it is not necessary for each I / O module to update data at least all at the same frequency. By setting the phase information,
Data can be output at an appropriate frequency required for each I / O module to avoid unnecessary data transfer. Then, with this, the I /
By reducing the output data amount of the O module, I /
Even if the number of O modules increases, it is not necessary to extend the time of the tact cycle. The appropriate data transfer frequency for each I / O module means, for example, that an I / O module that requires high speed performs data transfer in a short cycle, and an I / O module that does not require high speed.
The O module is set to transfer data in a long cycle.

For example, as shown in FIG. 4, one CPU module 2 (station number # 0) and 17
I / O modules (# 1 to # 17) (input device (D
i)), each I / O module (# 1 to # 1) is created when a program is created by the program creation tool (loader) or when a system configuration is created.
The control cycle of # 17) is 1 m for I / O # 1 to I / O # 2.
s, I / O # 3 to I / O # 5 for 1 ms, I / O # 6 to I / O
When O # 9 is set to 5 ms and I / O # 10 to I / O # 17 are set to 10 ms, the period information and phase information of each I / O module have the contents shown in the lower part of FIG. (In addition,
The phase information is programmed so that the output timing of the I / O module in the same control cycle is appropriately determined so as to be dispersed. That is, the “phase information” means that when there are a plurality of I / O modules having the same “control cycle”, the output timing is shifted so that data is not output and concentrated on a specific frame at the same timing. Information to do so).

FIG. 5 shows a case where “period information” and “phase information” are set for each I / O module as shown in FIG. 4 and added to the total frame transferred to the CPU module (# 0). FIG. 4 is a diagram showing data contents to be performed.

As shown in FIG. 5, a tact number is set at the head of the total frame. Tact N
O. is incremented by +1 each time the CPU module (# 0) (ring master station) sends a frame onto the serial link bus 1, for example. Of course, the present invention is not limited to this, and the tact number is updated in accordance with some predetermined rule. Also, when the tact No. is updated from 0 to 9, for example, it returns to 0 next.
The rotation may be performed in a certain cycle.

Each I / O module (# 1 to # 17)
Referring to the tact number of the received frame, it is determined whether or not it is the data output timing of its own station based on the “period information” and “phase information” set as shown in FIG. , The data of the own station is added to the end of the received frame and output.

The above determination method is performed, for example, by dividing the tact number of the received frame by "period information" and determining whether the remainder matches "phase information". For example, tact
When the frame No. is “3”, the I / O modules # 1 and # 2 determine that the “period information” is “1” and the “phase information” is “0”, Since the remainder '0' matches the “phase information”, the data of the own station is output. The I / O modules # 4, # 9, and # 13 also perform operations (3 ÷) based on the tact number and the “cycle information”, respectively.
2), the remainder of (3 ÷ 5), (3 ÷ 10) '1',
Since '3' and '3' coincide with the own “phase information”, the data of the own station is output. As a result, as shown in FIG. 5, the frame of tact NO. (= 3) has I / O
The output data of the modules # 1, # 2, # 4, # 9, and # 13 are added and transferred to the CPU module (# 0).

As described above, a large number of I / O modules (#
1 to # 17), the amount of data to be transferred on the serial link 1 can be reduced without adding all the output data of # 1 to # 17 to the frame as in the related art. The data transfer processing time can be shortened, so that the tact cycle can be shortened. In other words, in other words, even if the number of I / O modules increases, the rate of extension of the tact cycle can be reduced as compared with the conventional one (or there is no need to extend the tact cycle). It can be said that it becomes possible to greatly increase the number of I / O points that can be handled by the.

Such an effect is obtained by using “phase information”, when there are a plurality of I / O modules having the same output frequency (period information), for example, the period information as shown in FIG. '5' I / O module # 6,
It becomes more remarkable by dispersing the outputs of # 7, # 8, and # 9 into frames of tact Nos. 0 to 4 as shown in FIG.

Next, the data output processing of the CPU module 2 by the multicast method in the present embodiment will be described with reference to FIGS. In the above-mentioned prior application, the time of the tact cycle is 1 msec * N (the value of N varies according to the number of stations on the serial link bus 1), and the time of the tact cycle must be extended as the number of stations increases. However, in the present embodiment, the tact cycle can be set relatively short even when the number of stations increases.

This is the second embodiment. In the following description, for example, as shown in FIG. 6, the serial link bus 1 includes a CPU module 2 (station number # 0)
It is assumed that 17 I / O modules 3 (all output devices) from # 1 to # 37 are connected.

FIG. 7 is a diagram showing a control process regarding data output in the CPU module 2. That is, the configuration particularly related to the multicast system is shown. CPU
The module 2 includes an output buffer 26, an output data transfer table 27, and an output buffer transfer table 28 as components for performing data output control.
The transmission buffer 1 is provided in the serial link control LSI 10.
2

The output buffer 26 stores the data for which the task 25 performs output processing for each station that outputs data based on the reference result of the output data transfer table 27, with the station number of the output destination I / O module, the data size, and the mask information. This is a buffer that accumulates together.

The output data transfer table 27 exists for each task, and is referred to when the output data output by the task is transferred from the I / O area 22 to the output buffer 26.

The output buffer transfer table 28 exists for each tact number in a format corresponding to each tact number. That is, in the multicast method of the present embodiment, the tact number is set in the multicast token. Then, the CPU module 2 (serial link LSI 10) uses the table corresponding to the tact number in the output buffer transfer table 28 from the tact number in the received token for multicast, and To transfer necessary data to the transmission buffer 12.

This will be further described with reference to specific examples shown in FIGS. FIG. 8 is a diagram for explaining in detail the transfer of data from the output buffer 26 to the transmission buffer 12 according to the output buffer transfer table 28 of FIG.

As described above, a plurality of output data transfer tables 27 exist for each task, and are referred to when transferring data from the I / O area 22 to the output buffer 26. For example, as shown in FIG. 8, in the input data transfer table 27, for each piece of data for which each task performs output processing, “address 1” which is the storage position of the data in the I / O area 22, and “output 1” “Address 2” which is a storage position in the buffer 26 is stored in association with the “address 2”.

As shown in the figure, the output buffer 26 stores, for each station (I / O module 3) to which data is to be output, the data on which the task 25 performs output processing and the station number of that station (for example, ##). 21) and the data size and mask information.

The output buffer transfer table 28 is composed of tables corresponding to each tact No. as described above. For example, as shown in the figure, for the tact 0, for the tact 1, for the tact 2,. Table exists. In the table for each tact number, each station (I / O module) receives a multicast token having that tact number.
Is stored in the output buffer (output buffer 2).
6 (address 3) is stored.
In FIG. 9, the address is uniformly shown as "address 3", but actually, for example, as shown in FIG.

FIG. 9 is a diagram showing an example of the output buffer transfer table 28. In the drawing, for example, it is assumed that tact numbers are 0 to 9 and an example of a table corresponding to each tact number is shown. As described above, each table stores the address (in the output buffer 26) at which the output data to each station (I / O module) is stored. For example, in the table for tact 0, the I / O module O modules # 21, # 22, # 23, # 25, # 26, # 3
0 data is stored (in the output buffer 26)
Each address is stored. At the end of each table, an "end code" is stored.

For example, at the time of compiling, the contents of each of these tables are automatically generated by the program creation tool (loader) by referring to the definition information of the PC system (for example,
The example shown in FIG. 9 is generated in a form corresponding to the control cycle, cycle information, and phase information as shown in the lower part of FIG. 6). When the application program is downloaded to the CPU module 2, it is downloaded as a system definition at the same time, and is stored in the CPU module 2 in advance before the application program is executed.

Such an output buffer transfer table 28
Will be described below with reference to FIG. In FIG. 10, when a multicast token is received, the following processing is performed with reference to the table corresponding to the tact number (step S1).

That is, each time one data is read from the table, it is determined whether or not the data is the "end code" (step S2), and if so (step S2, YES), the processing is ended. I do. "Exit code"
If not (step S2, NO), the read data is the storage address (in the output buffer 26) of the output data for any of the stations. The transferred data is transferred to the transmission buffer 12. First, the "size" information at this address is referred to, and "data" at this address is transferred to the transmission buffer 12 by the size indicated by this information (step S).
3). When the transfer is completed, the pointer of the table is advanced (step S4), and the process returns to step S2.
Steps S2 to S4 until "end code" is reached
Is repeated.

For example, when the tact number of the received token is “0”, the processing of FIG. 10 is performed by using the table for tact 0 in FIG.
# 21, # 22, # 23, #
Multicast frames for the I / O modules 25, # 26, and # 30 are output.

As described above, the CPU module 2 outputs a multicast frame having only data for the predetermined I / O module 3 according to the tact number. Thus, the input processing in each I / O module 3 (output device DO) is simply performed by the I / O module 3 which is the output device.
Need only fetch data for the own station from the multicast frame received from the serial link bus 1 and output it to a control device or the like connected to the own station. That is, it may be substantially the same as the input processing of the above-mentioned prior application.

In the second embodiment described above, the "control cycle"
In the case where there are a plurality of I / O modules having the same value, the "phase" is shifted so that data is not concentrated on a specific frame. On the other hand, in a PC system,
For some reasons, a plurality of I / O modules having the same "control cycle" may need to synchronize and output data to a control device connected to the own station.

In such a case, the “phase information” must be the same by the method of the second embodiment only,
In this case, data is concentrated on a specific frame, and the effect of reducing the amount of data flowing on the serial bus 1 is reduced.

An example of a method corresponding to such a case will be described below with reference to FIGS. still,
This is the third embodiment. FIG. 12 is a diagram showing an example of the configuration of the I / O module 3 (output device DO) in the third embodiment.

In the figure, an output device (DO) 40 is
It has a serial link control LSI 41, a buffer 42 and the like. When receiving the multicast frame from the serial link bus 1, the serial link control LSI 41 takes the frame into its own reception buffer (not shown) and transmits it to the downstream station.

Here, the serial link control LSI 41
Is provided with a period information storage area and a phase information storage area in a memory or the like (not shown) inside thereof, and when the above frame is received, if the frame includes data addressed to the own station, the data is extracted. Further, it is determined whether or not it is the data output timing to the control device of the own station, based on the “tact No.” included in this frame and the period information and the phase information.

The determination method is, for example, “Tact No. set in the head of the received multicast frame.
Is divided by the value of the period information, and when the remainder matches the value of the phase information, it is determined that it is the data output timing to the control device of the own station.

If it is not the data output timing, the data extracted from the frame is temporarily stored. On the other hand, if it is the data output timing, the data extracted from the frame or the temporarily stored data is output to the control device of the own station.

These information are set by the CPU module 2 for each I / O module 3 at the time of initial processing such as when the power is turned on or when a reset is started.
The setting contents are automatically or manually created when a program is created by a program creation tool (loader) or when a system configuration is created.

FIGS. 13 and 14 are diagrams showing an example of the setting contents of the period information and the phase information of each of the I / O modules 3 (output device DO). In FIG. 13, as shown in FIG. 13, the phase information of all I / O modules 3 is set to “0”. This is because of the I / O of the same control cycle described above.
This is a setting for outputting the output of the module 3 at a synchronized timing.

For example, in the same figure, when the frame of "tact No." (= 3) in FIG. 11 is transferred on the bus, the I / O module # 24 receives data addressed to its own station. “Tact No.” (= 3) is used as the cycle information (=
Since the remainder '1' divided by 2) does not match the phase information (= 0), at this time, the data is temporarily stored without outputting data to the control device to which the own station is connected. Then, when the frame of “tact No. = 4” is transferred next, it is determined that it is the output timing, and the data is output. At this time, the I / O modules # 23 and # 25
However, it receives the data addressed to its own station, determines that it is the output timing, and outputs the received data to the control device. In this way, three I / O modules # 23, # 24, and # 25 having the same control cycle can output data at synchronized timing.

As described above, according to the third embodiment, the CP
Even if the phase is shifted on the U module 2 side (so that data is not concentrated on a specific frame), the I / O module 3 side sets the output timing of the received data to
Since the determination is made based on the “tact No.” and the cycle information and the phase information stored in the own station, the same control cycle I
The output of the / O module 3 can be performed at synchronized timing.

By setting the phase information as shown in FIG. 14, the output timing of the I / O module 3 having the same control cycle can be intentionally shifted. still,
In the setting contents shown in FIG. 11, when the frame as shown in FIG. 11 is received, the output timing is when the data addressed to the own station is received, but the present invention is not limited to this.

Next, a fourth embodiment will be described with reference to FIGS. In the fourth embodiment, for example, in a multi-CPU system as shown in FIG.
A method for synchronizing the operation of a task in a PU will be described.

Thereafter, the CPUs # 0 and C as shown in FIG.
Multi-C having three CPUs, PU # 1 and CPU # 2
A PU system will be described as an example. It is also assumed that a periodic task as shown in FIG. 16 is registered in each CPU. That is, the task # 0 (2
A fixed-cycle task called “ms cycle” and task 1 (5 ms cycle) is registered. Task # 2 (2 ms cycle) and task 3 (5 ms cycle) are registered in the CPU # 1. CP
Task 4 (5 ms cycle) is registered in U # 2.

In this embodiment, as shown in the figure, cycle information and phase information on each fixed-cycle task are set for each CPU module. Note that these cycle information and phase information are set in advance by the loader as control information of each task for each CPU, for example.

Thus, for example, when the total frame is received in the first embodiment, the start timing of each of the fixed-period tasks is controlled in accordance with the “tact NO.” Added to the total frame. That is, for each task of each CPU module, the “tact NO.”
Is divided by the value of the period information, and the task is started when the remainder matches the value of the phase information.

For example, when the periodic information and the phase information of each fixed-period task are set as shown in FIG. 16, the operation sequence of the task of the multi-CPU system is as shown in FIG.
As shown in FIG. For example, tact 2 (“tact NO.
When the total frame of “= 2” is received, the task 0 of the CPU 0 has the remainder of 2 ÷ 2 coincide with the phase information “0”, and the task 4 of the CPU 2 has the remainder of 2 ÷ 5 corresponding to the phase information “2”. ', These tasks 0 and 4 are activated.

As described above, the “tact” of the total frame
By using the NO. "And the cycle information and the phase information set for each fixed-cycle task in each CPU module 2, the start timing of each task is controlled by the above-described method, whereby a multi-CPU system can be controlled. It is possible to perform completely synchronized control between the tasks, and it is also possible to control the tasks between the CPUs in a pipelined manner.

In the description of each embodiment described above, “tact N
Although description has been made such that O. ", period information, phase information, and the like are handled as numerical data, the present invention is not limited to this. For example, a bit pattern as shown in FIG.

FIG. 18A shows an example of a bit pattern added to the total frame. This is the “tact
NO. ", Hereinafter referred to as" tact pattern data ".

FIG. 18B shows an example of a bit pattern set / stored in each I / O module.
This corresponds to the period information and the phase information, and is hereinafter referred to as “processing pattern data”.

In the figure, the tact pattern data and the processing pattern data are 16 bits, but the invention is not limited to this. A method for realizing “determining whether or not it is the data input / output timing of the own module” in each of the above-described embodiments using the configuration using the bit pattern will be described below.

That is, each I / O module extracts the tact pattern data added to the received total frame, and performs a logical product (AND) process on the tact pattern data and its own processing pattern data.
If the result is not '0' (0000000000000000), it is determined that it is the data input / output timing, and the predetermined processing is executed. For example, a logical product (AND) process is performed on “tact pattern data” corresponding to tact No. 0 in FIG. 6A and “processing pattern data” corresponding to I / O # 1 in FIG. If this is done, the result will not be '0' (in other words, the result of the AND processing will be the same as the “tact pattern data” of tact No. 0), so it is the data input / output timing described above. Is determined.

The "processing pattern data" shown in FIG.
Corresponds to the period information and phase information shown in FIG. For example, since the cycle information of I / O # 1 and # 2 is “1”, any “tact pattern data”
Is set so that the AND processing result does not become "0". (Note that the fact that these upper bits are not "1" corresponds only to tact numbers 0 to 9. These are, if necessary, 16 bit
Everything should be '1').

By using such a method, each I
There is no need to provide a circuit for the remainder calculation for each / O module, and the hardware can be realized with simple hardware.

[0087]

As described above in detail, according to the programmable controller and the input / output control method of the programmable controller of the present invention, an identification number updated according to a predetermined rule is added to a frame flowing on a system bus. The information for determining the data input or data output timing of the own module or the output destination module is set / stored for each module based on the identification number, so that the information can be appropriately set for each I / O module. Data update cycle can be set, unnecessary data transfer can be suppressed, the amount of data flowing on the bus can be reduced, and the tact cycle can be compared even if the number of I / O modules increases. It becomes possible to set the target short.

Further, the start timing of each task of the CPU module can be controlled based on the identification number added to the frame. In a multi-CPU system including a plurality of CPU modules, it is possible to completely synchronize the tasks. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an entire PC system to which an embodiment is applied.

FIG. 2 is a diagram showing a control process for input data in a CPU module.

FIG. 3 shows an I / O module (I / O module as an input device Di).
FIG. 3 is a diagram illustrating an example of a configuration of an O module).

FIG. 4 is a diagram showing an example of setting of cycle information and phase information according to a control cycle of each I / O module.

FIG. 5 is a diagram showing an example of data transferred by a total frame according to the setting contents shown in FIG. 4;

FIG. 6 is a system configuration diagram showing a configuration related to a multicast system in the PC system shown in FIG. 1;

FIG. 7 is a diagram illustrating a control process regarding data output in the CPU module.

8 is a diagram for explaining in detail transfer of data from an output buffer to a transmission buffer using the output buffer transfer table of FIG. 7;

FIG. 9 is a diagram illustrating an example of an output buffer transfer table.

FIG. 10 is a flowchart illustrating a data output process of a CPU module.

11 is a diagram illustrating an example of data transferred by a multicast frame according to the setting content illustrated in FIG. 9;

FIG. 12 is a diagram showing an example of the configuration of an I / O module (output device DO).

FIG. 13 is a diagram showing an example (No. 1) of setting contents of period information and phase information of each I / O module (output device DO).

FIG. 14 is a diagram showing an example (part 2) of setting contents of period information and phase information of each I / O module (output device DO).

FIG. 15 is a diagram illustrating an example of a configuration of a PC system that is a multi-CPU system.

FIG. 16 is a diagram illustrating an example of setting contents of period information and phase information regarding a fixed period task of each CPU in a multi-CPU system.

17 is a diagram showing an example of an operation sequence of a task according to the setting content of each fixed-cycle task shown in FIG.

FIG. 18 is a diagram for describing a modification in which a tact number, period information, phase information, and the like are configured as a bit pattern.

[Explanation of symbols]

 Reference Signs List 1 serial link 2 CPU module 3 I / O module 10 serial link LSI 11 reception buffer 12 transmission buffer 21 input buffer 22 I / O area 23 input buffer transfer table 24 input data transfer table 25 task 26 output buffer 27 output data transfer table 28 Output buffer transfer table 30 Input device (I / O module) 31 Serial link LSI 32 Buffer 40 Output device (I / O module) 41 Serial link LSI 42 Buffer

Claims (7)

[Claims] 1. A programmable controller comprising at least one CPU module and a plurality of I / O modules connected to a bus, wherein a frame used for data transfer on the bus is given a predetermined rule every tact cycle. The I / O module adds an updated identification number, and determines whether or not it is the data output timing to the CPU module according to the identification number of the frame to be received. A data output control means for adding data to the frame and transferring the data when the frame is determined. 2. The data output control means determines that the data output timing is reached when a predetermined condition is satisfied based on an identification number of the received frame and output timing data set / stored in advance. The programmable controller according to claim 1, wherein the determination is performed. 3. A programmable controller comprising at least one CPU module and a plurality of I / O modules connected to a bus, wherein a token circulating on the bus is updated at a predetermined rule every tact cycle. The CPU module adds the identification number,
When outputting data to the I / O module, the I / O module to be output data is determined according to the identification number added to the token, and the I / O module to be output to the data is determined for each tact cycle. A programmable controller comprising output processing means for performing data output processing. 4. The data output by the output processing means of the CPU module is transferred on the bus by a frame to which the identification number is added, and each of the I / O modules is addressed to its own module in a received frame. If the data exists, the data is fetched, and based on the identification number of the frame to be received and the output timing data set / stored in advance, the fetched data is extracted when a predetermined condition is satisfied. 4. The programmable controller according to claim 3, wherein the output is outputted to a control device of the own module. 5. A plurality of CPU modules and a plurality of I / Os.
In a programmable controller having a module connected to a bus, a frame used for data transfer on the bus is added with an identification number that is updated according to a predetermined rule for each tact cycle. Activating condition storing means for storing the activating condition of each task; determining whether the activating condition is satisfied based on the activating condition stored in the activating condition storing means and the identification number of the received frame; And a task activation control unit for activating a task that satisfies a condition. 6. The identification number is configured as bit pattern data, and each of the I / O modules or CPU modules converts the data set / stored for performing the determination or determination based on the identification number into bits. The programmable controller according to claim 1, wherein the programmable controller has the pattern data. 7. An input / output control method for each I / O module in a programmable controller having at least one or more CPU modules and I / O modules connected to a bus, wherein the identification is added to a received frame. An input / output control method, comprising: dividing a number by preset cycle information; and performing data output or data input of the own module when the remainder of the division matches preset phase information.