JP4293086B2 - Multiprocessor system and processor control method - Google Patents

Description

  The present invention relates to a multiprocessor system having a plurality of interrelated processors and a processor control method.

  In recent years, in order to speed up arithmetic processing and control processing in a computer, a computer equipped with a multiprocessor system that performs arithmetic processing and control processing using a plurality of processors has been used.

In a multiprocessor system having a plurality of interrelated processors, even if a certain processor stops operating, other processors continue to operate, and the interrelationship with the stopped processor is lost. Therefore, in order to maintain the relationship between the processors, it is necessary to synchronize the start / stop of each processor.
In the conventional multiprocessor system, in order to synchronize the start / stop between the processors, the stop request signal between the processors is connected, and the synchronization is realized by stopping the processors themselves.

  For example, Patent Document 1 discloses an interrupt to a computer environment configured by a plurality of processors connected to each other via a network and a host computer that controls these processors and controlling itself on the host computer. A technique related to a multiprocessor system that sends a message related to an interrupt in response to a request is disclosed.

  Patent Document 2 discloses a technique related to an access arbitration device for a shared memory that arbitrates access to the shared memory of each CPU in a multiprocessor system in which two CPUs exchange word data via the shared memory. ing.

Patent Document 3 discloses a technique related to a control device including a microprocessor that can change access timing to peripheral I / O such as a memory by inputting a wait signal from the outside.
Japanese Patent Laid-Open No. 1-118953 JP-A-5-324577 Japanese Patent No. 3204743

However, the conventional multiprocessor system has the following problems.
(A) In order to stop the processor itself, there is a problem that a dedicated circuit must be provided. In particular, when a multiprocessor system is configured by a plurality of processors having different operating frequencies and architectures, this dedicated circuit becomes complicated, and it is difficult to realize a multiprocessor system that synchronizes the start / stop of the plurality of processors. there were.

(B) Against this background, in the development of a multiprocessor system, a development tool such as ICE (In-Circuit Emulator) is used to control the operation of the processor and to start / stop the processor, internal state, and execution state. In order to improve the development efficiency.
However, because of the problem described in (a) above, in a multiprocessor system, a development environment in which an ICE is connected to a certain processor on a one-to-one basis, and the other processor is controlled while controlling the operation of the processor. It was not easy to build.

(C) In recent years, in a portable information processing apparatus (portable computer) such as a mobile phone or a PDA (Personal Digital Assistance), multiprocessors have been developed in order to improve data processing performance. In addition, due to the nature of a portable computer, it is necessary to mount a multiprocessor system that is small and saves power. At that time, it is necessary to select a processor in consideration of a structural problem (for example, a spatial problem) of the portable computer. Alternatively, each processor must be appropriately selected in accordance with the characteristics of data processed by the computer (for example, processing of voice call data or data processing such as e-mail / Internet in a mobile phone). That is, it is necessary to configure a multiprocessor system using processors having different operating frequencies and architectures and mount the system on a portable computer. And the combination pattern of a plurality of processors is very diverse.
In the development of a multiprocessor system in such a background, the problem described in (b) above is very remarkable, and the problem has been highlighted in the form of a decrease in development efficiency and an increase in production cost.

  The present invention has been made in view of the above circumstances, and when a certain processor performs a start / stop operation, controls a Wait function for extending an external access cycle held by the other processor from the other processor. It is an object of the present invention to provide a multiprocessor system that synchronizes the start / stop of a plurality of processors by extending the external access cycle of the processors to a memory, an external input / output device, or the like. Moreover, it aims at providing the control method of a processor.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a multiprocessor system including a plurality of interrelated processors, and is stopped from a first external device connected to the first processor. First stop means for stopping the operation of the first processor upon request, and a second external device connected to the second processor with respect to the second processor connected to the first processor The first output means for outputting the external access wait request signal to the first level at the first level, and the access cycle for the second external device is stopped by detecting the first level external access wait request signal And a second stop means, and in response to an operation start request from a first external device connected to the first processor First start means for starting operation of one processor, and external access Wait for a second external device connected to the second processor for the second processor connected to the first processor A second output means for outputting a request signal at a second level; and a second output means for starting an access cycle for the second external device by detecting the external access wait request signal at the second level. And starting means.

  The invention according to claim 2 is characterized in that the second stopping means is configured to identify whether the second external device is in an access cycle, and the first identification means. When the means identifies that the second processor is in an access cycle to the second external device, the means for extending the access cycle, and the first identification means, Means for deferring an access cycle to be executed next and shifting to a waiting state when the second processor identifies that the second external device is not yet accessed; and The second starting means includes a second identifying means for identifying whether or not an access cycle is postponed for the second external device, and the second identifying means. A processor is connected to the second external When it is identified that the access cycle has been postponed to the device, the second processor is configured to resume the access cycle and the second identification unit to wait for the access cycle. And means for canceling the standby state and starting an access cycle to the external device when it is identified.

  The invention according to claim 3 is characterized in that the external device is a memory storing instructions executed by a processor connected to the external device.

  The invention according to claim 4 is a method of controlling a processor in a multiprocessor system including a plurality of mutually related processors, wherein the stop request is sent from a first external device connected to the first processor. A first stop step for stopping the operation of the first processor, and external access to a second external device connected to the second processor for the second processor connected to the first processor A first output step for outputting a wait request signal at a first level; and a second step for stopping an access cycle for the second external device by detecting the external access wait request signal at the first level. And an operation start from a first external device connected to the first processor. A first start step for starting the operation of the first processor in response to a request, and a second external device connected to the second processor with respect to a second processor connected to the first processor A second output step of outputting an external access wait request signal for the second external device at a second level, and an access cycle for the second external device is started by detecting the external access wait request signal of the second level And a second starting step.

  According to a fifth aspect of the present invention, the second stop step includes a first identification step for identifying whether the second external device is in an access cycle, and the first identification. If the second processor identifies that the second external device is in an access cycle, the step of extending the access cycle and the first identifying step include: If the second processor identifies that it is before accessing the second external device, the method includes deferring the next access cycle to be executed and shifting to a standby state, The second start step includes a second identification step for identifying whether an access cycle is postponed for the second external device, and the second identification step. When the second processor identifies that the access cycle is postponed to the second external device, the step of restarting the access cycle and the second identification step include: When the two processors identify that they are waiting for an access cycle, the waiting state is released and an access cycle to an external device is started.

  The invention according to claim 6 is characterized in that the external device is a memory storing instructions executed by a processor connected to the external device.

According to the present invention, as will be apparent from the following description, in a multiprocessor system having a plurality of interrelated processors, by using a Wait function for extending an external access cycle held by the processor, the multiprocessor system It is possible to easily synchronize the start (resumption of operation) / stop between a plurality of processors having different operating frequencies and architectures.
This also makes it possible to easily build a development environment for a multiprocessor system composed of a plurality of processors having different operating frequencies and types, thereby improving the development efficiency of the multiprocessor system or the multiprocessor. System manufacturing costs can be reduced.

Next, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a diagram showing an outline of a multiprocessor system according to an embodiment of the present invention.
The multiprocessor system 10 includes a plurality of processors 1a and 1b. The multiprocessor system 10 may include the external device 2.
The processors 1a and 1b have a mutual relationship, and exchange data and messages with each other, thereby changing individual execution states. For example, the data processed by the processor 1a is passed to the processor 1b, and the processor 1b performs another processing, or transfers a message from the processor 1b to the processor 1a, and the processor 1a executes an instruction based on the message. , And so on, there is a relationship (mutual relationship) in which the state changes by mutual exchange.

The processors 1a and 1b need not be limited to the same processor.
For example, the processors 1a and 1b can perform the same calculation and control, but their operation clocks may be different. Alternatively, the processors 1a and 1b may be processors that can perform different operations and controls, that is, processors having different architectures.

In such a multiprocessor system having an interrelationship, when a certain processor is started / stopped by an external request, the start / stop of the processor is synchronized with the start / stop of the other processor.
That is, as shown in the flowchart of FIG. 2, the processor 1a stops its operation in response to a stop request 20 from the external device 2a (step S1), and simultaneously outputs an external access wait request signal 21 to the processor 1b. (Step S2).
The processor 1b receives the external access wait request signal 21 (step S3), and checks the state of access to the external device 2b (step S4). If the access cycle is in progress (step S4 / Yes), the cycle is extended (step S5). If it is before the access (step S4 / No), the next access to be executed is postponed and a standby state is entered.

As shown in the flowchart of FIG. 3, in starting the re-operation of the multiprocessor system, the processor 1a resumes its operation by receiving the re-operation start request 22 from the external device 2a (step S11). The output of the external access wait request signal 21 to the processor 1b is stopped (step S12).
The processor 1b checks the access state to the external device 2b by detecting the stop of the external access wait request signal 21 (step S13) (step S14). If the access cycle has been extended (step S14 / Yes), access to the external device 2b is executed (step S15). When it is in the standby state (step S14 / No), the standby state is canceled and access to the external device 2b to be executed next is started (step S16).

  The embodiment described above is an example of a preferred embodiment of the present invention. However, the embodiments of the present invention are not limited to these, and various modifications can be made without departing from the gist of the present invention. An example is shown below.

FIG. 4 is a diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.
The multiprocessor system 10 includes processors 1a and 1b. The processor 1a is bus-connected to a memory 3a that stores instructions executed by the processor. Similarly to the processor 1a, the processor 1b is also bus-connected to a memory 3b that stores instructions executed by the processor. The processors 1a and 1b are connected by a bus so that data and messages can be transferred to each other, and further, a path for the processor 1b to transmit an external access wait request signal for extending the access cycle with the memory 3b is connected. Has been.

The processors 1a and 1b need not be limited to the same processor.
For example, the processors 1a and 1b can perform the same calculation and control, but their operation clocks may be different. Alternatively, the processors 1a and 1b may be processors that can perform different operations and controls, that is, processors having different architectures.

An ICE (In-Circuit Emulator) 4 is connected to the processor 1a from the outside of the multiprocessor system 10.
In the development of a multiprocessor system, a development tool such as ICE is used to control the operation of the processor and check the start / stop of the processor, the internal state, the execution state, and the like to improve the development efficiency.

The operation of the multiprocessor system will be described with reference to the timing charts of FIGS. FIG. 5 is a timing chart in the case where the access cycle of the processor 1b is extended when the operation of the processor 1a is stopped, and FIG. 6 is a timing chart in the case of waiting for the access cycle of the processor 1b.
When the operation of the multiprocessor system 10 is started, the processor 1a sequentially executes the instructions stored in the memory 3a (the “operation” state on the left side of the processor 1a).
Similarly, the processor 1b sequentially executes instructions stored in the memory 3b. Here, the “access cycle” is a period during which the processor accesses the external device (memory or the like) in order to operate the external device. In general, the processor operates faster than the external device. Thus, there is a processor latency between the two access cycles.
The processor 1a performs the same operation as the processor 1b, but is omitted from FIGS.

The ICE 4 can request the processor 1a to start (resume operation) / stop the processor 1a at an arbitrary timing.
When the ICE 4 makes a stop request to the processor 1a, the processor 1a receives the stop request and stops its own operation. At the same time, the processor 1a sets the external access wait request signal 21 to the high level for the processor 1b.
The processor 1b recognizes (detects) the High level, and extends the access cycle when the memory 3b is being accessed. That is, the access cycle is temporarily stopped (see FIG. 5).
If the memory 3b is not being accessed, the next access execution (access cycle) is postponed (see FIG. 6).

When the ICE 4 makes an operation resumption request to the processor 1a, the processor 1a resumes the operation and simultaneously returns the external access wait request signal 21 to the low level. The processor 1b recognizes the low level and executes the access cycle to the extended memory 3b (see FIG. 5) or executes the next access that has been postponed (see FIG. 6).
By this operation, the start (resumption of operation) / stop of the processors 1a and 1b can be synchronized.

  The number of processors in the multiprocessor system according to the present invention is not limited to two processors shown in the present invention, and may be three or more processors.

In addition, when a multiprocessor system is installed in a portable computer such as a mobile phone or a PDA (Personal Digital Assistance), structural problems (for example, spatial problems) and characteristics of data processed by the computer In particular, the multiprocessor system according to the present invention is carried from the viewpoint that an optimum processor must be selected in accordance with (for example, voice data processing in a mobile phone, data processing such as mail / Internet). It is effective to apply to the type computer.
However, the application of the present invention is not limited to this, and the same effect can be obtained when applied to a more general computer (PC, workstation, server, etc.).

In addition, the multiprocessor system according to the present invention does not need to have the same architecture of each processor. Therefore, the multiprocessor system is not limited to a mode in which a plurality of processors are mounted on one base, but each mounted on a different base. A multiprocessor system in which these processors have a mutual relationship may be used.
For example, a processor (for example, a CISC processor) mounted on a certain computer base (for example, a motherboard) and a processor mounted on another base (for example, a PCI board) mounted on the base by a bus connection. (For example, a RISC processor) may be a multiprocessor system having a mutual relationship.

It is the figure which showed the outline | summary of the multiprocessor system which is embodiment of this invention. It is the figure which showed the flow of the process of operation stop in a multiprocessor system. It is the figure which showed the flow of the process of a re-operation start in a multiprocessor system. It is the figure which showed the structure of the multiprocessor system which is one Example of this invention. 6 is a timing chart showing the operation of the multiprocessor system (in the case of extended access cycle). 6 is a timing chart showing the operation of the multiprocessor system (in the case of an access cycle wait).

Explanation of symbols

1 Processor 2 External Device 3 Memory 4 ICE (In-Circuit Emulator)
10 Multiprocessor System 20 Stop Request Signal 21 External Access Wait Request Signal 22 Reoperation Start Request Signal (Start Request Signal)

Claims (6)

A multiprocessor system comprising a plurality of interrelated processors,
First stop means for stopping the operation of the first processor in response to a stop request from a first external device connected to the first processor;
First output means for outputting, to a second processor connected to the first processor, an external access wait request signal for the second external device connected to the second processor at a first level. When,
Second stop means for stopping an access cycle for the second external device by detecting the first level external access wait request signal;
A first starter configured to start the operation of the first processor in response to an operation start request from a first external device connected to the first processor;
Second output means for outputting, to the second processor connected to the first processor, an external access wait request signal for the second external device connected to the second processor at a second level. When,
And a second start means for starting an access cycle for the second external device by detecting the second level external access wait request signal. The second stopping means is first identifying means for identifying whether the second external device is in an access cycle; and
Means for extending the access cycle if the first identification means identifies that the second processor is in an access cycle for the second external device;
When the first identifying unit identifies that the second processor is not accessing the second external device, the access cycle to be executed next is postponed and the standby state is entered. Means,
Furthermore, the second starting means includes second identifying means for identifying whether or not an access cycle is postponed for the second external device;
Means for resuming the access cycle if the second identification means identifies that the second processor has postponed the access cycle to the second external device;
A means for releasing the waiting state and starting an access cycle to an external device when the second identifying means identifies that the second processor is in a waiting state for an access cycle; The multiprocessor system according to claim 1, further comprising:   The multiprocessor system according to claim 1, wherein the external device is a memory that stores instructions executed by a processor connected to the external device. A method for controlling a processor in a multiprocessor system including a plurality of interrelated processors,
A first stop step of stopping the operation of the first processor in response to a stop request from a first external device connected to the first processor;
A first output step of outputting, to a second processor connected to the first processor, an external access wait request signal for the second external device connected to the second processor at a first level. When,
A second stop step of stopping an access cycle for the second external device by detecting the first level external access wait request signal;
A first start step of starting the operation of the first processor in response to an operation start request from a first external device connected to the first processor;
A second output step of outputting, to a second processor connected to the first processor, an external access wait request signal for a second external device connected to the second processor at a second level; When,
And a second start step of starting an access cycle for the second external device by detecting the second level external access wait request signal. The second stop step includes a first identification step for identifying whether or not an access cycle is being performed for the second external device;
If the first identifying step identifies that the second processor is in an access cycle for the second external device, extending the access cycle;
In the first identification step, when the second processor identifies that the second external device is not yet accessed, the next access cycle to be executed is postponed and the standby state is entered. And having steps,
Further, the second starting step includes a second identifying step for identifying whether or not an access cycle is postponed for the second external device;
Resuming the access cycle if the second identification step identifies that the second processor is deferring an access cycle for the second external device;
When the second identifying step identifies that the second processor is in an access cycle waiting state, the step of releasing the waiting state and starting an access cycle to an external device includes: 5. The processor control method according to claim 4, further comprising:   The processor control method according to claim 4, wherein the external device is a memory that stores an instruction to be executed by a processor connected to the external device.

Images