JPS5941944A - Processing device of power failure of data transmission system - Google Patents

Abstract

PURPOSE:To prevent completely the phase shift between a main system and an interface, by storing the interface management state of the main system at a power failure time while power supply is cut off and referring to management information at the power failure time to restart the transfer control when power supply is recovered. CONSTITUTION:When power supply is recovered, flags stored in an area H are referred to perform the data transfer control. The set state of a flag WED is referred to in the transmitting operation, and the set state of a flag RED is referred to in the receiving operation. When the flag WED is set, it indicates that the power failure occurs at the completion time of data transfer of one block, and it is sufficient if data of the next new block is transferred; but when the flag WED is reset at the power supply recovery time, data of said one block is transferred again from the beginning.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power outage processing device for a data transmission system in which data transmission control is performed by an interface connected between a main system and a data transmission line.

In a data transmission system such as a local network system, each terminal can transmit data to other terminals according to certain transmission rules.

In a 1m local network system, data transmission control is performed by the following procedure.

First, each terminal connected to the transmission line reads the destination terminal address written at the beginning of the data packet, and if it matches its own address, it reads the following data. CR
As a result of the C check, if there is no error, an ACK packet is sent to the transmitting terminal. If there is an error, the received data is discarded. The transmitting terminal measures the time after transmission using a timer, and retransmits if there is no ACK within a certain period of time. In addition, when performing even stricter transmission control, a RACK packet is transmitted to the transmitting terminal when an ACK packet is received.

Conventionally, in the data transmission control described above, this control was executed by an application program prepared for each terminal, and the controller 1-roller that connects the main system of the terminal and the transmission line simply assembled packets and transferred data. All that was required was level conversion (conversion between voltage level and logic level). However, as the load on the main system increases as more application programs are required, the efficiency of task processing decreases.
Because data retransmission and bucket generation are performed by hierarchically upper application programs, error recovery processing and collision prevention cannot be performed efficiently and quickly.
It was not possible to obtain sufficient reliability and high speed.

Therefore, the present applicant has proposed that these data transmission controls be performed on the controller side, that is, on the interface connected between the main system and the data transmission line, 2. We proposed a data transmission control device in which the main system only processes the transmitted and received data and manages the interface.

However, if the main system and the interface perform the above operations independently, there is a possibility that the phases of the two systems will not match when a power outage occurs, resulting in loss of transferred data.

The purpose of this invention is to handle a power outage in a transmission system that controls data transfer so that there is no phase shift between the interface and the main system after a power outage occurs and then when the power is restored. The goal is to provide equipment.

This invention can be summarized as follows.

Management information storage means for storing the interface management status in the main system is provided on the interface side. This storage means is composed of a flag that indicates when one block of data transfer is completed, which is an example of management information, and is set by the main system. At least this storage means functions during a power outage and stores management information at the time of a power outage. As in the embodiment described later, management information may be updated and stored even when attending a seat. The interface side is further provided with a battery backup storage means for saving and storing the above management information when a power outage notification is received from the main system J1 side. In other words, management information during a power outage is
The management information is stored in the backup memory so that the management information can be referenced in data transfer control when the power is restored.

On the other hand, on the main system side, there is a power outage processing determining means for determining whether the power outage processing of the interface is completed after the power outage processing in the main system is completed, and a means for resetting the main system and the interface when the power outage processing is determined by this determining means. and. That is, when both the main system and the interface complete power outage processing, they are reset and transitioned to the power-off state.

According to this invention, both the main system and the interface are sent after the power outage processing is completed, and the interface management state in the main system at the time of the power outage is stored during the power outage, so when the power is restored, the Data transfer control can be restarted while referring to the management information, and the phase shift between the main system and the interface can be completely eliminated.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a low-power rune software work system that implements the present invention. In the figure, terminal devices A-N, which are the main system, are connected to a data transmission line L consisting of a coaxial cable via a transmission interface I/F, so that various data can be freely sent and received between each terminal. It has become. FIG. 2 is a block diagram of the transmission/interface I/F, and FIG. 3 is a more detailed block diagram thereof.

The transmission interface I/F includes a transmission control circuit 10, a reception control circuit 11, and a transmission/reception data transfer control circuit l2.
It consists of The transmission control circuit 10 sends the transmission data or response packet I on the transmission line in a predetermined packet format, and the reception control circuit I1 sends out the transmission data or response packet I on the transmission line I.
, determine the packet format of the received data,
A response bucket is created based on the determination result. In addition, the transmission/reception data transfer control circuit l2 is a reception control circuit l■
, controls the transfer of transmitted and received data between the transmission control circuit IO and the terminal device.

In FIG. 3, the transmission/reception data transfer control circuit 12 is comprised of a transmission data transfer control circuit 1 and a reception data transfer control circuit 2. The transmission data transfer control circuit I has a register a that temporarily stores byte by byte of data sent from the terminal device when transmitting various data, and a seso register that stores data sent byte by byte when transmitting various data. It has a cheat flag WEN, a flag WED that is set when the terminal device has transferred all the transmission data, and a power outage flag PDF that is set by the terminal device when a power outage occurs. The reception data transfer control circuit 2 also includes an acquisition register b for transferring the reception data on the interface side to the terminal device byte byte when receiving various data, and a reception register b for transferring the reception data on the interface side to the terminal device for each byte, and a reception register b for transmitting the reception data on the interface side to the terminal device for each channel. a flag REN to notify the user that the terminal device has received all received data, a flag RED to notify the interface side for each channel that the terminal device has taken in all received data, and a flag RED to notify the interface side that the terminal device is ready for reception. The transmission control circuit 10 has a flag RDY of
, and the reception control circuit 11 includes a reception buffer G for storing reception data for each channel, and buffers A and B for storing transmission data. Random number table TBL. for selecting a backoff timer value, which will be described later. Area H for saving and storing flags of the transmitting/receiving data transfer control circuit in the event of a power outage, memory 4 for storing the interface control program and being fully serviced by battery E, and control circuit 6 for controlling the timer and interrupt functions at the transmitting/receiving stage. , a DMAC 3 for DMA transfer of data between the memory 4 and the transmission/reception data transfer control circuit 1.2, and a DMAC 3 for controlling transmission/reception operations;
A link controller 7 having transmitting/receiving buffers C and F and transmitting/receiving shift registers D and E, and a collision controller that modulates the transmitted data and sends it onto the line during transmission, and detects whether there are access requests from multiple terminals at the same time. A line control circuit 8 including a detection circuit, a line control circuit 9 that receives a signal on the line, demodulates the signal, and transfers it to the link controller 7, and the entire interface are controlled according to a control program stored in the memory 4. It is composed of a sub CPU5.

FIG. 4 is a circuit diagram of a collision detection circuit provided in the line control circuit 8. As shown in the figure, the modulated signal and the pre-demodulation signal are applied to an exclusive OR circuit 8l, whose output is used as a set signal for the flip-flop 82. By doing so, the collision detection signal CO can be obtained when the transmitted data and the received data are different, that is, at the time of a collision.

FIG. 5 is a circuit diagram of a signal detection circuit provided in the line control circuit 9. Moreover, FIG. 6 is a timing chart of the same carrier detection circuit.

In this embodiment, a carrier signal CDI indicating that there is a flow of data on the line and a rear signal CDI that is held for a certain period of time are used.
A signal CD2 indicating that there is no signal is set to 111. That is, the demodulation circuit 9o creates a receive clock a from the signal received from the line, inputs it to the pinary counter 91 and the launch circuit 92, and generates the signal CI)l.
And I got CD2. As shown in FIG. 6, when the receive clock disappears, the CL (clear) terminal of the pinary counter 9l is released, the count advances according to the basic clock φ, and the carrier signal CDI, which is a mirror image signal of the carrier wave, is obtained. As the count progresses further, a signal CD2 is obtained which is obtained by adding a preset processing time t to the period of the clock φ.

Each terminal individually detects the signal CDI and the signal CD2, and uses a circuit not shown to transmit the data bucket only when the signal CD2 is 1 low (logical 0).
A CK packet or a RACK packet has a signal CDI of “
It is controlled so that it can be transmitted only when the signal is "low" (logical 0). By controlling the transmission and reception while checking the signals CDI and CD2 in this manner, collision with data packets from other terminals is prevented regarding ACK and RACK packet transmission after data packet transmission. FIG. 7 shows the signals on the line and the above signal CDI. , CD2. In the figure, time t represents a certain period of time when there is no carrier signal on the line. This time is set to be longer than at least the allowable retransmission time of response packets for ACK and RACK packets, and if a response packet is not sent within this time t, the line is no longer occupied.
New access from other devices is allowed.

FIG. 8 shows the basic transmission procedure in this local network. FIG. 3A shows the procedure when both the transmitting terminal and the receiving terminal are in a normal state. First, a data packet including a header section such as a flag and an address is transmitted from a transmitting terminal to a destination. When this data packet is received normally, the data packet receiving terminal transmits an ACK packet. The data packet transmitting terminal that has received the ACK packet sends a response packet (RA) to the ACK packet.
CK packet). If the receiving terminal is not ready to accept the data packet for data packet transmission, the receiving terminal transmits the NRDY packet and ends the process, as shown in FIG. If the receiving buffer corresponding to the channel of the transmitted data packet is full, an NRDY packet with a buffer full statement is sent as shown in FIG.

FIG. 9 is a diagram showing the packet format.

This packet consists of a format that separates data into a flag (leading flag) and a flag (trailing flag). Both flag codes are 7E (hexadecimal). Destination address DA specifies the receiving station. Source address SA specifies the transmitting station. Data type TYPE specifies the type of transfer frame. The types are data, ACK, RACK, NRAD
There are four types of Y. Channel number CIl. NO specifies the channel type of the packet. Line status DLS describes the statement at the time of NRADY packet transmission. The statements include receive not possible and receive buffer full. Byte counters BCL and BCH specify the number of bytes of data. The data field DATA sets the data to be transferred. This data field DA
TA is present only in data packets. CRC provides a code for error detection.

Next, the operation of the interface shown in FIG. 3 will be explained with reference to FIGS. 10 to 12. FIGS. 10 to 11 show the transmitting operation and receiving operation, and FIG. 12 shows the power outage processing operation.

(1) Transmission operation FIGS. 10(A) to 10(C) are flowcharts showing the data transmission operation.

Now, assume that specific data is to be transmitted from terminal storage A to terminal device N.

First, in step nl (hereinafter step ni will be simply referred to as ni), the terminal device A writes 1 byte of data to the write register a of the transmission data transfer control circuit 1, and also sets the flag WEN. At this time, terminal device A
From there, the transmission data length (number of bytes) and channel information CHn specifying which channel to handle the data are sent together with the above data and set in a predetermined area.The transfer control circuit l that received these data is , selects the DRQ3 channel (channel used for data transfer within the interface), which is the DMA transfer channel for the transmission data, and instructs DMAC3 to perform DMA transfer (n2)
. Upon receiving the instruction, the DMAC 3 sets a transfer destination address in the memory 4 (n3), and transfers the data in register a to the transmission buffer 8 located at that address (n4). ■
When the byte transfer is completed, the flag WEN is reset (n5). The terminal WA monitors the flag WEN, and when it learns that it will be reset (n21), it returns to n20 and sends the next 1 byte of data to register a. In this way, the terminal device 8 monitors the flag WEN, and each time the flag is reset, 1 byte of data is stored in the register a.
while on the interface side, I) MAC
1) MA transfer the data of the register disk A to the transmission bath sofa A in sequence. When all data transfer is finished,
Terminal device A goes to set flag WED <(n22)
. When this flag WED is sent, the control circuit 1
At n7 and n8, the check for the fixed number of bytes for 1 and the check for the transmission command are performed, and if correct, proceed to n9. D.M.A.
C3 executes MA transfer of data from buffer A to buffer B at n9, nlO. When the transfer is completed, the flag W is set to indicate that the sending bath sofa is free.
Reset ED (nil). When the terminal device A learns that the flag WED is in the reset state, if there is data to be transmitted next, the terminal device A transfers the transmission data to the buffer 8 in the same manner as described above.

As described above, the flag WED constitutes a storage means representing the interface management state in the terminal device. That is,
If the flag WED is in the reset state after data transfer from the terminal device, it indicates an instruction to continue transferring the current block data,
If set, it indicates that block data transfer has been completed.

On the other hand, when the transmission data is prepared on the transmission bath sofa B as described above, the CP that controls the movement of the interface
U5 issues a transmission instruction (n30) and sets the link controller 7 to a transmission ready state (n31). At this time, the link controller 7 checks the signal CD2 obtained by the carrier detection circuit CD, and if it is "low", immediately sends the leading flag F, which is the first data of the packet, onto the line via the line control circuit 8. (n32).

Next, the CPU 5 sets the start address of buffer B of the memory 4 and the number of data bytes in the DMAC 3 (n33.n
34), instructs data transfer from bath sofa B to link controller 7; During this time, the link controller 7 continues to send out the above-mentioned leading flag F, but n
After completing 34, the sending of the same flag F is stopped (n35)
.

Next, when the transmission buffer C of the link controller 7, which is the data transfer destination, is empty (n36), and the link controller I/roller 7 sends a data transfer enable signal to the DMAC 3 to the Bazza C ( n37), 1 in n3B
Bytes of data are transferred from buffer B to buffer C. The link controller 7 further transfers the transfer data to the bath sofa C to the shift register D, transfers 1 byte to the shift register D (n40), returns to n37 again, executes the DMA transfer, and transfers the data of the shift register D. The data is sent to the line control circuit 8 and sent out to the line after modulation (n41"n44).

As will be described later, if the above operations are performed simultaneously on two or more terminals, a collision will occur at least when the source address of the data is sent, but this collision will be detected by the collision detection circuit CO. If so, the process advances from n44 to n60 to prohibit transmission. Now, assuming there are no collisions,
The link controller 1/roller 7 sequentially transfers the data from the bath sofa C to the shift register disk D, and transfers the data from the bath sofa C to the shift register disk D as described above.
The data transferred by DMA to the line control circuit 8 is sequentially sent to the line control circuit 8. Repeat this operation (n37 to n'45),
When the transmission of the specified data length is completed, the DMAC 3 counts up the built-in piete counter, thereby notifying the link controller 7 that the frame transmission has been completed (
n46). Upon receiving this, the link controller 7
Attach C and complete data transmission of ■ frame. And the link controller 7 is C. The CPU 5 sends an interrupt signal indicating that the frame data transmission has been completed (n47), and the CPU 5 sends a trailing flag F to the line control circuit 8 via the link controller 1 and the roller 7.
(n4B). 1-Railing flag F
For example, the CPU 5 performs a transmission completion process (n49) and continues sending the flag until it performs a reception preparation process (n50), and when these processes are completed, flag sending is stopped and (
n51), set the interface to receive mode (
n52).

Next, in n44, the operation when the data bucket 1 collides will be explained.

Data bucket collisions occur when two or more terminals attempt to transmit at the same time in a common channel scheme where each terminal has equal access. Although the signal CD2 prevents collisions when the access timings are completely different, since there is a large propagation delay between mutually distant terminals, it takes time to detect the transmission of another terminal. As a result, collisions are more likely to occur. Generally, in a local network system that uses a common channel method, in order to solve the above problem, data is retransmitted after waiting a certain period of time after a collision is detected. This processing is called backoff processing. The steps below n60 are the steps for performing this bank-off process.

Collision is i! When detected by the i-detection circuit CO, all terminals that sent data packets stop sending (n60
). The line is then pulled high (n) so that other terminals can easily detect that a collision has occurred.
61'). Next, the falling edge of the signal CD2 is detected (n
62) At the falling timing, a predetermined passoff timer value is read from the random number table TBL provided in the memory 4 (n63), and the value is set in the timer 1' of the control circuit 6 (n64). Subsequently, when the predetermined time set in this way has elapsed (n65), the CPU 5 detects the state of the signal CD2 again, and the level becomes "low".
If the access is possible, the process returns to n30 and the above-described transmission operation is repeated. The level of signal CD2 is “
If the state is "high" and line use is not permitted, proceed to n67 and start the back-off timer again at the timing when the signal CD2 falls (n64), and when the timer elapses, the signal CD2 becomes off. wait.

FIG. 13 shows the operation when terminals A, B, and C attempt to access almost simultaneously (with some errors due to propagation delays, etc.) and a collision occurs. When each terminal A, B, and C detects a collision as shown in the figure, they immediately stop transmitting, and at the falling timing of signal CD2, each terminal sets the bass off timer values t1, t generated using a random number table.
2. Start t3. When time (l has elapsed, A
The terminal detects the state of signal CD2. At this time, terminal B and terminal C cannot transmit because the timer values t2 and t3 have not elapsed. Therefore, as long as there is no access from other terminals, signal CD2 is in the OFF state, allowing retransmission from terminal A. In this example, A
A case is shown in which a data packet is transmitted from a terminal to terminal B. Regarding the other terminals B and C, which could not transmit due to a collision, the transmission of terminal A was successful. A retransmission will be attempted later. This method is carried out in the same manner as t above. That is, timer values t2 and t3 are started at the falling timing of signal CD2, and terminal B starts at time L2.
The state of the signal CD2 is checked at the time when the time has elapsed, and if it is off, retransmission is performed. Furthermore, the C terminal checks the signal CD2 when the time t3 has elapsed, and if it is off, retransmits it.

In this way, the order of transmissions from colliding terminals is sorted out while performing bank-off processing.

As described above, in this embodiment, the starting point of the back-off timer is set at the falling timing of the signal CD2,
It is designed to start at the same timing regardless of the type of terminal. Therefore, there is an advantage that the probability of collision occurring again can be reduced and the accuracy of the back-off timer can be improved. The backoff timer value set at n64 is set to the same value the next time a cent is sent at n64 unless a new collision occurs.

FIG. 14 shows the structure of the data packet sent out on the line by the above operation.

As shown in the figure, m leading flags F are located at the beginning of the packet, and a trailing flag F of jllm is located at the end of the packet. As described above, m flags are sent out at times n32 to n35, and j flags are sent out at times n48 to n51. In this way, by consecutively sending flags at the beginning and end of a packet, the transmitting terminal can prepare for reception at the time when the last flag is continuously sent, and the receiving terminal can receive the consecutive leading flags. In between, you can change the mode to normal reception mode.

The receiving terminal is set to normal receiving mode in the following cases. For example, if a receiving terminal receives signals from two or more transmitting terminals at the same time, a collision is detected when the source address is received. At this time, the receiving terminal has already received the reading flag and is in a data waiting state because the receiving terminal is not set to receive mode. However, the two transmitting terminals that caused the collision have stopped transmitting and are waiting for the next chance. Therefore, when a new data packet is transmitted from either terminal or another terminal, the receiving terminal in the data waiting state regards the first leading flag as the trailing flag (leading flag and trailing flag are both " 7
When the leading flag is received, it is detected that the format of the packet is incorrect (the format length is short), and error handling is performed.

Therefore, in such a case, if there is only one leading flag, there is a possibility that the received data after error processing will be treated as having no leading flag and error processing will be performed.

On the other hand, if an appropriate number of leading flags are set consecutively in the data packet, the receiving terminal will process the error when receiving the first leading flag and perform normal reception. When the mode is entered, it is possible to process the leading flag that is still in use as a flag for the next Pakesoto.

That is, by attaching mill leading flags and j trailing flags, it is possible to put the transmitting terminal and the receiving terminal in a state in which they can normally receive Pakesoto.

(2) Reception operation FIGS. 11(A) to 11(C) are flowcharts showing the data reception operation.

The data packet sent out on the line as described above is received by the line control circuit 9 on the terminal device N side (n7
0), and is demodulated (n71) and guided to the shift register E of the link controller 1/roller (n'72). The link controller 7 determines whether the first byte of the received data is a flag or something other than a flag, and if it is a flag, guides the next byte of data to the shift register E. If it is other than the flag, the destination address DA is read and it is determined whether the address is the self address (n75), and if it matches the self address, the process advances to n76. At n76, the received data in the registers 1 to E are transferred to the receiving bath sofa F, and an instruction is given to the DMAC 3 that there is received data (n77). At the same time, [)RQI is selected as the channel for transferring data to the bath sofa G. The DMAC 3 receives the instruction that there is received data, and transfers the received data from the reception buffer F to the buffer G of the memory 4.
Transfer sequentially to The bath sofa G is provided with the same number of channels, and the received data is transferred to the portion corresponding to the channel number specified by the Paqueso 1-.

This transfer is performed byte by byte of data led to register E, and it is determined that reception is complete when a flag (trailing flag) indicating a data break is detected (n
79), the link controller 7 instructs the CPU 5 to complete the reception (n80). CPU5 that received this instruction
prohibits the reception mode and determines the type of data sent. If it is data information, it is determined by the flag RDY in the received data transfer control circuit 2 whether the terminal device is in a ready state at the time of reception and can receive it (n89). This flag RDY is controlled by the terminal device, and is set to 1 when the terminal device is in a receiving state. If reception is possible, then it is determined whether the reception bath sofa G (in the memory 4) of the designated channel (designated by CH.No. in FIG. 9) is free (n90). As mentioned above, this reception buffer G has a number of channels prepared, and whether or not each channel is free is indicated by the flag REN in the reception data transfer control circuit 2. When the reception buffer for a channel is empty, the flag REN corresponding to that channel is set.On the other hand, when the buffer is full, the flag REN corresponding to that channel is reset.n9
If the reception bath for the channel specified by 0 is in an empty state, an ACK message is sent to the terminal that sent the data message (n91). Although not shown in FIG. 11, this ACK bucket assembly is performed by the CPU 5. As is clear from FIG. 9, the assembly of the ACK packet is extremely simple, and the destination address DA
Other data except for will be a fixed code. There is no need to create the destination address itself, and the source address SA of the sent data packet can be used as is. After transmitting the ACK packet, the CPU 5 sets the data presence flag REN (of the designated channel) in the reception data transfer control circuit 2 (n92), and enters the re-reception mode.

In n89, if terminal device N cannot receive data,
Send NRDY page 7 with n93 and return to ゜ζ re-reception mode. Also, if the reception breadth is full on n90,
In other words, if the flag REN corresponding to the specified channel is set, the buffer is full (NRDY) with n94.
Send the packet and return to re-receive mode.

On the other hand, since terminal device A receives the ACK packet transmitted in 1191 above at terminal device N, n
Proceed to 82-"n83-"n95. Normally, after data packet transmission, the state transitions to an ACK packet waiting state, so the process proceeds from n95 to n96, and a RACK packet is transmitted to the ACK packet transmitting terminal, that is, the terminal device N (n
96), set the transmission/reception control section to reception mode (n97)
).

Note that both the ACK packet transmission on the n91 and the RACK packet transmission on the n96 are performed using the transmission timer TI.
, and when ACK packet transmission fails a predetermined number of times, or when a RACK packet cannot be transmitted even after transmitting ACK packets a predetermined number of times, error handling is performed.

When the RACK packet is transmitted by terminal device A as described above, terminal device N receives n82-”n83→n84→
Proceed to n98. When a normal state transition occurs, the transmission of the ACK packet is already finished when the RAcK packet is received, and the process proceeds from n98 to n97 to set the reception mode. If a RACK packet is received without transmitting an ACK packet, the ACK packet is retransmitted (n99) and the reception mode is set (n97). Further, if the received packet is an NRDY packet at n85, the process proceeds from n85 to nl00. Normally N
When receiving RDY data, proceed to nl00-ntoi after sending data data, notify the terminal device that the other party is in NRDY state fi (data cannot be accepted), and change the reception mode. Set (
n97).

The response packet is sent at 182 and below as described above, but the data packet is received by the main judge and ACK is sent.
When the bagasoto is transmitted, the received data is transferred to and from the terminal device via the transmit/receive data transfer control circuit. This procedure is shown below.

At n110, the terminal device N connects to the main C (not shown).
Check whether the flag REN corresponding to the channel specified by the PU is set. If the flag REN corresponding to that channel is set, a received data read command is given to the received data control circuit 2 (nllll).

Then, the above flag REN is reset and (n1
12), the CPU 5 sets the start address and received data length (number of bytes) of the buffer G (of the designated channel number) in the memory 5 in the DMAC 3 to prepare for DMA transfer (n113). Furthermore, the CPU 5 selects a channel to be used for data transfer (different from the specified channel above, refers to a data transfer channel within the interface) using DRQ2.
(nl14) and instructs DMA transfer (nll
5) - Then, 1 byte of data is transferred from BA, 7FA G to register b (n1.16), and terminal device N
An interrupt signal is output for (nl17)
. When the terminal device N receives this interrupt signal,
The process proceeds from n130 to nl31 to take in the data transferred to register b. On the other hand, the data presence flag REN
is reset at nll2, one new byte of data is transferred from buffer F to buffer G at n7B. At the same time, the flag REN is reset at n77. Therefore, nlllO below is executed again,
The next 1 byte of data is set in register b at nll6, and the terminal device N takes in the data at n13l.

Repeating this operation, when all the data in buffer G is taken in through register b, the DMA transfer is completed, the process proceeds from nll9 to n120, and DMAC3 stops its operation.

The terminal device N side checks whether the number of bytes of the received data matches the number of bytes of the actually captured data, and if they match, processes the captured data into the desired format (nl33), and the processing is completed. Once completed (nl3
4) Set the flag RED of the reception data transfer control circuit 2 (nl35) to notify the interface side of the completion of the capture. When the CPU 5 on the interface side detects that the flag RED is set (n12l), it resets the flag RED (ri122) and prepares for the next data transmission/reception.

In the receiving operation, the flag RED serves as an interface management state storage means in the terminal device, as described above. That is, by setting the flag RED, a data transfer request for the next block from the interface is permitted.

As described above, specific data is transmitted from the terminal device A to the terminal device N.

(3) Power outage processing operation FIG. 12 is a flowchart showing operations during a power outage.

A power outage is detected at the terminal device. When a power failure detection circuit (not shown) detects a power failure, the terminal devices sequentially notify the power failure from the first interface to the nth interface. That is, at n150, the flag PDF of the first interface is set. Similarly, n
2nd interface to nth interface in l51 to n152
Go to set the flag PDF of the th interface.

By setting the flag PDF, the interface executes a power failure processing routine with a high interrupt priority. First, in n160, the flags of the transmission/reception data transfer control circuits 1 and 2 are saved in area H of the memory 4. Subsequently, other power outage processing is performed (n161), and in n162, the flag PDF is reset, and then the process shifts to HALT mode.

On the other hand, in the terminal device, after setting the flag PDF of all interfaces in nl52, the terminal device itself performs power outage processing (nl53). When this process is completed, it is then checked whether the flags PDF of all interfaces have been reset (n154). All flags PDF
Once reset, the process proceeds to n155, outputs a reset signal, and ends the process. At n155, the terminal device itself and all interfaces connected to the terminal device are reset and powered off.

When the power is restored, the flags stored in area H are referenced and data transfer control is performed. In this case, the sent state of the flag WED is referred to in the transmission operation, and the set state of the flag RED is referred to in the reception operation. Flag W
As is clear from FIG. 10(A), when ED is at cent, it indicates that one block of data transfer has been completed. In other words, it indicates that a power outage occurred at the time when the data transfer of block (1) was completed. Therefore, when the power is restored, if the terminal device checks this flag WED and sets it, it is sufficient to transfer data for the next new block. On the other hand, if the flag WED is reset when the power is restored, the original one block data transfer is performed again from the beginning.

Further, when the flag RED is set, it indicates that one block of data transfer has been completed, as is clear from FIG. 11(A). Therefore, as in the case of transmission, if the flag RED is set when the power is restored, transfer the data of the next new block, and if it is reset, transfer the data of the original new block. As shown in the figure, even if a power outage occurs, the interface management status of the main system is saved in the backup memory at the time of the power outage, and the data is sent after the interface power outage processing and the main system power outage processing are completed. The phase can be matched between the main system and the interface when the power is restored after a power outage.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a local networking system to which the present invention is applied. FIG. 2 is a block diagram of the transmission interface I/F, and FIG. 3 is a more detailed block diagram thereof. FIG. 4 is a circuit diagram of a collision detection circuit provided in the line control circuit 8. FIG. 5 is a circuit diagram of a carrier detection circuit provided in the line control circuit 9. Moreover, FIG. 6 is a timing chart of the same carrier detection circuit. FIG. 7 shows the relationship between the signals on the line and the signals CDI and CD2. FIG. 8 shows the basic transmission procedure in this local network. FIG. 9 is a diagram showing the packet format. FIGS. 10(A) to 10(C) are flowcharts showing the data transmission operation. FIGS. 11(A) to 11(C) are flowcharts showing the data receiving operation. FIG. 12 is a flowchart showing the power outage processing operation. FIG. 13 shows the operation when terminals A, B, and C attempt to access almost simultaneously and a collision occurs. FIG. 14 shows the configuration of the data packet sent out on the line. (Fig. 2) 10-1 transmission control circuit, l1- reception control circuit, 12- transmission/reception data transfer control circuit, (Fig. 3) 1- transmission data transfer control circuit, 2- reception data transfer control circuit, 3-DMAC ( Direct memory access controller), 4-memory (Banteli bank up),
5 - Sub CPU 6 - control circuit, 7 - Link controller, 8 - Line control circuit (transmission), 9 - Line control path (reception). -2 row-242- -243- 244-245-246-

Claims (1)

[Claims] In a device having an interface connected to a +11 data transmission line and controlling data transmission, and a main system managing this interface and processing transmitted and received data, a management information storage means for storing the interface management state in the main system. and,
The interface is provided with a battery backup storage means for storing the management information at that time stored in the storage means when there is a power outage notification from the main system; The main system is provided with a power outage processing completion determining means for determining whether the power outage processing is completed at the interface after the processing is completed, and a means for resetting the main system and the interface when the determining means determines that the power outage processing is complete. , at the time of a power outage, the interface management state at that time is stored in the battery bank amplifier storage means, and a reset process is performed after completing the power outage processing at the interface and the power outage processing at the main system; System power outage handling device.