JP3298018B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter referred to as a PC) having a pulse catch circuit.

[0002]

2. Description of the Related Art FIG. 6 is a timing chart showing the operation of a PC. As shown in the figure, the PC generally cyclically repeats input transfer, instruction execution, and output transfer. In input transfer, ON / OFF information is fetched from an input terminal to an input relay, and in command execution, arithmetic processing is performed based on ON / OFF information of the input relay, and the result is reflected in an output relay. In the output transfer, ON / OFF information of the output relay is output to the output terminal. Thus, the ON / OFF information of the input terminal is transmitted at the time of input transfer (b
Therefore, when a pulse signal which rises during the execution of the instruction (timing a) and immediately falls is input to the input terminal, it cannot be captured to the input relay.

FIG. 7 shows an example of such a case.
9 is a timing chart showing the operation of a PC provided with a pulse catch circuit having a pulse catch function for taking in a signal having a short pulse width that cannot be taken in by ordinary processing. This pulse catch circuit is designed so that an input signal can be taken into an input relay even if its ON / OFF information changes in addition to input transfer. The pulse catch circuit detects the rising of the signal at the input terminal and sets the latch status (at timing c) to temporarily hold the latch status. At the time of input transfer, the latch status is taken into the pulse catch relay (timing d). Thereafter, the latch status is reset in preparation for taking in the next pulse (timing e). Then, the pulse catch relay is held in the current scan and reset by the input transfer of the next scan (timing f).

[0004]

FIG. 8 is a timing chart showing the operation of the pulse catch relay.
Is a timing chart showing the operation of a normal input relay. As shown, the pulse catch relay takes in the rising signal and holds the signal for only one scan. However, unlike a normal input relay, the pulse catch relay does not perform a process of capturing an input signal every time an input is transferred, and thus the pulse catch relay cannot be used as a normal input relay shown in FIG. For this reason,
When performing pulse catch and normal input from the same signal,
In spite of the same signal, the input terminal for pulse catch and the input terminal for normal input must be divided, and the same terminal cannot be used together.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has been made in consideration of the problem that a signal from the same input terminal can be taken into both a pulse catch relay and a normal input relay. The purpose is to provide.

[0006]

According to the present invention, a PC includes an input circuit to which an input signal is input, an input relay for receiving an input signal from the input circuit at the time of input transfer, and a pulse catcher for holding an input pulse for a predetermined time. And a pulse catch relay that captures the output of the pulse catch circuit at the time of input transfer, and is a programmable controller that performs arithmetic processing based on the signals of the input relay and the pulse catch relay at the time of executing the instruction. The input terminal is connected to an input circuit, and an input relay for receiving a signal obtained through the input terminal is provided.

[0007]

In the present invention, the signal of the input terminal for pulse catch is taken into the pulse catch relay and also taken into the input relay.

[0008]

FIG. 1 is a block diagram showing a hardware configuration of a PC according to an embodiment of the present invention. This PC is CPU1, R
It comprises an OM 2, a RAM 3, an I / O port 4, and a pulse catch circuit 5. The ROM 2 stores a program for controlling the arithmetic processing of the CPU 1. RAM3
Stores various data. In this embodiment, a pulse catch relay 3a, an input relay 3b, an output relay 3c and the like are built in. Note that these relays are not mechanical relays, and when data of "1" or "0" is set in each storage element, they correspond to ON or OFF of the relay, and thus are referred to as such. The pulse-catch relay 3a stores pulse-caught data, the input relay 3b stores input data, and the output relay 3c stores calculation results.
The I / O port 4 is connected to an output terminal and an input terminal, receives an input signal via the input terminal, and sends an output signal via the output terminal. Pulse catch circuit 5
Has a function of capturing a change in the input signal and temporarily holding the change as described in the related art.

FIG. 2 is a block diagram showing an input port 4a of the I / O port 4. As shown in FIG. The input port 4a is connected to input terminals 41 to 43, which are connected to buffer circuits 44 to 46. And the buffer 47
Are connected to the input terminal 44 of the pulse catch circuit 5.

FIG. 3 is a flowchart showing the operation during the operation of the PC. When driving is started, as shown in FIG.
The CPU 1 fetches an input signal via the I / O port 4 by input transfer, and fetches it into the input relay 3b of the RAM 3 (S1). When the CPU 1 captures all input signals,
Next, based on the program stored in the ROM 2, a calculation process is performed using the input data that has already been captured, and the calculation result is captured in the output relay 3c of the RAM 3 (S
2). Next, the CPU 1 reads out the output relay 3c and outputs it via the I / O port 4 (S3). The above calculation process is cyclically repeated until the power is turned off or there is a stop.

FIG. 4 is a flowchart showing details of the input transfer, and FIG. 5 is a timing chart showing the operation state at that time. When a pulse signal is input to the input terminal 44 during operation, the pulse catch circuit 5 latches the pulse signal, and the state appears in the latch status k of the circuit. The latch status at this time is "1" as shown in FIG. When the input transfer is performed, first, the CPU 1 inputs the latch status at the timing of h in FIG.
(S11). Next, the CPU 1 sets the input terminals 41 to 4
4 is taken into the input relay 3b via the buffers 45-48 (S12).

The pulse catch circuit 5 automatically resets its latch status after a predetermined time and detects a change in the signal at the input terminal 44. Therefore, when the input signal remains at "1" as shown in FIG. , The reset state is maintained as it is. Therefore, when the latch status is input at the timing of i in the next input transfer, the catch pulse relay 3a is reset. In a normal input signal transfer, the state of the signal at the input terminal 44 is input, so that the input relay 3b is kept set.

The above-mentioned normal input signal terminal and pulse catch input terminal are not limited to the number of the above-mentioned embodiments, but can be changed as appropriate. Further, the order of each processing in the flowchart of FIG. 4 may be reversed.

[0014]

As described above, according to the present invention, the signal from the input terminal for pulse catch is taken into the pulse catch relay and also taken into the input relay, so that the signal from the same input terminal is provided in two forms. It can be imported, and the application range of the user's application is expanded.
Further, since the state of the signal at the input terminal for pulse catching can be confirmed by the input relay, it is not necessary to check the terminal using a tester or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a hardware configuration of a PC according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an input port portion of an I / O port of the embodiment.

FIG. 3 is a flowchart showing an operation during operation of the PC of the embodiment.

FIG. 4 is a flowchart showing details of input transfer in the embodiment.

FIG. 5 is a timing chart showing an operation state of the embodiment.

FIG. 6 is a timing chart showing the operation of a conventional PC.

FIG. 7 is a timing chart showing an operation of a PC having a conventional pulse catch circuit.

FIG. 8 is a timing chart showing an operation of the pulse catch relay.

FIG. 9 is a timing chart showing the operation of a normal input relay.

Claims (1)

(57) [Claims] An input circuit to which an input signal is input, an input relay for receiving an input signal from the input circuit at the time of input transfer, a pulse catch circuit for holding an input pulse for a predetermined time, and an output of the pulse catch circuit. A pulse catch relay for capturing at the time of input transfer, wherein the programmable controller performs an arithmetic process based on signals of the input relay and the pulse catch relay at the time of executing an instruction, wherein a pulse catch input terminal of the pulse catch circuit is connected to an input circuit. A programmable controller, further comprising an input relay connected to the input terminal and for receiving a signal obtained through the input terminal.