JPH05289714A - Programmable controller - Google Patents

Abstract

PURPOSE:To fetch signals supplied from the same input terminal to both a pulse catching relay and a normal input relay. CONSTITUTION:In a programmable controller which fetches the input signals to an input relay 3b via an input/output port 4 and also fetches the input pulses to a pulse catch relay 3a via a pulse catch circuit 5 respectively, the programmable controller is provided with a pulse catch input terminal 44 of the circuit 5 connected to the circuit 5 and also contains an input relay which fetches the signals obtained via the terminal 44. Thus the signals supplied through the terminal 44 are fetched to both relays 3 and 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter referred to as PC) having a pulse catch circuit.

[0002]

2. Description of the Related Art FIG. 6 is a timing chart showing the operation of a PC. As shown, the PC generally cyclically repeats input transfer, command execution, and output transfer. In the input transfer, the ON / OFF information is fetched from the input terminal to the input relay, and in the command execution, arithmetic processing is performed based on the ON / OFF information of the input relay, and the result is reflected in the output relay. In output transfer, ON / OFF information of the output relay is output to the output terminal. In this way, the ON / OFF information of the input terminal is transferred during input transfer (b
However, if a pulse signal that rises and immediately falls during command execution (timing a) is input to the input terminal, it cannot be captured by the input relay.

FIG. 7 shows a method for dealing with such a case.
6 is a timing chart showing the operation of a PC provided with a pulse catch circuit having a function of pulse catch that takes in a signal with a short pulse width that cannot be taken in by normal processing. This pulse catching circuit is designed so that the input signal can be taken into the input relay even if the ON / OFF information of the input signal changes in addition to the input transfer. The pulse catch circuit detects the rising edge of the signal at the input terminal, sets the latch status, and temporarily holds it (timing c). Then, at the time of input transfer, the latch status is taken into the pulse catch relay (timing d). After this, the latch status is reset in preparation for fetching the next pulse (timing e). Then, the pulse catch relay is held in this scan and reset by the input transfer of the next scan (timing of f).

[0004]

FIG. 8 is a timing chart showing the operation of the pulse catch relay, and FIG.
Is a timing chart showing the operation of a normal input relay. As shown in the figure, the pulse catch relay takes in the rising signal and holds the signal only for one scan. However, unlike the normal input relay, the pulse catch relay does not process the input signal for each input transfer, and the pulse catch relay cannot be used as the normal input relay shown in FIG. For this reason,
When performing pulse catch and normal input from the same signal,
Despite the same signal, the input terminal for pulse catching and the input terminal for normal input must be separated, and the same terminal cannot be used together.

The present invention has been made in order to solve such a problem and is a PC which can take in a signal from the same input terminal to both a pulse catch relay and a normal input relay. The purpose is to provide.

[0006]

A PC according to the present invention is a PC in which an input signal is taken into an input relay via an input circuit and an input pulse is taken into a pulse catch relay via a pulse catch circuit. The input terminal for pulse catch of is also connected to the input circuit, and an input relay for taking in a signal obtained through the input terminal is provided.

[0007]

In the present invention, the signal from the pulse catch input terminal is taken into the pulse catch relay and also into the input relay.

[0008]

1 is a block diagram showing a hardware configuration of a PC according to an embodiment of the present invention. This PC is CPU1, R
It is composed of an OM2, a RAM3, an I / O port 4 and a pulse catch circuit 5. The ROM 2 stores a program that controls the arithmetic processing of the CPU 1. RAM3
Stores various data. In this embodiment, the pulse catch relay 3a, the input relay 3b, the output relay 3c, etc. are built in. Note that these relays are not mechanical relays, and when data "1" or "0" is set in each storage element, they correspond to turning on or off of the relays, so they are called as such. The pulse catch relay 3a stores the pulse caught data, the input relay 3b stores the input data, and the output relay 3c stores the calculation result.
An output terminal and an input terminal are connected to the I / O port 4, and an input signal is taken in through the input terminal and an output signal is sent out through the output terminal. Pulse catch circuit 5
Has a function of catching and temporarily holding a change in the input signal as described in the related art.

FIG. 2 is a block diagram showing a portion of the input port 4a of the I / O port 4. The input port 4a is connected to the input terminals 41 to 43, which are connected to the buffer circuits 44 to 46. And the buffer 47
Is connected to the input terminal 44 of the pulse catch circuit 5.

FIG. 3 is a flowchart showing the operation of the PC during operation. When the operation is started, as shown in FIG.
The CPU 1 takes in an input signal through the I / O port 4 by input transfer and takes it into the input relay 3b of the RAM 3 (S1). When the CPU 1 takes in all input signals,
Next, based on the program stored in the ROM2, the arithmetic processing is performed using the input data that has already been captured, and the calculation result is captured into the output relay 3c of the RAM3
2). Next, the CPU 1 reads the output relay 3c and outputs it through the I / O port 4 (S3). The above arithmetic processing is cyclically repeated until the power is turned off or there is a stop.

FIG. 4 is a flow chart showing the details of the input transfer, and FIG. 5 is a timing chart showing the operation state at that time. When a pulse signal is input to the input terminal 44 during operation, the pulse catch circuit 5 latches the pulse signal, and that state appears in the latch status k of the circuit. The latch status at this time is "1" as shown in FIG. Then, in the case of input transfer, the CPU 1 first inputs the latch status at the timing h in FIG.
(S11). Next, the CPU 1 uses the input terminals 41 to 4
The input signal of No. 4 is taken into the input relay 3b via the buffers 45 to 48 (S12).

Since the pulse catch circuit 5 automatically resets its latch status after a predetermined time and detects a signal change at the input terminal 44, when the input signal remains "1" as shown in the figure. The reset state is maintained as is. Therefore, when the latch status is input at the timing i in the next input transfer, the catch pulse relay 3a is reset. Since the state of the signal at the input terminal 44 is input in the normal transfer of the input signal, the state in which the input relay 3b remains set is maintained.

The above-mentioned normal input signal terminals and pulse catch input terminals are not limited to the numbers in the above-mentioned embodiments, but can be changed appropriately. Furthermore, the order of each process in the flowchart of FIG. 4 may be reversed.

[0014]

As described above, according to the present invention, the signal from the input terminal for pulse catch is taken into the pulse catch relay and also into the input relay. Therefore, the signal from the same input terminal is in two forms. It can be imported, expanding the range of applications for user applications.
Moreover, since the signal state of the pulse catching input terminal can be confirmed by the input relay, it is not necessary to check the terminal with a tester or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration of a PC according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an input port portion of an I / O port of the above embodiment.

FIG. 3 is a flowchart showing an operation during operation of the PC of the embodiment.

FIG. 4 is a flowchart showing details of input transfer in the embodiment.

FIG. 5 is a timing chart showing an operation state of the embodiment.

FIG. 6 is a timing chart showing the operation of a conventional PC.

FIG. 7 is a timing chart showing the operation of a PC including a conventional pulse catch circuit.

FIG. 8 is a timing chart showing the operation of the pulse catch relay.

FIG. 9 is a timing chart showing the operation of a normal input relay.

Claims (1)

[Claims] 1. A programmable controller for receiving an input signal into an input relay via an input circuit and capturing an input pulse into the pulse catch relay via a pulse catch circuit, wherein a pulse catch input terminal of the pulse catch circuit is provided in the input circuit. A programmable controller, which is also provided with an input relay which is also connected to the input relay and which receives a signal obtained through the input terminal.