JPS60241104A - Arithmetic method of digital controller - Google Patents

Arithmetic method of digital controller

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Publication number
JPS60241104A
JPS60241104A JP9651784A JP9651784A JPS60241104A JP S60241104 A JPS60241104 A JP S60241104A JP 9651784 A JP9651784 A JP 9651784A JP 9651784 A JP9651784 A JP 9651784A JP S60241104 A JPS60241104 A JP S60241104A
Authority
JP
Japan
Prior art keywords
processing
sequence
numerical
circuit
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9651784A
Other languages
Japanese (ja)
Inventor
Hiroshi Nagase
博 長瀬
Miki Kajita
梶田 美樹
Tsutomu Omae
大前 力
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP9651784A priority Critical patent/JPS60241104A/en
Publication of JPS60241104A publication Critical patent/JPS60241104A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To perform both the sequence processing and the numerical processing at a high speed and with high efficiency by executing the sequence processing only when a sequence data input signal has a change and otherwise carrying out the numerical processing. CONSTITUTION:In an arithmetic method of the digital controller for both the sequence processing and the numerical processing, the ON/OFF signals I1-In are supplied to a signal change discriminating circuit 1 for a switch, etc. supplied for the sequence processing. Then the changes of these signals are detected, and this detection output is supplied to an instruction switch circuit 2. The circuit 2 decide to start a sequence instruction circuit 3 or a numerical processing instruction circuit 4. The result of this decision is supplied to the corresponding circuit. The output signals of both circuits 3 and 4 are supplied to an arithmetic circuit 5 for execution of an operation. The sequence processing is carried out only when a sequance data input signal has a change. Thus it is possible to perform both sequence and numerical processings at a high speed through the same arithmetic circuit.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はシーケンス処理と数値処理の両方の処理演算機
能をもつディジタル制御装置の演算方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a calculation method for a digital control device having both sequence processing and numerical processing processing functions.

〔発明の背景〕[Background of the invention]

シーケンス処理をプログラムによって行う制御装置にプ
ログラマブル・コントローラ(以後、PCと略称する)
がある。PCはシーケンス処理をプログラムによって行
うので、従来のリレー回路よシも取扱いが容易という利
点を有し広く使用されるようになっている。PCの応用
分野が広がると、単にオン、オフ信号を扱うシーケンス
処理機能だけでなく、シーケンス処理を行いながら、算
術演算を扱う数値処理を行うというように両者を同時に
行える装置が必要となる。これらの処理は2つの別なフ
ローとして記述されるために、同一処理装置でこれらを
実行するにはシーケンス処理と数値処理を時分割に実行
する必要がある。このために、たとえば従来は一連のシ
ーケンス処理を実行した後に数値処理を実行し、それが
終るとシーケンス処理を再び実行する方法が考えられて
いる。あるいは、シーケンス処理または数値処理を実行
するプログラムの中のところどころにシーケンス処理か
ら数値処理へ実行に移す命令あるいはその逆の命令を入
れ、この命令が出る毎にシーケンス処理から数値処理へ
、数値処理からシーケンス処理へと処理が実行され、シ
ーケンス処理と数値処理が交互に行なわれるような方法
が考えられている。
A programmable controller (hereinafter abbreviated as PC) is a control device that performs sequence processing by program.
There is. Since PCs perform sequence processing through programs, they have the advantage of being easier to handle than conventional relay circuits, and have come to be widely used. As the field of application of PCs expands, it becomes necessary not only to have a sequence processing function that simply handles on and off signals, but also to have a device that can simultaneously perform both sequence processing and numerical processing that handles arithmetic operations. Since these processes are described as two separate flows, in order to execute them with the same processing device, it is necessary to execute the sequence processing and the numerical processing in a time-sharing manner. For this purpose, for example, conventionally, a method has been considered in which numerical processing is performed after a series of sequence processing is performed, and when the numerical processing is completed, the sequence processing is performed again. Alternatively, you can insert an instruction to move from sequence processing to numerical processing, or vice versa, somewhere in a program that executes sequence processing or numerical processing, and each time this command is issued, the sequence processing changes to numerical processing, and vice versa. A method has been considered in which processing is executed in sequence, and sequence processing and numerical processing are performed alternately.

しかしながら、これらの方法には次の問題点がある。す
なわち、前者の方法は数値処理が多い場合、数値処理の
実行時間が長くなるので、次にシーケンス処理が実行さ
れるまでに時間がかかり、実質的なシーケンス処理の実
行時間が長くなる問題がある。一方、後者の方法はシー
ケンス処理から数値処理へ、あるいはその逆へと処理を
変えるためにプログラムが煩雑になるというだけでなく
、例えばシーケンス処理のなかにタイマー動作がある場
合に、タイマ動作中に数値処理を実行しようとするとこ
の処理とは別にタイマー管理を行う必要があり装置が複
雑になるという問題がある。
However, these methods have the following problems. In other words, in the former method, when there is a lot of numerical processing, the execution time of numerical processing becomes long, so it takes time until the next sequence processing is executed, and there is a problem that the actual execution time of sequence processing becomes longer. . On the other hand, the latter method not only makes the program complicated because it changes the processing from sequence processing to numerical processing or vice versa, but also, for example, if there is a timer operation in the sequence processing, When attempting to perform numerical processing, it is necessary to manage timers separately from this processing, which poses a problem in that the apparatus becomes complicated.

〔発明の目的〕[Purpose of the invention]

本発明は上記欠点に対してなされたもので、その目的と
するところはシーケンス処理と数値処理を効率良く高速
に行えるディジタル制御装置の演算方法を提供すること
にある。
The present invention has been made to address the above-mentioned drawbacks, and its purpose is to provide a calculation method for a digital control device that can perform sequence processing and numerical processing efficiently and at high speed.

〔発明の概要〕[Summary of the invention]

本発明の特徴とするところは、シーケンスデータ入力信
号が変化したときのみシーケンス処理を実行し、その他
のときは論理演算を含む算術演算を行うための数値処理
演算を実行するようにすることによってシーケンス処理
回数を実質的に減少させ、シーケンス処理と数値処理を
高速に実行できるようにしたことにある。
A feature of the present invention is that sequence processing is executed only when the sequence data input signal changes, and numerical processing operations for performing arithmetic operations including logical operations are executed at other times. The purpose is to substantially reduce the number of processing times and to be able to execute sequence processing and numerical processing at high speed.

〔発明の実施例〕[Embodiments of the invention]

第1図に本発明の一実施例を示す。 FIG. 1 shows an embodiment of the present invention.

第1図において、II〜工、はシーケンス処理のために
入力されるスイッチ等のオン、オフ信号で、これがデー
タ処理装置に入力される。また信号11〜■、はディジ
タル制御装置外部からの信号だけではなく、あるシーケ
ンス演算、すなわち、オン、オフ状態から論理演算を行
い、結果を出力する演算に必要であればディジタル制御
装置内で演算した信号でもよい。信号11〜I、は信号
変化判別回路1に入力され、信号11〜I、の変化が検
出される。信号変化判別回路1の出力は命令切換回路2
に入力される。命令切換回路2はシーケンス命令回路3
めるいは数値処理命令回路4のいずれかを起動するか決
める。その結果は、シーケンス命令回路3または数値処
理命令回路4に入力される。シーケンス命令回路3と数
値処理命令回路4の出力信号は演算回路5に入力され・
演算が実行される。なお、ここでいう数値処理とは、単
なる数値演算だけでなく、それにともなう論理演算や条
件判定などが必要であれば、それらを含めたものでおる
In FIG. 1, reference numerals II to D indicate on/off signals of switches, etc., input for sequence processing, which are input to the data processing device. In addition, signals 11 to ■ are not only signals from outside the digital control device, but also perform a certain sequence operation, that is, a logical operation from the on/off state, and if necessary for the operation that outputs the result, the signal is calculated within the digital control device. It may be a signal that Signals 11-I are input to the signal change determination circuit 1, and changes in signals 11-I are detected. The output of the signal change discrimination circuit 1 is sent to the command switching circuit 2.
is input. The instruction switching circuit 2 is the sequence instruction circuit 3.
The first step is to decide which one of the numerical processing command circuits 4 to start. The result is input to the sequence instruction circuit 3 or the numerical processing instruction circuit 4. The output signals of the sequence instruction circuit 3 and the numerical processing instruction circuit 4 are input to the arithmetic circuit 5.
The operation is executed. Note that the numerical processing referred to here includes not only simple numerical calculations but also accompanying logical calculations and conditional judgments, if necessary.

この動作を第2図の動作波形を用いて説明する。This operation will be explained using the operation waveforms shown in FIG.

信号11〜1.のどれかが変化すると、信号変化判別回
路Iにおいて検出される。信号変化判別回路は第2図(
a)に示すようなパルス状の信号を出力する。オン、オ
フ信号11〜1.が変化、すなわちシーケンスデータ入
力状態の変化によって命令切換回路2に第2図(a)の
ようなパルス信号が入力されると、命令切換回路2はシ
ーケンス命令回路3に起動命令を出す。シーケンス命令
回路3が起動されシーケンス命令信号が演算回路5に入
力されると、演算回路5は数値処理の実行を中止し、現
在のデータ等を内蔵のメモリに格納してシーケンス命令
を実行する。一連のシーケンス処理が終了すると、終了
信号がシーケンス命令口#63から命令切換回路2に出
される。命令切換回路2は数値処理命令回路4に起動命
令を出す。′数値処理命令が演算回路5に入力されると
、先のシーケンス処理を実行する直前の状態から数値処
理が開始され、数値処理命令に従って演算回路5が動作
する。
Signal 11-1. If any one of them changes, it is detected by the signal change determination circuit I. The signal change discrimination circuit is shown in Figure 2 (
A pulse-like signal as shown in a) is output. On, off signals 11-1. When a pulse signal as shown in FIG. 2(a) is input to the command switching circuit 2 due to a change in the sequence data input state, that is, a change in the sequence data input state, the command switching circuit 2 issues an activation command to the sequence command circuit 3. When the sequence command circuit 3 is activated and a sequence command signal is input to the arithmetic circuit 5, the arithmetic circuit 5 stops executing numerical processing, stores the current data, etc. in the built-in memory, and executes the sequence command. When a series of sequence processing is completed, an end signal is sent to the command switching circuit 2 from the sequence command port #63. The instruction switching circuit 2 issues a start instruction to the numerical processing instruction circuit 4. 'When a numerical processing command is input to the arithmetic circuit 5, numerical processing is started from the state immediately before executing the previous sequence process, and the arithmetic circuit 5 operates according to the numerical processing command.

第2図(b)、(C)は演算回路5における命令実行状
況を示す。第2図(b)はシーケンス処理、(C)は数
値処理が実行される様子を示す。第2図から、同図(a
)に示すオン・オフ信号の変化時に得られるパルス信号
が出される毎にシーケンス処理が実行されることがわか
る。このとき、シーケンス処理はシーケンス処理命令の
最初からスタートしてもよく、あるいはシーケンス処理
の現在までの状況からシーケンス命令のどこの部分を実
行すればよいかがわかる場合にはその部分だけを実行す
るようにしてもよい。後者の場合、シーケンス処理に要
するシーケンスデータ入力信号II〜工、を全部読み込
む必要はなく、さらにシーケンス処理に要する時間が短
くできるという利点がある。
FIGS. 2(b) and 2(C) show the instruction execution status in the arithmetic circuit 5. FIG. FIG. 2(b) shows how sequence processing is performed, and FIG. 2(C) shows how numerical processing is performed. From Figure 2, the same figure (a
It can be seen that the sequence processing is executed every time the pulse signal obtained when the on/off signal changes as shown in ) is output. At this time, sequence processing may start from the beginning of the sequence processing instruction, or if it is known which part of the sequence instruction should be executed from the current status of sequence processing, only that part may be executed. You may also do so. In the latter case, there is no need to read all of the sequence data input signals II to II required for sequence processing, and there is an advantage that the time required for sequence processing can be shortened.

第3図はさらに数値処理のなかでフィードバック制御等
を行うために一定周期で演算を行う必要の処理がある場
合の動作説明図である。第3図(a)は信号変化判別回
路1の出力信号、(b)はシーケンス処理が実行されて
いる状態、(C)は一定周期で演算する数値処理が実行
されている状態、(ψは前記外の数値処理が実行されて
いる状態を示す。第3図(a)のようなパルス信号が出
されると同図(b)のようにシーケンス処理が実行され
る。この場合、同図(C)の一定周期で処理される数値
処理がシーケンス処理中にも存在する場合には、シーケ
ンス処理が中断され一定周期の数値処理が優先される。
FIG. 3 is an explanatory diagram of the operation in the case where there is a process in which calculations need to be performed at regular intervals in order to perform feedback control or the like in the numerical processing. FIG. 3 (a) shows the output signal of the signal change discrimination circuit 1, (b) shows the state where sequence processing is being performed, (C) shows the state where numerical processing is performed in a constant cycle, and (ψ is This shows a state in which numerical processing other than the above is being executed. When a pulse signal as shown in Fig. 3(a) is output, sequence processing is executed as shown in Fig. 3(b). If the numerical processing in C) that is processed at a constant cycle also exists during sequence processing, the sequence processing is interrupted and priority is given to the numerical processing at a constant cycle.

一定周期の数値処理は演算回路5内のタイマでその起動
が管理さ、れる。シーケンス処理も一定周期の数値処理
も実行されていない場合には第3図(d)のようにその
他の数値処理が実行される。
The activation of the constant period numerical processing is managed by a timer within the arithmetic circuit 5. If neither sequence processing nor fixed period numerical processing is being executed, other numerical processing is executed as shown in FIG. 3(d).

以上のように演算を行うのであるが、シーケンスデータ
入力信号が変化したときのみシーケンス処理を実行する
ので、シーケンス処理実行回数が少なくなるために効率
良くかつ高速にシーケンス処理と数値処理を同一の演算
回路によって実行することができる。
Calculations are performed as described above, but since sequence processing is executed only when the sequence data input signal changes, the number of sequence processing executions is reduced, making it possible to efficiently and quickly perform sequence processing and numerical processing in the same operation. It can be implemented by a circuit.

第4図は第1図の実施例を具体的に実行するための詳細
回路例を示す。単安定マルチバイブレータ11〜15は
シーケンス上の入力信号工1〜I。
FIG. 4 shows a detailed circuit example for concretely implementing the embodiment shown in FIG. Monostable multivibrators 11 to 15 are input signal components 1 to I on the sequence.

が入力され、入力信号が変化したときにパルス状の信号
を出力する。単安定マルチバイブレータ11〜15の出
力は論理和回°路16に入力され、さらに論理和回路1
6の出力はマイクロプロセッサ17の割込端子に入力さ
れる。マイクロプロセッサ17の入出力信号はバス23
を介して、シーケンス用の入力回路18、シーケンス用
の出力回路19、数値信号の入出力を行う入出力回路2
0、メモリ21.22に接続される。
is input, and outputs a pulse-like signal when the input signal changes. The outputs of the monostable multivibrators 11 to 15 are input to the OR circuit 16, and further to the OR circuit 1.
The output of 6 is input to the interrupt terminal of microprocessor 17. The input/output signals of the microprocessor 17 are connected to the bus 23.
A sequence input circuit 18, a sequence output circuit 19, and an input/output circuit 2 for inputting and outputting numerical signals through the
0, connected to memory 21.22.

−第4図の構成において、シーケンスデータ入力信号1
1〜工・のいずれかが変化すると、その変化は単安定マ
ルチバイブレータ11〜15によって検出され、それは
論理和回路16を介して、マイクロプロセッサ17の割
込端子に入力される。
- In the configuration shown in Figure 4, sequence data input signal 1
When any one of 1 to 1 changes, the change is detected by the monostable multivibrators 11 to 15, and is input to the interrupt terminal of the microprocessor 17 via the OR circuit 16.

マイクロプロセッサ17は割込み信号を受けるとシーケ
ンス処理を実行するため、数値処理を中止し、現在の状
態をメモリ21に入力する。次に、シーケンス命令がメ
モリ22から読み出され、シーケンス処理が実行される
。シーケンスデータ信号■1〜工、は入力回路18を通
して読みとられ、シーケンス処理の結果は出力回路19
を通して出力信号01〜0.として出力される。シーケ
ンス処理が終了すると、シーケンス処理が実行される前
の状態に戻り、数値処理がメモリ22からの命令に従っ
て実行される。演算で必要な数値は入出力回路20を通
して外部機器へ出力される。
When the microprocessor 17 receives an interrupt signal, it executes sequence processing, so it stops numerical processing and inputs the current state into the memory 21. Next, the sequence instructions are read from memory 22 and sequence processing is executed. The sequence data signals 1 to 1 are read through the input circuit 18, and the result of sequence processing is sent to the output circuit 19.
Output signals 01~0. is output as When the sequence processing is completed, the state returns to the state before the sequence processing was performed, and numerical processing is performed according to instructions from the memory 22. Numerical values necessary for calculation are output to external equipment through the input/output circuit 20.

第5図は以上の処理を行うためのフローチャートを示す
。第5図(a)は数値処理を実行するためのフローチャ
ートである。同図(a)には図示していないが、演算に
必要なデータ線メモリ21または入出力回路20へ入出
力される。第511(b)は割込み信号がマイクロプロ
セッサ17の割込端子に入力され、シーケンス処理を実
行するときのフローチャートを示す。この場合、先に説
明したように、これまでのシーケンス演算の結果から、
シーケンス命令のどこの部分を実行すればよいかがわか
る場合、そこだけを実行してもよい。このとき、シーケ
ンスデータ入力信号■!〜工、の全部を取込む必要はな
く、必要な部分のみ取込めばよい。さらに、演算結果も
出力01〜01として総て出力せずに必要な信号のみを
変更するだけでよい。
FIG. 5 shows a flowchart for performing the above processing. FIG. 5(a) is a flowchart for executing numerical processing. Although not shown in FIG. 5A, the data is input/output to the data line memory 21 or the input/output circuit 20 necessary for calculation. No. 511(b) shows a flowchart when an interrupt signal is input to the interrupt terminal of the microprocessor 17 and sequence processing is executed. In this case, as explained earlier, from the results of the sequence operations so far,
If you know which part of a sequence instruction should be executed, you can execute only that part. At this time, the sequence data input signal ■! It is not necessary to include all of ~, but only the necessary parts. Furthermore, it is only necessary to change only the necessary signals without outputting all the calculation results as outputs 01 to 01.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によればシーケンスデータ
の入力信号が変化し、シーケンス処理が必要なところで
のみシーケンス処理が実行されるので、シーケンス処理
の回数が少なくなる。この結果、シーケンス演算に要す
る時間を短くでき、数値処理に多くの時間をあてること
ができるっこの結果、同一の演算回路上で効率よく、高
速に数値処理とシーケンス処理が実行できる。さらに、
一つの演算回路で高速のデータ処理装置が構成できるの
で、装置が安価になるという経済的な効果もある。
As described above, according to the present invention, the input signal of sequence data changes and sequence processing is executed only where sequence processing is necessary, so the number of sequence processings is reduced. As a result, the time required for sequence calculations can be shortened, and more time can be devoted to numerical processing.As a result, numerical processing and sequence processing can be performed efficiently and at high speed on the same arithmetic circuit. moreover,
Since a high-speed data processing device can be configured with one arithmetic circuit, there is also an economical effect that the device becomes cheaper.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す構成図、第2第5図は
第4図の回路の動作説明図である。 1・・・信号変化判別回路、2・・・命令切換回路、3
・・・シーケンス命令回路、4・・・数値処理命令回路
、52m +l#M− 1面 (t)
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 and 5 are diagrams explaining the operation of the circuit shown in FIG. 4. 1... Signal change determination circuit, 2... Command switching circuit, 3
...Sequence instruction circuit, 4...Numerical processing instruction circuit, 52m +l#M- 1st page (t)

Claims (1)

【特許請求の範囲】 1、論理演算を含む算術演算を行うための数値処理命令
とオン、オフ信号を処理する論理演算を行うためのシー
ケンス処理命令の命令群を格納する第1記憶手段と、外
部機器と数値データの授受を行う第1人出力手段と、前
記外部機器とシーケンスデータの授受を行う第2人出力
手段と、前記第1記憶回路からの命令に従い数値処理演
算あるいはシーケンス処理演算を実行する演算手段と、
前記演算手段で演算したデータを記憶する第2記憶手段
とを有するディジタル制御装置において、前記演算手段
は前記第1記憶手段力・らの命令の処理順序を変更する
ための割込み処理機能を有し、シーケンスデータとして
入力される信号のオン、オフ状態の変化信号を割込み信
号として入力された際に、数値処理演算を中止してシー
ケンス処理演算を実行し、シーケンス処理が終了後にシ
ーケンス処理開始前の状態からの数値処理演算を実行す
ることを特徴とするディジタル制御装置の演算方法。 2、特許請求の範囲第1項において、前記演算手段は一
定周期で演算を行う数値処理命令が存在する場合、シー
ケンス処理演算中であっても一定周期の数値処理命令を
優先して実行することを特徴とするディジタル制御装置
の演算方法。
[Scope of Claims] 1. A first storage means for storing an instruction group of numerical processing instructions for performing arithmetic operations including logical operations and sequence processing instructions for performing logical operations for processing on and off signals; a first output means for exchanging numerical data with an external device; a second output means for exchanging sequence data with the external device; and a numerical processing operation or a sequence processing operation according to instructions from the first storage circuit. arithmetic means to execute;
and second storage means for storing data calculated by the calculation means, wherein the calculation means has an interrupt processing function for changing the processing order of instructions from the first storage means. , when the on/off state change signal of the signal input as sequence data is input as an interrupt signal, the numerical processing operation is stopped and the sequence processing operation is executed, and after the sequence processing is completed, the data before the sequence processing starts is A calculation method for a digital control device, characterized by performing numerical processing calculations from a state. 2. In claim 1, when there is a numerical processing instruction that performs calculations at a constant cycle, the calculation means executes the numerical processing instruction with priority at a constant cycle even during sequence processing calculations. A calculation method for a digital control device characterized by:
JP9651784A 1984-05-16 1984-05-16 Arithmetic method of digital controller Pending JPS60241104A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9651784A JPS60241104A (en) 1984-05-16 1984-05-16 Arithmetic method of digital controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9651784A JPS60241104A (en) 1984-05-16 1984-05-16 Arithmetic method of digital controller

Publications (1)

Publication Number Publication Date
JPS60241104A true JPS60241104A (en) 1985-11-30

Family

ID=14167328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9651784A Pending JPS60241104A (en) 1984-05-16 1984-05-16 Arithmetic method of digital controller

Country Status (1)

Country Link
JP (1) JPS60241104A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6346507A (en) * 1986-08-14 1988-02-27 Mitsubishi Electric Corp High-speed arithmetic processor
JPS6413507U (en) * 1987-07-14 1989-01-24
JPH01109405A (en) * 1987-10-22 1989-04-26 Fanuc Ltd Programmable controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6346507A (en) * 1986-08-14 1988-02-27 Mitsubishi Electric Corp High-speed arithmetic processor
JPS6413507U (en) * 1987-07-14 1989-01-24
JPH01109405A (en) * 1987-10-22 1989-04-26 Fanuc Ltd Programmable controller

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