JPH0777931A - Programable controller - Google Patents

Abstract

PURPOSE:To prevent the influence from imparting to an instruction execution cycle even when a transferring data amount at the time of I/O refresh is increased. CONSTITUTION:By an MPU 11, immediately after a user program is executed, a bus switching circuit 52 is instructed so as to connect a transferring data memory 51 to an internal bus 16, and the output data of a work memory 14 are exchanged with the input data of the transferring data memory 51, and after the exchange is ended, the bus switching circuit 51b is instructed so as to switch the transferring data memory 51a to an external bus 3, and an operation start command is issued to a data transfer circuit 52, and immediately thereafter, it enters the next cycle, and the user program is executed again. On the other hand, by the data transfer circuit 52, the operation start command from the MPU 11 is received, and the output data of the transferring data memory 51a are exchanged with the input data of an I/O unit 2.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CPU unit and an I / O.
The present invention relates to a programmable controller adapted to exchange input / output data with an O unit via an external bus.

[0002]

2. Description of the Related Art Programmable controllers are usually
A CPU unit and an I / O unit for inputting / outputting input / output data are connected and configured.

In such a programmable controller, normally, as shown in FIG. 5, a microprocessor (hereinafter referred to as MPU) in a CPU unit executes a user program and an external bus between the CPU unit and the I / O unit. I / O refresh processing, that is, exchange of input / output data, is repeatedly executed via the.

[0004]

However, since the external bus between the CPU unit and the I / O unit generally has a slower data transfer rate than the internal bus in the unit, the external bus is different from the conventional programmable controller described above. Since the MPU in the CPU unit was directly performing I / O refresh with the I / O unit via the external bus, if the amount of transfer data during I / O refresh becomes large, the instruction execution cycle There is a problem in that the ratio of I / O refresh cycles to the above cannot be ignored.

Therefore, an object of the present invention is to provide a programmable controller that does not affect the instruction execution cycle even when the amount of transfer data at the time of I / O refresh becomes large.

[0006]

In order to achieve the above object, the invention according to claim 1 provides a CPU unit and an I / O.
A programmable controller in which a unit is connected to an external bus, wherein a CPU unit is connected to a microprocessor via the internal bus, and execution data storage means stores input / output data when executing a user program. And a microprocessor and execution data storage means via an internal bus, and an I / O unit via an external bus.
A data transfer means for storing input / output data transferred between the PU unit and the I / O unit, and a data transfer means are provided, and the microprocessor stores the data in the execution data storage means after executing the user program. The stored output data is transferred to the transfer data storage means, the input data stored in the transfer data storage means is transferred to the execution data storage means, and then the user program is executed. After the input / output data is transferred by the microprocessor, the output data stored in the transfer data storage means is transferred to the I / O unit, and the input data captured by the I / O unit is transferred to the transfer data storage means. It is characterized by:

According to a second aspect of the invention, in the programmable controller according to the first aspect, the microprocessor immediately transfers the output data stored in the execution data storage means to the transfer data storage means after executing the user program. Along with the transfer, the input data stored in the transfer data storage means is transferred to the execution data storage means, and then the user program is executed.

According to a third aspect of the present invention, in the programmable controller according to the first aspect, the microprocessor stores the output data stored in the execution data storage means after the execution of the user program for a certain period of time after the execution of the user program. And the input data stored in the transfer data storage means are transferred to the execution data storage means, and then the user program is executed.

According to a fourth aspect of the present invention, in the programmable controller according to the first aspect, the microprocessor immediately transfers the output data stored in the execution data storage means to the transfer data storage means after executing the user program. At the same time as the transfer, the input data stored in the transfer data storage means is transferred to the execution data storage means, and then the user program is executed, while the data transfer means transfers the input / output data by the microprocessor and then transfers the data. The output data stored in the data storage means for I
The data is transferred to the I / O unit, and the transfer of the input data taken in by the I / O unit to the transfer data storage means is repeated until the microprocessor finishes executing the user program.

[0010]

According to the first aspect of the invention, the microprocessor transfers the output data stored in the execution data storage means to the transfer data storage means after the execution of the user program, and stores the output data in the transfer data storage means. The transferred input data is transferred to the execution data storage means, and then the user program is executed, while the data transfer means transfers the input / output data by the microprocessor and then the output data stored in the transfer data storage means I The data is transferred to the I / O unit and the input data taken in by the I / O unit is transferred to the transfer data storage means.

According to another aspect of the present invention, the microprocessor transfers the output data stored in the execution data storage means to the transfer data storage means immediately after the execution of the user program.

According to the third aspect of the invention, the microprocessor transfers the output data stored in the execution data storage means to the transfer data storage means after a predetermined time has elapsed after the execution of the user program.

According to the present invention, the microprocessor transfers the output data stored in the execution data storage means to the transfer data storage means immediately after the execution of the user program, and at the same time, the transfer data storage means. The input data stored in the execution data storage means and then executes the user program, while the data transfer means transfers the input / output data by the microprocessor,
The output data stored in the transfer data storage means is I / O
The transfer to the unit and the transfer of the input data captured by the I / O unit to the transfer data storage means are repeated until the microprocessor finishes executing the user program.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a programmable controller (hereinafter referred to as PLC) according to the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a PLC according to the present invention. This PLC is configured by connecting a CPU unit 1 and an I / O unit 2 with an external bus 3.

The CPU unit 1 includes an MPU 11 that executes a user program, a system program memory 12 that stores a system program for operating the MPU 11, a user program memory 13 that stores a user program, and program instructions. It has a work memory 14 as an execution data storage means for storing input / output data at the time of execution, and an interface (I / F) circuit 15 connected to the external bus 3. Connected through.

The interface circuit 15 includes a transfer data storage unit 51 as a transfer data storage unit, and the MPU 1.
The data storage unit 51 for transfer according to the data transfer command from
Data transfer circuit 52 as data transfer means for transferring input / output data between the I / O unit 2 and the I / O unit 2 as described later.
It consists of and. In this embodiment, the transfer data storage unit 51 is a single-port transfer data memory 51.
a is connected to the internal bus 16 and the external bus 3, and MP
Data memory 51 for transfer by a switching command from U11
And a bus switching circuit 51b for switching the connection destination to either the internal bus 16 or the external bus 3.

Further, the I / O unit 2 is configured to exchange data with the CPU unit 1, perform input / output to / from an external device, and execute data processing inside the I / O unit. Although only one I / O unit 2 is shown here, a plurality of I / O units 2 can be connected to the external bus 3 and may be dedicated to input and output.

Next, the operation of the PLC of the first embodiment will be described. The first embodiment is an embodiment in which the user program execution time by the MPU 11 is longer than the data exchange time by the data transfer circuit 52 between the transfer data memory 51a and the I / O unit 2.

FIG. 2 shows the MPU 1 in the first embodiment.
1 shows a time chart of operations of 1 and the data transfer circuit 52.

In the case of the first embodiment, the user program execution time t1 by the MPU 11 is shorter than the data transfer circuit 5.
3 is longer than the data exchange time t2 with the I / O unit 2, the MPU 11 immediately sends a switching command to the bus switching circuit 52 to connect the transfer data memory 51 to the internal bus 16 after executing the user program. To transfer the output data stored in the work memory 14 to the transfer data memory 51a via the internal bus 16 and to transfer the input data stored in the transfer data memory 51a to the work memory 14 Transfer to.

After this transfer is completed, the MPU 11 sends a switching command to the bus switching circuit 51b to transfer data memory 51.
A command is issued to switch the connection destination of a from the internal bus 16 to the external bus 3, an operation start command is sent to the data transfer circuit 52 to notify the end of the I / O refresh processing of the MPU 11, and immediately after that the next cycle is started. Enter and try to run the user program again.

On the other hand, in the data transfer circuit 52, the MPU1
When the end notification of the I / O refresh process is received from 1,
The data memory 51a for transfer by the bus switching circuit 51b
Since the connection destination of is switched to the external bus 3, the output data stored in the transfer data memory 51a is transferred to the I / O unit 2 via the external bus 3, and
The input data taken in by the O unit 2 is transferred to the data transfer data memory 51a. Then, it waits for the next operation start command from the MPU 11.

Therefore, according to the first embodiment, the MPU
The user program execution process by the I / O unit 11 and the I / O refresh process by the data transfer circuit with the I / O unit 2 are processed in parallel, and the MPU 11 operates the I / O unit in the CPU unit 1.
Data memory 51a for transfer of / F circuit 15 and internal bus 1
I / O refresh via I / O 6, that is, exchange of input / output data is all that is required.
The I / O refresh cycle and the instruction execution cycle are shortened as compared with the case where the I / O refresh is performed with the O unit 2, and the instruction execution cycle is started even when the transfer data amount at the I / O refresh becomes large. Can reduce the effect of.

Here, as shown in FIG. 2, the MPU 11 does not perform I / O refresh with the transfer data memory 51a.
If it takes only 3 hours, according to this first embodiment,
The instruction execution cycle can be shortened by (t2-t3) time as compared with the conventional case.

Next, a second embodiment of the present invention will be described. The PLC of the second embodiment is similar to the first embodiment shown in FIG. 1 in terms of hardware configuration, but the system program is different from that of the first embodiment, and the MPU is of the first embodiment. Is configured to operate differently from.

That is, this second embodiment will be described later with reference to FIG.
As shown in FIG. 5, this is an embodiment in which the user program execution time t1 by the MPU is shorter than the data exchange time t2 by the data transfer circuit with the I / O unit. After the MPU executes the user program, it waits for a certain period of time. From I /
The I / O refresh is performed with the transfer data memory of the F circuit.

Next, the operation of the second embodiment will be described.
The configuration of the PLC will be described using the reference numerals of the PLC configuration of the first embodiment shown in FIG.

FIG. 3 shows the MPU 1 in the second embodiment.
1 shows a time chart of operations of 1 and the data transfer circuit 52.

In the second embodiment, since the user program execution time t1 is shorter than the data exchange time t2 with the I / O unit 2 by the data transfer circuit 52, the MPU 11
Waits for a certain time t4 after the execution of the user program and then sends a switching command to the bus switching circuit 52 to connect the transfer data memory 51a to the internal bus 16 and output data stored in the work memory 14, The input data stored in the transfer data memory 51a is transferred to the internal bus 1
Replace via 6.

After this input / output data exchange processing is completed, MP
U11 sends a switching command to the bus switching circuit 52 to switch the connection destination of the transfer data memory 51a from the internal bus 16 to the external bus 3, and also sends an operation start command to the data transfer circuit 52.

Upon receiving this operation start command, the data transfer circuit 52 transfers the output data stored in the transfer data memory 51a to the I / O unit 2 via the external bus 3 and the bus switching circuit 51b. And I
The input data is transferred from the / O unit 2 to the data transfer data memory 51a. Then, it waits for the next operation start command from the MPU 11.

Therefore, according to the second embodiment, as in the case of the first embodiment, the user program execution processing by the MPU 11 and the I / O refresh processing with the I / O unit 2 by the data transfer circuit are performed in parallel. Processed, MPU1
Since 1 only needs to exchange input / output data via the transfer data memory 51a of the I / F circuit 15 and the internal bus 16, the I / O unit 3 and I / O refresh are performed via the external bus 3. Compared to the case, the I / O refresh cycle and the instruction execution cycle are shortened, and the influence on the instruction execution cycle can be reduced even when the transfer data amount at the time of I / O refresh becomes large.

Here, according to the second embodiment, as shown in FIG. 3, the instruction execution cycle can be shortened by (t2− (t3 + t4)) as compared with the conventional case.

Next, a third embodiment of the present invention will be described. The PLC of the third embodiment is similar to the second embodiment and the first embodiment shown in FIG. 1 in terms of the hardware configuration, but the system program is different from that of the first and second embodiments. Therefore, the MPU is configured to operate differently from those of the first and second embodiments.

In other words, the third embodiment is an embodiment in which the user program execution time t1 by the MPU is longer than the data exchange time t2 by the data transfer circuit with the I / O unit, and when the MPU executes the user program. , Configured to use the latest input data.

Next, the operation of the third embodiment will be described.
The configuration of the PLC will be described using the reference numerals of the PLC configuration of the first embodiment shown in FIG.

FIG. 4 shows the MPU 1 in the third embodiment.
1 shows a time chart of operations of 1 and the data transfer circuit 52.

In the third embodiment, since the user program execution time t1 is longer than the data exchange time t2 with the I / O unit 2 by the data transfer circuit 52, the MPU 11
Immediately after the execution of the user program, the bus switching circuit 5
2, the transfer data memory 51 is connected to the internal bus 16, the output data stored in the work memory 14 is transferred to the transfer data memory 51a via the internal bus 16, and the transfer data is transferred. The input data stored in the memory 51a is transferred to the work memory 14. The processing up to this point is exactly the same as in the case of the first embodiment.

After this transfer is completed, the MPU 11 sends a switching command to the bus switching circuit 51b to transfer data memory 51.
The connection destination of a is switched from the internal bus 16 to the external bus 3, and then an operation start command is sent to the data transfer circuit 52, and immediately after that, the next cycle is entered to execute the user program again.

On the other hand, in the data transfer circuit 52, the MPU1
When the end notification of the I / O refresh process is received from 1,
The data memory 51a for transfer by the bus switching circuit 51b
Since the connection destination of has been switched to the external bus 3, first O
UT refresh, that is, data memory 51a for transfer
Output data stored in the I / O via the external bus 3.
Transfer to O unit 2.

After that, until the MPU 11 finishes executing the user program and starts the I / O refresh processing, IN refresh is repeated, that is, I / O.
The transfer of the input data from the unit 2 to the data transfer data memory 51a is repeated.

That is, in FIG. 4, the IN refresh is repeated only during the time t22, which is the user program execution time t1 by the MPU 11 excluding the OUT refresh time t21 by the data transfer circuit 52.

When the MPU 11 finishes executing the user program, the data transfer circuit 52 makes the IN
After the repetition of the refresh process, the MPU 11
Wait until the next operation start command comes from.

Therefore, according to the third embodiment, the user program execution processing by the MPU 11 and the I / O by the data transfer circuit are performed as in the first and second embodiments.
Since the I / O refresh process with the unit 2 is processed in parallel, and the MPU 11 only needs to exchange input / output data with the transfer data memory 51a in the CPU unit 1 via the internal bus 16, and therefore via the external bus 3. The I / O refresh cycle and the instruction execution cycle are shortened as compared with the case where the I / O unit 3 and the I / O refresh are performed, and the instruction is executed even when the transfer data amount at the time of the I / O refresh becomes large. The impact on the cycle can be reduced.

Here, according to the third embodiment, as in the case of the first embodiment shown in FIG. 2, if the MPU 11 requires t3 time for I / O refresh with the transfer data memory 51a, Conventionally, the instruction execution cycle can be shortened by (t2-t3) time.

Further, according to the third embodiment, the data transfer circuit 52 makes the MPU 11 after the OUT refresh processing.
Since the IN refresh is repeated until the I / O refresh process is performed by the MPU 11, when the MPU 11 performs the I / O refresh process, the latest input data is stored in the transfer data memory 51a, and the user program is executed in the next cycle. Sometimes the latest input data will be available.

In each of the first to third embodiments, as shown in FIG. 1, the transfer data storage unit 51 as the transfer data storage means is provided with a single-port transfer data memory 51a and a bus switching circuit. However, in the present invention, the transfer data storage unit 51 is configured by only the dual port memory, and the dual port memory is directly connected to both the internal bus 16 and the external bus 3 without a bus switching circuit. Connect and connect this dual port memory to M
Of course, both the PU 11 and the data transfer circuit 52 may be freely accessible.

[0049]

As described above, according to the present invention, CP
After the MPU in the U unit executes the user program,
The input / output data is exchanged with the transfer data storage means in the CPU unit, and then the user program is executed, while the data transfer means exchanges the input / output data with the MPU, and then the transfer data storage means and the I / O are exchanged. I / O data is exchanged with the unit, so MPU
The user program execution processing by the above and the input / output data exchange processing by the data transfer means with the I / O unit are processed in parallel.

Therefore, according to the present invention, the MPU does not need to directly exchange data with the I / O unit outside the CPU unit, and the I / O unit 3 is connected via the external bus.
And I / O refresh, the I / O refresh cycle and the instruction execution cycle are shortened, and even if the amount of transfer data at the time of I / O refresh becomes large, the influence on the instruction execution cycle is affected. Can be made smaller.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLC according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the MPU and the data transfer circuit in the first embodiment.

FIG. 3 is a time chart showing the operation of the MPU and the data transfer circuit in the second embodiment.

FIG. 4 is a time chart showing operations of an MPU and a data transfer circuit according to the third embodiment.

FIG. 5 is a time chart showing an instruction execution cycle in a conventional PLC.

[Explanation of symbols]

 1 CPU Unit 2 I / O Unit 3 External Bus 11 Microprocessor (MPU) 12 System Program Memory 13 User Program Memory 14 Work Memory (Execution Data Storage Means) 15 Interface (I / F) Circuit 51 Transfer Data Storage Unit ( Data storage means for transfer) 52 Data transfer circuit (data transfer means)

Claims (4)

[Claims] 1. A programmable controller in which a CPU unit and an I / O unit are connected by an external bus, the CPU unit being connected to a microprocessor and the microprocessor via an internal bus for executing a user program. The execution data storage means for storing input / output data is connected to the microprocessor and the execution data storage means via the internal bus, and is also connected to the I / O unit via the external bus to connect the CPU unit and the I / O unit. Output data stored in the execution data storage means after execution of the user program by the microprocessor, and data transfer means for storing input / output data transferred between the O units. Is transferred to the transfer data storage means and is stored in the transfer data storage means. While transferring the input data to the execution data storage means and then executing the user program, the data transfer means transfers the output data stored in the transfer data storage means after the input / output data is transferred by the microprocessor. I / O unit and I
/ O unit transfers input data taken in to a transfer data storage means. 2. The microprocessor transfers the output data stored in the execution data storage means to the transfer data storage means immediately after executing the user program, and
2. The programmable controller according to claim 1, wherein the input data stored in the transfer data storage means is transferred to the execution data storage means, and then the user program is executed. 3. The microprocessor transfers the output data stored in the execution data storage means to the transfer data storage means after a certain time has elapsed after the execution of the user program, and the microprocessor stores the output data in the transfer data storage means. The programmable controller according to claim 1, wherein the input data is transferred to the execution data storage unit, and then the user program is executed. 4. The microprocessor transfers the output data stored in the execution data storage means to the transfer data storage means immediately after executing the user program, and
The input data stored in the transfer data storage means is transferred to the execution data storage means and then the user program is executed, while the data transfer means transfers the input / output data by the microprocessor and then the transfer data storage means. The output data stored in the I / O unit is transferred to the I / O unit and
2. The programmable controller according to claim 1, wherein the transfer of the input data captured by the unit to the transfer data storage means is repeated until the microprocessor finishes executing the user program.