JP4037941B2 - Control device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a control device such as a programmable controller.
[0002]
[Prior art]
The programmable controller sequentially executes a plurality of instructions, and when all instructions have been executed, returns to the first instruction and repeats execution. In this way, near real-time control can be performed according to the state of external and internal relays, switches, and the like. Note that this one-cycle instruction execution is called a scan cycle.
[0003]
Incidentally, in recent years, a programmable controller 2 that can execute commands from peripheral devices such as an external computer and a display has been put into practical use. The system configuration is shown in FIG. Connected to the programmable controller 2 are an input device 4 such as a push button switch and a limit switch, and an output device 6 such as an electromagnetic switch and a relay. The programmable controller 2 reflects the state of the input device 4 in the memory, and controls the state of the output device 6 based on the state of the memory.
[0004]
The programmable controller 2 is also connected with peripheral devices 8 such as a computer and a display. The peripheral device 8 gives a write command to change the state of the memory, for example, to the programmable controller 2. In the scan cycle, the programmable controller 2 receiving this stores the write command in the memory. Thereafter, at the end of the scan cycle, the write command recorded in the memory is executed.
[0005]
Thereby, regardless of the actual state of the input device 4, the programmable controller 2 can be operated assuming that the input device 4 is in a predetermined state.
[0006]
[Problems to be solved by the invention]
However, the conventional control apparatus as described above has the following problems.
[0007]
First, the conventional control apparatus can receive only one command from the outside in one scan cycle. If two or more instructions are given within one scan cycle, the instructions given after the second are not executed and are ignored. Therefore, in order to perform a job composed of a plurality of instructions, at least as many scan cycles as the number of the instructions are required. In other words, the execution of external instructions has not been quick.
[0008]
Secondly, the conventional control device cannot properly execute a command received from a plurality of peripheral devices.
[0009]
The present invention solves the above-described problems, and appropriately receives a command from a plurality of connected peripheral devices and a control device that can be executed in response to a plurality of external commands within one scan cycle. An object of the present invention is to provide a control device that can be executed.
[0012]
[Means for Solving the Problems]
In the control device of the present invention, the number of instructions that can be received within one scan cycle is determined for each port, and instructions exceeding the number of instructions that can be received are given to one port within one scan cycle. If the command is received, the fact that the command cannot be received is returned.
[0015]
【The invention's effect】
In the control device of the present invention, the number of instructions that can be received within one scan cycle is determined for each port, and instructions exceeding the number of instructions that can be received are given to one port within one scan cycle. If the command is received, the fact that the command cannot be received is returned. As a result, the external device that has given the command can give the command again and execute the command reliably in a later scan cycle. In addition, it is possible to avoid a situation in which execution of external instructions is occupied by one port and the instruction execution balance with other ports is lacking.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a configuration of a programmable controller according to an embodiment of the present invention. Connected to the CPU 10 are a system program memory 12, a sequence program memory 14, an auxiliary memory 16, an I / O interface 18, and ports P1, P2,... Pn. Devices such as an input relay, an output relay, and a switch are connected to the I / O interface 18.
[0017]
Peripheral devices such as a computer and a display for giving commands from the outside are connected to the ports P1 to Pn, respectively.
[0018]
The sequence program memory 14 is provided with a storage unit that holds a storage state corresponding to the state of these external devices. The storage unit is also provided with a location indicating the state of the internal relay. Further, the sequence program memory 14 stores a sequence program created by the user.
[0019]
The system program memory 12 stores a system program that controls basic operations of the programmable controller.
[0020]
The auxiliary memory 16 serving as an external command storage means stores commands from the ports P1 to Pn.
[0021]
Hereinafter, a case where an external command as shown in FIG. 2 is given to the sequence controller via the ports P1 and P2 will be described as an example. FIG. 3A shows the format of the external instruction. Following the first header, the operation type, target device, data, and terminator are given. The header indicates the start and the terminator indicates the end. The operation type indicates the type of operation such as data clear and write. The target device indicates a device (input, output, internal relay, data register, or the like) that is a target for performing the operation. Data indicates data to be operated.
[0022]
For example, the batch data clear command has a configuration as shown in FIG. 3B. In the case of a data clear command, data to be operated is not necessary. The start control relay ON command has a configuration as shown in FIG. 3C. The target device is designated by its type (m, internal relay) and the corresponding address (300) in the memory.
[0023]
FIG. 4 shows a flowchart of the system program stored in the memory 12. First, in step S1, the content of the address in the memory 14 corresponding to the output device (such as an output relay connected to the interface 18) is read, and the output device is controlled based on this content.
[0024]
Next, the state of the input device (such as a switch connected to the interface 18) is obtained, and the content of the address of the corresponding memory 14 is rewritten according to this state (step S2).
[0025]
Thereafter, the first step of the user program stored in the memory 14 is executed (step S3). When this is finished, the next step is executed (step S4). This is repeated until the last step of the user program is executed (step S5).
[0026]
When an external command is given from one of the ports P1 to Pn as shown in FIG. 2 during the execution of the above steps S1 to S5, the external command is stored in the auxiliary memory 16 by interrupt processing.
[0027]
When the execution of the user program is completed in this way, the instruction stored in the auxiliary memory 16 is executed (step S6). Thereby, an instruction given from the outside can be executed at the end of one scan cycle.
[0028]
When the instruction stored in the auxiliary memory 16 is executed (that is, when one scan cycle is completed), the execution of step S1 and subsequent steps is repeated again.
[0029]
FIG. 5 shows a flowchart of interrupt processing for storing an external command in the auxiliary memory 16. First, in step S10, the number of instructions m given so far for a port to which an external instruction is given.
To get. The auxiliary memory 16 stores instructions from the ports P1 to Pn in a data structure as shown in FIG. Therefore, it is possible to easily obtain the instruction number m given so far for the port.
[0030]
As shown in FIG. 2, when an external command is given, first, the interrupt processing of FIG. 5 is executed by a batch data clear command given to the port P1. Note that interrupt processing is performed in the order of the time when the external instruction is completely given (in the order of t1, t2, and t3). Since this scan cycle has started and no instruction has been given to the port P1, the number m of acquired instructions is zero.
[0031]
Next, in step S11, it is determined whether or not the instruction number m of the port P1 is smaller than the maximum instruction possible number. If it is smaller, the total number k of instructions through all ports (the total number of instructions m at each port) is incremented by one (step S12). This instruction total number k is stored in the auxiliary memory of FIG. Here, the total number of instructions k is 1.
[0032]
Next, the instruction total number k is set as the order of the instructions (step S13). The order in which these instructions are given is also stored in the auxiliary memory (see FIG. 6). Subsequently, the instruction number m of the port (here, port P1) is incremented by one (step S14). The number of instructions is recorded in the auxiliary memory (see FIG. 6). Here, the instruction number m is 1, and is stored as the instruction number m from the port P1.
[0033]
Next, an external command is interpreted to obtain write data and an address (step S15). The batch data clear instruction has a format as shown in FIG. 3B. This instruction is interpreted to determine which data (ie, device) should be written with which data. That is, it interprets what data the external instruction requests to write to which address of the memory 14. For example, in the collective data clear command of FIG. 3B, the target addresses are all addresses corresponding to the input device, output device, and internal device (internal relay, etc.). The write data is “0”. The address and write data thus obtained are stored in the auxiliary memory (see FIG. 6).
[0034]
In the same manner as described above, the interrupt processing of FIG. 5 is also performed for the start control OFF command and the start control ON command of FIG.
[0035]
In step S11 in FIG. 5, when the number of instructions m is equal to the number of instructions that can be received by the port (maximum number of instructions that can be received), the fact that the instruction cannot be received is returned via the port. (Step S16). The maximum number of instructions that can be commanded is set in advance. In this way, it is possible to avoid a situation in which execution of an external instruction is occupied by one port and the instruction execution balance with other ports is lacking.
[0036]
As described above, the auxiliary memory 16 (command storage unit) stores the total number k of commands from all ports and the command information of each port, as shown in FIG. The instruction information of each port stores the order in which instructions through all the ports are given, and the contents of the instructions (write data, address).
[0037]
FIG. 7 shows specific contents stored in the auxiliary memory when an external command is given as shown in FIG. In this embodiment, the external command is interpreted to store the address and the write data, but the external command may be stored as it is.
[0038]
Next, execution of the external instruction stored in this way (step S6 in FIG. 4) will be described. The flowchart is shown in FIG. Here, description will be made assuming that an external command is stored as shown in FIG.
[0039]
First, in steps S20 and S21, the processing counter q is set to 1, and the port counter n is set to 1. Next, the instruction counter j is set to 0 (step S22).
Next, for the port indicated by the port counter n, the number m of stored instructions and the order of instructions stored first are acquired (step S23). Here, the number of instructions m = 2 and order = 1 are acquired. In step S24, it is determined whether or not the instruction counter j is equal to the instruction number m. Here, since j = 0 and m = 2 and they are not equal, the process proceeds to step S25. In step S25, the instruction counter j is incremented by one. As a result, j = 1.
[0040]
Next, it is determined whether or not the acquired order is equal to the processing counter q (step S26). Here, since the order = 1 and q = 1 are equal, the instruction recorded with the order = “1” is executed (step S27). That is, data “0” is written to all addresses, and a batch data clear command is executed.
[0041]
Thereafter, it is determined whether or not q is equal to the total number k of instructions from all ports. If they are equal, this process is terminated (step S28). Here, since k = 3 and q = 1, q is incremented by 1 in step S28 (step S29). As a result, q = 2, and step S22 and subsequent steps are executed again. As a result, the instruction having the second order is executed.
[0042]
First, the instruction counter j is set to 0 (step S22). Next, the number of instructions m and the order are acquired (step S23). Now, since the port counter n = 1, the number of instructions m = 2 and the order = 1 are acquired. Further, in step S24, it is determined whether or not the instruction counter j is equal to the instruction number m. Here, since the instruction counter j = 0 and the number of instructions m = 2, the process proceeds to step S25, and the instruction counter j is incremented by one. As a result, the instruction counter j = 1.
[0043]
Next, it is determined whether or not the processing counter q is equal to the order (step S26). Here, since q = 2 and order = 1, the process returns to step S23.
[0044]
In step S23, the order of the next stored instruction is acquired. Here, order = 3 is acquired (see FIG. 7). Thereafter, step S24, step S25, and step S26 are executed in this order. In step S26, since q = 2 and order = 3, the process returns to step S23 again. In step S24, the instruction counter j (= 2) is equal to the instruction number m (= 2), so the process proceeds to step S30.
[0045]
In step S30, it is determined whether or not the port counter n is equal to the total number of ports (here, 2). Here, since the port counter n = 1 and the total number of ports = 2, the process proceeds to step S31. In step S31, the port counter n is incremented by one. Thereafter, step S22 and subsequent steps are executed. In this way, the same processing is performed for the port P2. As a result, in step S26, the processing counter q = 2 and the order = 2, and the start control relay OFF command of FIG. 7 is executed in step S27. That is, data “0” is written to the address 300.
[0046]
Thereafter, the same processing is performed with the processing counter q = 3, and the start control ON command of FIG. 7 is executed. That is, data “1” is written to the address 300.
[0047]
As described above, external instructions can be executed in the given order. In particular, as shown in FIG. 2, when an OFF command and an ON command are given, the execution order is important. This is because if this order is reversed, the final relay ON / OFF changes. In this regard, according to the above-described embodiment, instructions are executed in the order given, and appropriate processing is possible.
[0048]
In the above embodiment, the case of having a plurality of ports P1 to Pn has been described. However, the present invention can be applied to the case of having one port. In this case, even if a plurality of instructions are given from one port within one scan cycle, the instructions can be executed in the given order.
[0049]
Further, in the above embodiment, instructions are stored together for each port. This is because the program can be simplified if the processing is summarized for each port. However, in some cases, the instructions may be stored by assigning port numbers according to the order in which the instructions are given.
[0050]
In the above embodiment, an instruction for writing is shown as an external instruction, but an external instruction for performing one scan cycle end processing can also be targeted.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a programmable controller according to an embodiment of the present invention.
FIG. 2 is a diagram showing the timing of an external instruction given to a port.
FIG. 3 is a diagram illustrating a format and an example of an external instruction.
FIG. 4 is a flowchart showing processing of a system program.
FIG. 5 is a flowchart showing processing when an external command is received.
FIG. 6 is a diagram illustrating a data structure of data (external command) stored in an auxiliary memory.
FIG. 7 is a diagram illustrating an example of data of an external command stored in an auxiliary memory.
FIG. 8 is a flowchart showing execution processing of instructions stored in the auxiliary memory.
FIG. 9 is a diagram illustrating a conventional programmable controller.
[Explanation of symbols]
P1 to Pn ... Port 10 ... CPU
12 ... System program memory 14 ... Sequence program memory 16 ... Auxiliary memory 18 ... I / O interface

Claims (1)

In a control device that performs control by repeatedly executing a program in a scan cycle,
At least one port for receiving instructions from the outside,
An external instruction storage means for storing instructions given through the port together with a given order within one scan cycle;
External instruction execution means for executing instructions stored in the external instruction storage means in accordance with a given order at the end of one scan cycle;
For each port, determine the number of instructions that can be received within one scan cycle,
If an instruction exceeding the number of instructions that can be received is given to one port within one scan cycle, a message indicating that the instruction cannot be received is returned.
A control device characterized by that.

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