JP5088566B2 - PLC with interrupt function - Google Patents

Description

  The present invention relates to a programmable controller (hereinafter referred to as “PLC”) having an interrupt function such as an I / O interrupt, a power interruption interrupt, and a scheduled interrupt.

  The PLC includes an all-in-one type in which various device components such as a power supply unit, an input / output processing unit, an arithmetic processing unit, various special arithmetic processing units, etc. are accommodated in one housing, There is a building block type in which each processing unit is housed in a separate housing.

  As an example of the arithmetic processing unit, a CPU unit of a building block type PLC is shown in FIG. The CPU unit 1 is connected to a power supply unit, an input / output unit, other special arithmetic units, and the like (not shown) via an internal bus 10 laid on a so-called backplane.

  As shown in the figure, the CPU unit 1 includes a user program memory (UM) 11, an input / output memory (IOM) 12, a data storage nonvolatile memory 13, a dedicated IC 14, a microprocessor (MPU) 15, and a system. A program memory (ROM) 16 and a work memory (work RAM) 17 are included.

  In the user program memory 11, a user program that is executed as one or more cycle execution tasks corresponding to a desired control specification and a user program that is executed as one or more interrupt execution tasks are predetermined. It is written in a user program language and stored in a state that can be executed by the dedicated IC 14.

  The input / output memory 12 is provided with an input data area and an output data area. The input data area stores input data corresponding to an input signal of an external input terminal array (not shown), and the output data area is shown in the figure. The output data corresponding to the output signal of the external output terminal row not to be stored is stored.

  The data storage nonvolatile memory 13 stores various setting data necessary for arithmetic processing and the like, an abnormality notification setting, an abnormality status, and the like.

  The dedicated IC 14 incorporates a program execution function for executing a user program described in a predetermined user program language.

  The microprocessor 15 implements various functions as a PLC by executing various system programs described in a microprocessor language. As typical ones of these functions, an input update process for reading input data from an external input terminal row of an input / output unit (not shown) through an input circuit and writing it in an input data area of the input / output memory 12, and input / output An output update process for sending output data stored in the output data area of the memory 12 to the outside from an external output terminal row via an output circuit of an input / output unit (not shown), and a user program memory under the intervention of the dedicated IC 14 Data is transmitted via communication between the instruction execution process that sequentially reads and executes each instruction word constituting the user program from 11 and other PLC, remote input / output terminal, or program development support device (tool device), etc. Peripheral service processing that exchanges

  The microprocessor 15 controls the control target according to the user program by controlling the input update process, the output update process, the instruction execution process, the peripheral service process, and the like to be repeatedly executed. The time required for one iteration at the time of repeated execution is called a cycle time.

  In the system program memory 16, a system program necessary for the microprocessor 15 to realize the above functions (input update processing, output update processing, instruction execution processing, peripheral service processing, etc.) is stored in a predetermined microprocessor language. And stored in a state executable by the microprocessor 15.

  The work memory 17 is used as a work area when the microprocessor 15 reads and executes the system program from the system program memory 16.

  The above PLC can accept various interrupt factors such as I / O interrupts, power interruption interrupts, scheduled interrupts, etc., and when those interrupt factors are accepted, Interrupt processing is executed according to the operation procedure.

  FIG. 10 is a flowchart showing an operation procedure of interrupt processing in the conventional CPU unit. As shown in the figure, the entire interrupt process is performed by the preceding process A (steps 201 to 203) entrusted to the MPU process (meaning the process executed by the MPU) and the dedicated IC process (executed by the dedicated IC). Main body processing B (step 204) entrusted to MPU processing and post-processing C (steps 205 to 207) entrusted to MPU processing.

  In this example, the pre-stage process A includes an interrupt prohibition process (step 201), a register save process (step 202), and an interrupt program execution pre-process (step 203). Further, the post-stage process C includes an interrupt program execution post-process (step 205), a register restoration process (step 206), and an interrupt release process (step 207).

  More specifically, as shown in FIG. 9, the I / O interrupt signal and the power interruption interrupt signal (IT1) are received by the dedicated IC 14 via the interrupt line included in the internal bus. Then, the dedicated IC 14 passes these interrupt signals to the interrupt input terminal of the microprocessor 15 in order to entrust the execution of the pre-process A (steps 201 to 203) to the microprocessor 15. When the execution of the pre-stage process A (steps 201 to 203) is completed, the microprocessor 15 passes the program execution right to the dedicated IC 14 in order to entrust the execution of the main body process B (step 204) to the dedicated IC 14. When the execution of the main body process B (step 204) is completed, the dedicated IC 14 passes the program execution right to the microprocessor 15 in order to again leave the execution of the subsequent process C (steps 205 to 207) to the microprocessor 15.

  As a result of the series of processes shown in the flowchart of FIG. 10 being executed in this way, as shown in FIG. 11, the user programs UP1-1 and UP1-2 are always set to cycle execution tasks (cyclically). When an I / O interrupt, scheduled interrupt, or power interruption interrupt occurs, the execution of the user program UP1-2 being executed as a cycle execution task is interrupted. Instead, the user program UP2 is executed as an interrupt execution task (meaning of a task executed in the interrupt process), and after the execution of the user program UP2 is completed, the cycle is executed before the interrupt. A series of operations such as returning to the user program UP1-2 being executed as a task is automatically executed. Thus, the user program which is a control program created by the user is executed as the above-described cycle execution task or the above-described interrupt execution task.

  By the way, in the user programs UP1-1 and UP1-2 executed as the above-mentioned cycle execution task and the user program UP2 executed as the interrupt execution task, the arithmetic register group operated during the execution of the program is the both user programs. It is customary to have some overlap between them.

  Therefore, the execution target program is switched from a user program executed as a cycle execution task to a user program executed as an interrupt execution task, or conversely, a cycle execution is executed from a user program executed as an interrupt execution task. When switching the execution target program to a certain user program executed as a task, the data (stored contents) of the register group shared between the two programs cannot be taken over as it is before and after the switching.

  As described above, in the field of information processing apparatuses having a large-capacity memory such as a personal computer when mutual switching of execution target programs is required between two or more programs that are independent of each other and partially use an arithmetic register. In general, a memory area called “bank” is allocated to each program, and necessary register groups are allocated to each program. When it is necessary to switch the execution target program, the register groups are grouped in units of banks. The method of switching (hereinafter referred to as “bank switching method”) is employed.

  According to such a bank switching method, when performing mutual switching of execution target programs between two or more programs that are independent of each other and partially use the arithmetic registers, the register group is switched in a bank unit. Therefore, there is an advantage that execution can be instantaneously transferred between programs.

  However, in the case of a control device that can hold only a relatively small amount of memory, such as a PLC, unlike the information processing device that has a large-capacity memory such as the above-mentioned personal computer, a register for each user program. Since it is difficult to assign a bank for group placement, the bank switching method cannot be adopted when switching the execution target program.

  Therefore, conventionally, when switching execution target programs between a user program serving as a cycle execution task and a user program serving as an interrupt execution task in a PLC, the arithmetic registers are themselves shared, For the data (stored contents) of the register group, a method (hereinafter referred to as “nesting method”) that saves to a predetermined storage area (stack) or restores from a predetermined storage area (stack) is adopted (hereinafter referred to as “nesting method”). For example, see Patent Document 1). In the example of FIG. 10, the register saving process (step 202) that constitutes the pre-stage process and the register restoration process (step 206) that constitutes the post-stage process correspond to the process for realizing the nesting method.

According to a PLC employing such a nesting method, even if only a relatively small amount of memory can be held, it is possible to smoothly switch the execution target program while avoiding data interference between programs. .
Japanese Patent Laid-Open No. 4-205031

  In a conventional PLC that employs a nesting method when switching an execution target program between a user program that is a cycle execution task and a user program that is an interrupt execution task, all arithmetic registers in the system or A register save process and a register restore process are executed for all arithmetic registers that may be shared among a plurality of user programs.

  However, in such a conventional PLC, all the arithmetic registers that may be shared among a plurality of user programs are at least a few hundred, so register saving processing and register restoring processing It takes a considerable amount of time, and the time required from interrupt start to interrupt return increases accordingly. As a result, a problem has been pointed out that the cycle execution task side is greatly affected by the interrupt processing for executing the interrupt execution task.

  Here, the effect on the cycle execution task side is that the execution accuracy of the cycle execution task is poor due to the input data being missed due to the delay of the input update process or the output delay of the output data due to the increase of the cycle time That is.

  The present invention has been made paying attention to such conventional problems, and the object of the invention is an interrupt function capable of shortening the time required from interrupt start to interrupt return as much as possible. It is providing the PLC provided with.

  Other objects and operational effects of the present invention will be easily understood by those skilled in the art by referring to the following description of the specification.

  It is considered that the above technical problem can be solved by a PLC having an interrupt function having the following configuration.

  That is, the PLC having this interrupt function performs at least a register saving process for saving the data stored in the arithmetic register to a predetermined memory area before executing the user program executed as the interrupt execution task. A register that restores the contents of the operation register by restoring the data saved in a predetermined memory area after execution of the user program executed as an interrupt execution task. Subsequent processing including at least restoration processing is executed.

  In addition, the PLC includes an operation target register specifying means for arbitrarily specifying a register storing data to be saved in the register saving process and to be restored in the register restoring process, When executing the user program, save / restore execution means for executing register save processing and register restore processing is provided only for the arithmetic register designated by the operation target register designation means.

  According to the PLC having such a configuration, when executing the interrupt user program, the register saving process and the register restoring process are executed only for the operation register designated by the operation target register designating unit. As long as only the operation registers that are actually manipulated by the interrupt processing are specified in advance by the operation target register specifying means, the time required for register save processing and register restoration processing is minimized, and interrupts are started from the start of the interrupt. The time required to return can be shortened as much as possible.

  In a preferred embodiment of the PLC according to the present invention, the operation target register designating unit includes an operation target registration register for preregistering data for designating a register to be operated, and save / restore execution unit However, the register saving process and the register restoring process are executed only for the arithmetic register designated by the data registered in the operation target register.

  According to such a configuration, as long as only the arithmetic register actually operated by the interrupt processing is registered in the operation target registration register, it is possible to interrupt without particularly giving a special instruction in the user program. If an interrupt factor occurs, the register save process and the register restore process are executed only for the register registered as the operation target, so if the selection of the operation target register to be registered is reliable, the interrupt starts. It is also possible to minimize the time required for the return from interruption to interruption.

  At this time, the saving / restoring execution means receives the saving operation instruction to which a predetermined instruction code is assigned and the data registered in the operation target registration register in response to the decoding of the saving operation instruction in the user program. Only for the arithmetic register specified in (2), the save operation instruction execution means for executing the register save processing, the restore operation instruction to which a predetermined instruction code is assigned, and the restore operation instruction are decoded in the user program. In response, a restore operation instruction execution means for executing register restore processing may be included only for the operation register specified by the data registered in the operation target registration register.

  According to such a configuration, by arranging the save operation instruction and the restore operation instruction at an appropriate position in the user program, the save timing, restore timing, etc. regarding the operation register registered in the operation target registration register can be changed from time to time. Therefore, if this function is used, if the time required for interrupt processing is not a problem, for example, as before, save and restore operations are performed for the majority of registers. In particular, only for situations where the time required for interrupt processing is a problem, save and restore operations are performed by placing save and restore operation commands at appropriate positions in the user program. By limiting the operation registers to those registered in the operation target registration register, the time required for interrupt processing can be minimized. Kill.

  In another preferred embodiment of the PLC according to the present invention, the operation target register designating means is assigned a predetermined instruction code, and an operand is a calculation register to be saved in the register saving process. A save operation instruction with an operation target specification that describes the data to be specified and a predetermined instruction code are assigned, and the operand specifies the operation register to be saved in the register save process In response to the evacuation operation instruction with the operation target designation being decoded in the user program, the save / restore execution means includes a evacuation operation instruction with the operation target specification in which data for operation is described. Save operation instruction execution that executes register save processing only for the operation register specified by the data described in the operand of the instruction In response to the decryption operation instruction with operation target designation being decoded in the user program, the register restoration processing is executed only for the operation register designated by the data described in the operand of the instruction. And a restoration operation command execution means.

  According to such a configuration, the evacuation operation instruction with operation target designation and the restoration operation instruction with operation object designation are arranged at appropriate positions in the user program, so that the evacuation timing, restoration timing, etc. can be controlled from time to time. In addition to being able to arbitrarily associate with the situation, the save instruction and the restore instruction itself can specify the register to be saved or restored, so if this function is used, for example, a pair can be saved between the save and restore. The number of operation registers to be saved and restored regardless of the type of interrupt factor by providing operation instruction pairs for each interrupt factor and making the contents of the operation target registers attached to them different. To minimize the time required from the start to the return for each interrupt process corresponding to each interrupt factor. Kill.

  According to the present invention, when executing the user program executed as the interrupt execution task, the register saving process and the register restoring process are executed only for the operation register specified by the operation target register specifying means. If only the operation registers that are actually manipulated by the interrupt processing are specified in advance by the operation target register specifying means, the time required for register save processing and register restore processing is minimized, and the interrupt is restored from the interrupt start. The time required to reach as low as possible.

  Hereinafter, a preferred embodiment of a PLC having an interrupt function according to the present invention will be described in detail with reference to the accompanying drawings.

  A hardware configuration diagram of a PLC CPU unit according to the present invention is shown in FIG. As shown in the figure, the CPU unit 1 includes a user program memory (UM) 11, an input / output memory (IOM) 12, a data storage nonvolatile memory 13, a dedicated IC 14, a microprocessor (like the conventional example). MPU) 15, system program memory (ROM) 16, and work memory (work RAM) 17.

  In the user program memory 11, a user program that is executed as one or more cycle execution tasks corresponding to a desired control specification and a user program that is executed as one or more interrupt execution tasks are predetermined. Stored in a state described in the user program language. The user program memory 11 also stores user programs for the dedicated IC 14 to execute the pre-stage process A and the post-stage process C, as will be described later.

  The data storage non-volatile memory 13 stores various setting data necessary for arithmetic processing and the like, an abnormality notification setting, an abnormality status, and the like.

  The dedicated IC 14 incorporates a program execution function for executing a user program described in a predetermined user program language. By executing various user programs stored in the user program memory 11 by this program execution function, the functions of the cycle execution task and the interrupt execution task described above are realized. In addition, in this example, the above-described pre-stage process A and post-stage process C are configured to be realized by a dedicated IC instead of a microprocessor as in the prior art.

  The microprocessor 15 implements various functions as a PLC by executing various system programs described in a processor language. As typical ones of these functions, an input update process for reading input data from an external input terminal row of an input / output unit (not shown) through an input circuit and writing it in an input data area of the input / output memory 12, and input / output By updating output data stored in the output data area of the memory 12 from the external output terminal array to the outside via an output circuit of an input / output unit (not shown), and entrusting the program execution right to the dedicated IC 14 Through communication between the instruction execution process for causing the dedicated IC 14 to execute each instruction word constituting the user program and another PLC, a remote input / output terminal, or a program development support apparatus (also referred to as a tool apparatus or the like) For example, peripheral service processing for exchanging data. The microprocessor 15 controls the control target according to the user program by controlling the input update process, the output update process, the instruction execution process, the peripheral service process, and the like to be repeatedly executed.

  In the system program memory 16, a system program necessary for the microprocessor 15 to execute the above processes (input update process, output update process, instruction execution process, peripheral service process, etc.) is stored in a predetermined microprocessor language. Is stored in the state described.

  The work memory 17 is used as a work area when the microprocessor 15 reads and executes the system program from the system program memory 16.

  The PLC (CPU unit 1) described above can accept various interrupt factors such as I / O interrupts, power interruption interrupts, scheduled interrupts, etc., and these interrupt factors are accepted. When interrupted, an interrupt process is executed according to a predetermined operation procedure.

  FIG. 2 shows a flowchart showing the operation procedure of the interrupt process in the CPU unit of the PLC according to the present invention. As shown in the figure, the entire interrupt process is composed of a pre-process A (steps 101 to 103), a main process B (step 104), and a post-process C (steps 105 to 107). . And especially in this example, those processes A to C are all entrusted to a dedicated IC process.

  In this example, the pre-stage process A includes an interrupt prohibition process (step 101), a register save process (step 102), and an interrupt program execution preprocess (step 103).

  The main body process B should be a main part for realizing the interrupt execution task, and the interrupt program execution process (step for executing the user program for the interrupt execution task corresponding to the interrupt factor at that time) 104).

  The post-stage process C includes an interrupt program execution post-process (step 105), a register restoration process (step 106), and an interrupt prohibition release process (step 107).

  Then, among the above-described processes, the “save” which is the main part of the present invention is performed by the register save process included in the pre-stage process A (step 102) and the register restore process included in the post-stage process C (step 106). The function of “restore execution means” will be realized.

  More specifically, referring back to FIG. 1, the I / O interrupt signal and the power interruption interrupt signal (IT1) are received by the dedicated IC 14 via the interrupt line included in the internal bus 10. Then, the dedicated IC 14 reads the corresponding program from the user program memory (UM) 11 and executes it, thereby executing the pre-stage process A (steps 101 to 103), the main body process B (step 104), and the post-stage process C (step 105 to 105). 107) are executed sequentially.

  Next, “operation target register designating means” and “save / restore execution means” which are the main parts of the present invention will be described. As described above, the CPU unit 1 has an arithmetic register storing data to be saved in the register saving process (step 102) and to be restored in the register restoring process (step 106). When the interrupt target user program is executed by the dedicated IC 14 and the operation register specified by the operation target register specifying means, the register save processing (step 102) and “restoration / restoration execution means” for executing the register restoration processing (step 106). Each function of these means (“operation target register specifying means” and “save / restore execution means”) can be specifically realized by various methods. In the following description, three methods including the first method to the third method are shown.

  An explanatory diagram (part 1) of the save / restore operation in the first method is shown in FIG. 3, and an explanatory diagram (part 2) thereof is shown in FIG.

  In order to realize the first method, an operation target registration register shown in FIG. 6 is prepared. Where to prepare the operation target registration register is a system design matter, and can be provided in, for example, the dedicated IC 14.

  As shown in FIG. 6, the operation target registration register (RG) is an example of a 16-bit register. Bit 0 is a register A designation area, bit 1 is a register B designation area, bit 2 is a register C designation area, bit 3 is a register D designation area, bit 4 is a register E designation area, bit 5 is a register F designation area, etc. Sixteen register designation areas are allocated to sixteen bits. When the value of the register designation area is “1”, it indicates that the contents (data) of the register corresponding to the area needs to be saved / restored. Further, when the value of the register designation area is “0”, it indicates that it is not necessary to save / restore the contents (data) of the register corresponding to the area. In this example, bit 0 and bit 1 are “1” and the others are “0”, indicating that registers A and B are registers that need to be saved / restored. In order to set the value of this register designation area to “0” or “1”, for example, a program development support apparatus (not shown) is connected to the CPU unit, and the dedicated in the CPU unit is in accordance with an instruction from the program development support apparatus. What is necessary is just to comprise so that a predetermined value may be written in the operation object registration register (RG) provided in IC14. In this example, since the operation target registration register (RG) is composed of a 16-bit register, the number of registers that can be designated as operation targets for saving / restoring is up to 16. In order to make all the operation registers the operation target for saving / restoring, the operation object registration register (RG) may be configured so that the number of bits corresponding to the number of all operation registers can be allocated. For example, a plurality of 16-bit registers may be used, or a plurality of 32-bit registers may be used.

  On the other hand, in the register saving process (step 102) and the register restoring process (step 106) shown in the flowchart of FIG. 2, the value of the register designation area of the operation target registration register (RG) shown in FIG. A function for saving and restoring only a certain register is incorporated. In order to realize these selective save processing and restoration processing, a user program for realizing such a processing procedure is placed in a predetermined area in the user program memory (UM) 11 on the manufacturer side or the vendor side. Should be stored in advance.

  FIG. 3 shows an example in which the register designation area from bit 0 to bit 5 of the operation target registration register (RG) in FIG. 6 is “1”. Specifically, the save / restore operation is shown in the case where six registers from register A corresponding to bit 0 to register F corresponding to bit 5 are designated as registers that need to be saved / restored.

  As shown in FIG. 9A, in the operation at the time of saving, regarding the registered registers (register A to register F), the data stored in these registers is the input / output memory (IOM) 12. It is stored (pushed) into the stack area (MA) provided in the inside. Further, as shown in FIG. 5B, in the operation at the time of restoration, regarding the registered registers (register A to register F), stack areas (in the I / O memory (IOM) 12) ( Each data is read (popped) from MA), and the read data is stored in the original registers (register A to register F), and the restoring operation is completed.

  FIG. 4 shows an example in which the register designation areas of bit 0, bit 2 and bit 4 of the operation target registration register (RG) in FIG. 6 are “1” and the other register designation areas are “0”. ing. Specifically, the save / restore when three registers, register A corresponding to bit 0, register C corresponding to bit 2, and register E corresponding to register 4, are designated as registers that need to be saved / restored. The restore operation is shown.

  As shown in FIG. 5A, in the operation at the time of saving, only the data stored in the registers A, C, and E are stored (pushed) into the stack area (MA), and the saving operation is performed. Is completed. In this case, each data stored in the register B, the register D, and the register F is maintained without being saved. Further, as shown in FIG. 5B, in the operation at the time of restoration, the corresponding data is read (popped) from the stack area (MA), and each read data corresponds. Returning to the registers (register A, register C, register E), the restoration operation is completed.

  As described above, according to the first method, the value of the bit position corresponding to the register (operation target register) that needs to be saved / restored in advance in the operation target registration register RG is selectively set to “1”. Saving / restoring operation can be realized. Therefore, as long as only the operation registers that are actually operated by the interrupt processing are registered in the operation target registration register in advance as the operation target registers, interrupts can be generated without giving special instructions in the user program. If a factor occurs, the register saving process (step 102) and the register restoration process (step 106) are executed only for the register registered as the operation target register, so that the selection of the operation target register to be registered is certain. As long as this is done, it is possible to minimize the time required from interrupt start to interrupt return.

  An explanatory diagram of the save / restore operation in the second method is shown in FIG. In the first method, the save process and the restore process are unconditionally executed for the register registered as the operation target register in the operation target registration register RG. However, in this second method, the save operation instruction The OP11 and the restore operation instruction OP12 are newly defined, and only when the instructions OP11 and OP12 are executed, the selective save process and restore process based on the registered contents of the operation target registration register RG are executed. I have to.

  In order to define such a save operation instruction OP11 and a restore operation instruction OP12, execution programs corresponding to these instructions are stored in the user program memory (UM) 11 in a state described in the user program language. . These instruction execution programs may be installed in advance in a predetermined area of the user program memory (UM) 11 on the manufacturer side or the vendor side. On the user side, the above-described selective save processing and restoration are performed by inserting the save operation instruction OP11 and the restore operation instruction OP12 at an arbitrary program position so as to be executed under a desired condition. Processing can be realized.

  That is, as shown in FIG. 9A, in the operation at the time of retraction, a predetermined input condition (indicated by an input contact symbol on the ladder diagram) is satisfied and the retraction operation instruction OP11 is executed. As a result, only the registers (register A, register C, register E) registered in advance as operation target registers are stored (pushed) into the stack area (MA). Further, as shown in FIG. 6B, a predetermined input condition (indicated by an input contact symbol on the ladder diagram in the figure) is satisfied, and the restoration operation instruction OP12 is executed by the dedicated IC 14, and as a result, the stack Data is read (popped) from the area (MA), and each read data is returned to the corresponding original register (register A, register C, register E), and the restoration operation is completed.

  As described above, according to the second method, only when the save operation instruction OP11 and the restore operation instruction OP12 described in the user program are decoded and executed, the selective operation based on the registered contents of the operation target registration register RG is performed. Since the save process and the restore process are executed, for example, when these instructions OP11 and OP12 are not executed, the save process and the restore process are executed for all the registers (register A to register F) as before. If the selective save process and restore process based on the registered contents of the operation target registration register RG are executed only when the save operation instruction OP11 and the restore operation instruction OP12 are decoded and used, Depending on the type and nature of the interrupt program being executed, or depending on the control status at that time, Bear in essential minimum, Thus, more have flexibility, and the time required to reach the interrupt return from the interrupt start can be the shortest.

  In the first method and the second method described above, the operation target registration register RG has been described as common for all interrupt factors, but a dedicated operation target registration register RG is provided for each interrupt factor. When each interrupt factor occurs, if the corresponding operation target registration register is referenced, the number of registers to be operated can be finely adjusted for each interrupt factor. By reducing the number of registers to be manipulated to the minimum necessary according to the cause, the dead time in save processing and restoration processing is reduced, and the time required from interrupt start to interrupt return is minimized for each interrupt factor. It is also possible.

  An explanatory diagram of the save / restore operation in the third method is shown in FIG. 7, and an explanatory diagram of the save / restore instruction is shown in FIG.

  As shown in FIG. 7, in the third method, a save operation instruction OP21 with an operation target designation and a restore operation instruction OP22 with an operation target designation are newly defined, and these instructions OP21 and OP22 are Only when executed, selective save processing and restore processing are executed only for the registers specified by the operands of those instructions. That is, in the first method and the second method described above, the register to be operated is designated by connecting a program development support apparatus (not shown) to the CPU unit and in accordance with an instruction from the program development support apparatus. This is made possible by writing a predetermined value in the operation target registration register (RG) provided in the IC 14. In the third method, the register to be operated is designated based on the register designated by the instruction operand when the instruction is executed.

  As shown in FIG. 8, the instructions OP21 and OP22 with operation target designation are composed of an instruction code, a first operand, and a second operand, as shown in FIG. The instruction code consists of a code (in this example, “EVRG”) indicating that the instruction word is a save operation instruction. The operation target register is designated as the first operand. An example of the designation method is shown in FIG. In this example, the operation target registration register (RG) is a 16-bit register. Bit 0 is a register A designation area, bit 1 is a register B designation area, bit 2 is a register C designation area, bit 3 is a register D designation area, bit 4 is a register E designation area, bit 5 is a register F designation area, etc. Sixteen register designation areas are allocated to sixteen bits. When the value of the register designation area is “1”, the register corresponding to the area is a save target. When the value of the register designation area is “0”, the register corresponding to the area is not saved. In the example of FIG. 5B, it is shown that two registers, register B and register F, are saved, and the other registers are not saved. In this example, if bit 0 is LSB (Least Significant Bit), the content of the bit string of the 16-bit register is expressed as 0x0022 (hexadecimal number). Therefore, when only two registers, register B and register F, are to be saved, 0x0022 (hexadecimal number) is designated as the numerical value for the first operand of the save operation instruction EVRG.

  On the other hand, a stack pointer address indicating the storage position of the stack area (MA) is described in the second operand, and data storage (push) and data read (pop) related to the stack area (MA) are performed according to the stack pointer address. The control is executed. In the example of FIG. 8A, MA0000 representing the top address (0000) of the stack area (MA) is designated as the stack pointer address. Although the restoration operation instruction is not shown, it may be configured in the same instruction format as the save operation instruction. For example, “RTRG” is used as a code indicating that the instruction word is a restoration operation instruction, an operation target register to be restored is specified in the first operand, and data to be restored is stored in the second operand. The stack pointer address may be specified.

  Returning to FIG. 7 again, as shown in FIG. 7A, in the operation at the time of saving, if the saving operation instruction OP21 with the operation target designation described above is decoded and executed, As shown in FIG. 8A, if 0x0022 is described in the first operand, the bit string (0000 0000 0010 0010) corresponding to the value is a register corresponding to “1” (register B, register F). Only, data is stored (pushed) into the stack area (MA), and the save operation is completed. On the other hand, as shown in FIG. 5B, in the operation at the time of restoration, when the restoration operation instruction OP22 with the operation target designation is decoded and executed, the register B and the register designated by the first operand are registered. Only for F, data is read (popped) from the stack area (MA), and the read data is stored in the original registers (register B, register F), thereby completing the restoring operation.

  Thus, according to the third method, the save operation instruction OP21 with the operation target designation and the restore operation instruction OP22 with the operation target designation are arranged at appropriate positions in the user program, so that the save timing and restoration timing are set. Etc. can be arbitrarily associated with the control status at that time, and the register to be saved or restored can be specified by the save instruction and the restore instruction itself. Operation instruction pairs that are paired with each other are provided for each interrupt factor, and the contents of the operation target instruction added to them are made different so that save and restore operations can be performed regardless of the type of interrupt factor. The number of operation registers to be saved is kept to the minimum necessary, and each interrupt process corresponding to each interrupt factor is from the start to the return. Time can also be a minimum.

  In the embodiment described above, as an operation procedure of the interrupt process in the CPU unit, the pre-process A, the main process B, and the post-process C are illustrated as examples of dedicated IC processes as shown in FIG. However, the present invention is not limited to this, and can also be applied to a case where the pre-processing A, the main processing B, and the post-processing C are all executed by a microprocessor (MPU). The present invention can also be applied to a case where the pre-processing A and the post-processing C are executed by a microprocessor (MPU) and the main body processing B is executed by a dedicated IC.

  According to the present invention, when executing the interrupt user program, the register saving process and the register restoring process are executed only for the operation register designated by the operation target register designating means. As long as only the operation register to be operated in advance is specified in advance by the operation target register specifying means, the time required for register saving processing and register restoring processing is minimized, and the time required from interrupt start to interrupt return Can be shortened as much as possible.

It is a hardware block diagram of CPU unit of PLC which concerns on this invention. It is a flowchart which shows the operation | movement procedure of the interruption process in CPU unit of PLC which concerns on this invention. It is explanatory drawing (the 1) of the saving / restoring operation | movement in a 1st system. It is explanatory drawing (the 2) of the saving / restoring operation | movement in a 1st system. It is explanatory drawing of the save / restoration operation | movement in a 2nd system. It is a block diagram of the operation target registration register. It is explanatory drawing of the save / restore operation | movement in a 3rd system. It is explanatory drawing of a save operation command. It is a hardware block diagram of the CPU unit of the conventional PLC. It is a flowchart which shows the operation | movement procedure of the interruption process in the conventional CPU unit. It is explanatory drawing which shows the relationship between the cycle execution task operation | movement and interrupt execution task operation | movement in CPU unit of PLC.

Explanation of symbols

1 CPU unit 10 Internal bus 11 User program memory (UM)
12 Input / output memory (IOM)
13 Nonvolatile memory for data storage 14 Dedicated IC
15 Microprocessor (MPU)
16 System program memory (ROM)
17 Work memory (work RAM)
A Pre-stage process B Body process C Post-stage process IT1 I / O and power interruption / interrupt signal IT2 Scheduled interrupt signal RG Operation target registration register RG1 First area RG2 Second area MA Stack area OP11 Save operation instruction OP12 Restoration operation Instruction OP21 Save operation instruction with operation target designation OP22 Restore operation instruction with operation target designation UP1-1, UP1-2 User program which is a cycle execution task UP2 User program which is an interrupt execution task

Claims (1)

Before execution of the user program executed as an interrupt execution task, pre-processing including at least register save processing that saves data stored in the operation register to a predetermined memory area is executed. After execution of the user program executed as a task, subsequent processing including at least register restoration processing for restoring the contents of the arithmetic register is executed by restoring data saved in a predetermined memory area to the original state. PLC,
An operation target register specifying means for arbitrarily specifying a register storing data to be saved in the register saving process and to be restored in the register restoring process;
Upon execution of the user program to be executed as an interrupt execution task, only for the specified operation register by the operation target register specifying means, possess the saving and restoring execution means for executing a register saving process, and the register restoration process,
The operation target register specifying means includes an operation target registration register for registering in advance data for specifying a register to be operated, and
The save / restore execution means executes the register save process and the register restore process only for the operation register specified by the data registered in the operation target registration register,
The save / restore execution means
A save operation instruction to which a predetermined instruction code is assigned; and
In the user program, in response to the saving operation instruction being decoded, the saving operation instruction execution means for executing the register saving process only for the operation register designated by the data registered in the operation target registration register;
A restoration operation instruction to which a predetermined instruction code is assigned; and
In the user program, in response to the decryption operation instruction being decoded, a restoration operation instruction execution means for executing register restoration processing only for the operation register specified by the data registered in the operation target registration register A PLC having an interrupt function characterized by including.

Images