JPH08161010A - Ladder sequence program arithmetic unit - Google Patents

Abstract

PURPOSE: To shorten the time of processing for ladder sequence operation by skipping the addresses of other networks when it is judged that a network execution flag is set, indicating head address information on the network to be executed next, and resetting the network execution flag. CONSTITUTION: When it is judged that the network execution flag A40 is set, the addresses of other networks for which network execution flags 40 are not set are skipped and the head address information A39 on the network to be executed for which the network execution flag 40 is set is indicated. Then the indicated head address information A39 is moved to the execution address of a central arithmetic processor and when operation is done, the network flag 40 of the network which has done the operation is reset. Consequently, the processing time of the ladder sequence operation can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ladder sequence program arithmetic unit used for a programmable controller (PC), an NC (numerical control) unit or the like.

[0002]

2. Description of the Related Art Among devices for calculating a ladder sequence program, a conventional example here will be described by taking a programmable controller.

General programmable controller PC
Are configured as shown in FIG.

The input section A11 is an interface for receiving a status signal and an operation command signal from an external device to be controlled. The central processing unit (CPU) A12 controls the entire operation of the programmable controller PC and executes the ladder sequence operation. The system program memory A13 stores a program for controlling the operation of the central processing unit A12. The sequence program memory A14 stores a ladder sequence program (ladder sequence command word) A18 as shown in FIG. 11 programmed by the user.

The data memory A15 stores data necessary for ladder sequence calculation such as input / output data and internal data. The output unit A16 is an interface that sends a signal obtained as a result of the ladder sequence calculation to an actuator or a display of an external device to be controlled. The peripheral device interface A17 is an interface for exchanging data with peripheral devices such as a user programming device and a data communication device.

FIG. 10 is a circuit diagram of a ladder sequence circuit,
FIG. 11 shows a ladder sequence program (ladder sequence command word) A18 corresponding to FIG. FIG.
The numerical value 0, “10”, “11”, or “100” described in FIG. 11 indicates the data memory number (relay number) in the data memory A15.

Next, the operation of the programmable controller PC having the above configuration will be described.

Roughly except for the exception processing, the processing shown in the flowchart of FIG. 12 is performed. First, data such as a status signal and an operation command signal of an external device to be controlled is fetched via the input unit A11, and the data memory A15
(S01). Next, the ladder sequence command of the ladder sequence program A18 as shown in FIG. 11 stored in the sequence program memory A14 is read (S02). Then, in S03 to S06, the ladder sequence calculation is performed based on the input data and the read ladder sequence program A18.
That is, first, it is judged whether or not it is the END instruction (S0
3) Otherwise, read the data from the data memory A15 (S04), perform the operation based on the ladder sequence instruction, store the result in the data memory A15 (S05), and read the next ladder sequence instruction. Perform (S06), and then return to step S03. These steps S03 to S06 are the ladder sequence operation, and this ladder sequence operation is repeatedly executed until the END instruction comes. The ladder sequence operation is completed by the END command, and the data to be output is output to the external device via the output unit A16 (S07). Then, data is exchanged with a peripheral device such as a user programming device or a data communication device via the peripheral device interface A17 (S08).

Generally, the process from the first step S01 to the last step S08 of the flow chart is called one scan, and this scan is repeatedly executed as an arithmetic method of the programmable controller PC. It is called a click operation.

In steps S03 to S06, which are a part of the ladder sequence operation, the programmable controller PC reads the ladder sequence instructions in order from the beginning and executes the operation. After execution of the end instruction or the final address portion, if there is no jump instruction such as a subroutine instruction or a jump instruction, all programmed instructions are sequentially executed.

[0011]

A ladder sequence operation performed by a conventional programmable controller PC or the like executes an operation as programmed by a user regardless of changes in input information and internal information. That is, even when there is no change in the information input in the previous scan or the obtained internal information, the same calculation as that executed in the previous scan is performed, and the same calculation result is obtained. It will be.

Furthermore, if there is no change in these information over several scans, the same operation is repeated many times. In addition, even if some input information or internal information changes, the part related to the changed information is often related to only a small part of the entire ladder sequence program. The same operation as before is executed for the unrelated program part and the same result is obtained. That is, useless calculations are repeatedly executed.

By the way, if the time required to process one scan is shortened, the time from input to output is shortened and the response speed to control is improved. Also, from the viewpoint of cyclic calculation that repeats scanning operation,
When the scan time is shortened, the number of scans per unit time is increased, and the responsiveness to external information changes is improved. Conventionally, the central processing unit (CPU) used
The responsiveness has been improved by increasing the speed. However, when the CPU speed is increased, the above-mentioned useless calculations are executed more per unit time. This increases the waiting time until the start of various processes other than the ladder sequence calculation, and is not a fundamental solution to the problem.

The present invention was devised in view of such circumstances, and performs only the necessary parts for changes in input information and internal information, but does not perform unnecessary operations. This aims to shorten the processing time of the ladder sequence calculation.

[0015]

A ladder sequence program arithmetic unit according to the present invention defines a network number for each ladder network of a ladder sequence program, and the ladder of the network number corresponding to the network number. Input the means to store the network start address information and the means to store the next execution network number corresponding to the address when the data of each address is the same as the data of other ladder networks. A means for detecting a change in information, a means for detecting a change in internal information, a means for setting a change flag for the changed information portion, and a next execution corresponding to the next execution network number storage means. Means to read the network number and read next execution network number The means for resetting the change flag when there is no number, the means for judging whether or not the change flag is set, and the means for reading out when it is judged that the change flag is set Means for setting a network execution flag in association with the start address information based on a network number corresponding to a next execution network number; means for determining whether the network execution flag is set; and the network execution When it is determined that the flag is set, the addresses of other networks for which the network execution flag is not set are skipped, and the network execution flag is set. Address to be executed by the central processing unit Means for transferring the address, is characterized in that a means for resetting the network execution flag to the network performing the operation when the operation is performed.

[0016]

The central processing unit is in the middle of performing an operation (ladder sequence operation) in a ladder network,
The next execution network number is read, and the network execution flag for the network that performed the calculation is reset. However, when there is a change in the input information or internal information, the change flag is set, and by setting this change flag, the network execution flag is set in association with the head address information based on the network number corresponding to the next execution network number. To be done. When there is no change in the input information or the internal information, and when the next execution network number indicates that there is no number, the change flag is reset, so the above network execution flag is not set. When the network execution flag is set, the execution address of the central processing unit is moved to the head address in the network to be executed next where the network execution flag is set. As a result, the address of the other network whose network execution flag is in the reset state because the change flag is in the reset state is skipped, and the operation in that network is not performed. That is, no unnecessary calculation is executed for a change in the input information or a change in the internal information, and the processing time of the ladder sequence calculation is significantly shortened.

In other words, the execution speed of one scan becomes faster, the time from the input of the status information of the external device to the output of the calculation result becomes shorter, and control with good responsiveness becomes possible. From the viewpoint of cyclic calculation,
The increase in the execution speed of one scan means that the number of scans per unit time increases, and the time from the input processing to the next input processing becomes short.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a ladder sequence program computing device according to the present invention will be described in detail below with reference to the drawings. In this embodiment, a programmable controller is taken as an example. The configuration of the programmable controller PC is the same as that shown and described in FIG.

The operation of the ladder sequence program processing of this embodiment is shown in the flow charts of FIGS. 6 to 9. Before starting the calculation, the following [1] to [5] will be described.
Data table is created and stored in the data memory A15 (step S11).

First, the creation of these data tables will be described below.

[1] Setting of Next Execution Network Memory A next execution network memory A34 is shown in FIG. 3 (c).
Is. Ladder sequence command word A33 (Fig. 3 (b))
Of the ladder network number (FIG. 3) in which the instruction to handle the same data is present in the increasing direction of the program address (A32 in FIG. 3B) in a state corresponding to each
(A31) of (a) is stored in the next execution network memory A34 (first line of step S11 in FIG. 6).

A user handling equipment such as a programmable controller PC generally designs a ladder sequence circuit A21 as shown in FIG. The individual circuits connected to the busbar are called a ladder network. That is, A50, A51, A52 ... A56 are ladder networks. Although the network numbers of the ladder networks A51 to A56 are shown on the left side of FIG. 2, the ladder sequence circuit A21 is managed by this network number. The address in parentheses below the network number is the address of the head instruction of each ladder network, and this corresponds to the address of the head instruction in the network head program address A39 of FIG. 5B.

The instruction word of FIG. 3B is obtained by converting the logic of the ladder sequence circuit A21 shown in FIG. 2 into the ladder sequence instruction word A33. This ladder sequence command word A33 is stored in the sequence program memory A14 of FIG. In the programmable controller PC,
Calculations are sequentially executed according to the ladder sequence command word A33.

Processing is performed based on this ladder sequence command word A33, and the next execution network number is stored in the next execution network memory A34 of FIG. 3 (c). That is, the same data memory number as the data memory number handled by the instruction existing at that address is searched in the direction of increasing addresses, and the ladder network number existing next is stored in the next execution network memory A34. For example, “STR 10” is stored as the ladder sequence command word A33 at the address “0000”. Where "10"
Is the data memory number (relay number), but on the ladder sequence program which is the ladder sequence command word A33, the network number of the next ladder network in which this data memory number "10" is attached to the command is "0002. ("STR at address 0016
10)), "0002" is stored as the next execution network number in the address "0000" of the next execution network memory A34 (see the chained arrow in the figure). If the same data memory number does not exist in the subsequent ladder network, the information "FFFF" meaning no number is stored in the next execution network memory A34.

Regarding the data memory numbers used in the OUT instruction and the instruction for instructing the output such as the timer instruction and the counter instruction which are not described here, the instruction for instructing the last output existing in the ladder sequence program. As the next execution network number corresponding to, the network number “0000” located first in the ladder sequence program is stored (A34 in FIG. 3C).
a)).

[2] Setting of initial network memory The data memory A15 in FIG. 1 stores relay data (ON / OFF data) and numerical data as control information. In the initial network memory A36 (which exists in the data memory A15 of FIG. 1) shown in FIG. 4B having an area corresponding to each bit of the data memory number of the data memory A35 shown in FIG. 4A. , Ladder sequence program (Ladder sequence command word A33)
The ladder network number (initial network number) in which the data memory number is described first is stored. For example, since the data memory number “0010” of the data memory A35 is first described by the network number “0000” of the ladder sequence command word A33 (corresponding to this being “STR 10”), the data memory number of the data memory A35 is The portion of the initial network memory A36 corresponding to the data memory number "0010" is shown in FIG.
The network number "0000" is stored as shown in (b). Further, since the data memory number “0013” of the data memory A35 is first described by the network number “0001” of the ladder sequence command word A33 (corresponding to this being “AND13”), the data of the data memory A35 is written. The portion of the initial network memory A36 corresponding to the memory number "0013" is shown in FIG.
The network number "0001" is stored as shown in (b).

[3] Setting of network execution address memory In FIG. 5B, the first instruction of each ladder network is a ladder sequence program (ladder sequence instruction word A3).
3) The network top program address memory A39 provided to refer to which address the address is located above
Is. This network top program address memory A39 exists in the data memory A15 of FIG. The address of the network top program address memory A39 (FIG. 5A) is the same as the ladder network number A38, and the execution start address of each ladder network is stored in each ladder network number A38. For example,
As can be seen from FIGS. 3A and 3B, since the execution start address of the network number “0001” is “0006”, the network number A38 of “0001” is as shown in FIGS. Corresponding to ".", The execution start address "0006" is stored in the network head program address memory A39. By doing so, when the contents of the network head program address memory A39 are read with the network number A38 as an address, the data becomes the execution start address of the ladder network.

[4] Set Network Execution Flag Memory (Write "1") The network execution flag memory A40 in FIG. 5C corresponds to the network head program address memory A39 in FIG. 5B. This network execution flag memory A40 exists in the data memory A15 of FIG. The network execution flag memory A40 is for managing the ladder network that needs to be executed. The network execution flag memory A40 is provided so that the same ladder network will not be duplicated when the necessary portion is calculated.

Before the calculation is started, "1" is written in all the addresses of the network execution flag memory A40.

When the flag of the network execution flag memory A40 is "1", the operation of the corresponding ladder network is executed. The flag is reset to "0" for the ladder network for which the calculation has been executed. When the flag is "0", the operation of the corresponding ladder network is not executed and the program jumps.

[5] Clearing the data change flag memory (writing "0") The data change flag memory A37 shown in FIG.
Data memory A15. Initially, the data change flag memory A37 is cleared at all addresses of the data memory A35.

When the input information from the outside has changed, or when the internal information has changed as a result of computing the ladder network, "1" is set as the change flag in the corresponding address of the data change flag memory A37, and When these pieces of information do not change, the corresponding address is reset to "0" as a change flag. When the change flag is "1", the instruction of the next ladder network is executed by setting the network execution flag of the corresponding next ladder network to "1". When the change flag is "0", the next ladder network is executed. The instruction of the next ladder network is skipped and not executed by resetting the network execution flag of the second ladder network to "0".

The above-mentioned settings [1] to [5] (step S11 in FIG. 6) are automatically performed when the program is stored or when the program mode is changed to the operation mode.
In order to initialize the data memory A15, it is assumed that all the ladder network instructions are executed in the first scan. This is accomplished by setting all network execution flags in the network execution flag memory A40 to "1".

The processing from step S12 of FIG. 6 will be described below.

In step S12, information indicating the state of the external device is fetched from the input section A11, and the data memory A15 is read.
To be stored. In step S13, the previous input information is compared with the current input information, and when there is a change in the input information, the process proceeds to step S14 and the input information is stored in the data change flag memory A37 of FIG. 4C. The change flag at the address (data memory number) that is being set to "1"
Set to. The input information is typically represented by ON and OFF, and a change flag is set when there is a change in the input information when it is turned from ON to OFF and from OFF to ON.

The input section A11 may determine whether or not the input information has changed, and the result may be transferred to the central processing unit A12. There are various means for determination, and there is no limitation. As a known technique, for example, there is JP-A-4-174008.

In step S15, the network number register is set to "0" in order to start execution of an instruction from the start address of the ladder scan program for one scan.
000 ”. Then, step S16
Then, the corresponding network execution flag is read from the network execution flag memory A40 of FIG. 5C based on the network number A38 of FIG. 5A. Then, in step S17, it is determined whether the read network execution flag is "1". In the first one scan, the network execution flags of all the network numbers are set to "1" in advance in step S11, and therefore the process proceeds to step S19. In the first ladder scan operation in one scan, S16 → S17 → S19 → S20 →
S21 → S22 → S23 → S24 (or S25) → S
26 → S27 (or S28 to S31) → S32 → S3
4 (or S33 to S34) → S35 (or S36)
→ Go through the routine of S22 (or S16). Specifically, it is as follows.

In step S19, the network execution flag is reset to "0". That is the next step S
Since the operation according to the instruction is always performed at 27 or step S28, it is reset in advance to indicate that the operation is performed. However, as will be described later, the network execution flag may be set to "1" again in step S33. In the next step S20, the address of the leading program of the ladder network is stored in the program counter. This is because the operation is executed from the first instruction of the ladder network. Step S21
Then, the instruction in the ladder sequence instruction word A33 in FIG. 3B is read at the current address designated by the program counter. Further, the next execution network number of the current address is read from the next execution network memory A34 of FIG. 3 (c). The reading of the next execution network number is a preparation for use in subsequent steps S23 and S33. In step S22, it is determined whether or not it is the END instruction. However, the determination is negative here, the flow proceeds to step S23, and it is determined whether or not the previously executed next execution network number is "FFFF" (none). "FFF
When it is “F”, the data memory number is skipped next time without using the data memory number.
In the data change flag memory A37 of (c), the change flag of the data memory number is reset to "0", and the data of the data memory number designated by the instruction of the current address designated by the program counter is read. On the other hand, if the next execution network number is other than "FFFF" (none), the process proceeds to step S24 to read the data of the data memory number designated by the instruction of the current address, and change flag corresponding to the data memory number. Is read out. This is because it is used in step S32.

Then, in step S26, the instruction is OUT.
Determine if it is an instruction. If it is other than the OUT instruction, the process proceeds to step S27 to execute a predetermined sequence operation, and proceeds to step S32. If it is an OUT instruction, the operation proceeds to step S28 to execute an OUT operation. Then, in step S29, as a result of the OUT operation, it is determined whether or not the data (internal information) of the data memory number has changed. If there is no change, the process proceeds to step S30 to reset the change flag to "0". If there is a change, the process proceeds to step S31, the change flag is set to "1", and the process proceeds to step S32. In this way, since it is inevitable that the operation is performed in either the general operation or the OUT operation, in order to indicate that the operation has been performed, the network execution flag is set to "in advance" in step S19. It was reset to "0".

In step S32, it is determined whether or not the change flag is set to "1". If it is set to "1", the process proceeds to step S33, and the next execution network number of FIG. 3 (c) read in advance in step S21 is used as an address to set the corresponding network execution flag of FIG. 5 (c). It is set to "1", so that the next network using the changed data is ready for later execution.

Then, the process proceeds to step S34. When the change flag is "0", the data used at the present time will not be used later, so that the data of "0" is reset by the reset performed in step S19 without setting the network execution flag. The state is left as it is and the process proceeds to the next step S34. .

Next, in step S34, it is judged whether or not the operation of the ladder network is finished at present, and if it is not finished, the routine proceeds to step S35, where the program counter is incremented and the next address shown in FIG. ), The instruction in the ladder sequence instruction word A33 is read. Further, the next execution network number of the new address is read from the next execution network memory A34 of FIG. 3 (c). Then, the process returns to step S22 and the same operation as above is repeated. As a result, when the operation of the ladder network is finished at present, steps S34 to S34 are performed.
Proceeding to 36, the network number register is incremented, and the process returns to step S16 to search for the network to be executed next. In step S16, the network execution flag is read, and in step S17 it is determined whether the network execution flag is "1". In the first scan, the network execution flag is "1" for all network numbers until the END instruction comes. Therefore, the process proceeds to step S19 and the same operation as above is repeated.

When the END instruction is received, the process proceeds from step S22 to step S37 to end the ladder sequence calculation. The network execution flag of the network number including the END instruction is always set to "1", and the operation is always performed to end the ladder sequence operation.

When the ladder sequence calculation is completed and the process proceeds to step S37, the data is output to the output section A16 in FIG. 1 to control the external equipment. Next, in step S38,
Data is exchanged with a peripheral device such as a programming device via the peripheral device interface A17. Then, in step S39, it is determined whether or not there is an instruction to stop the arithmetic operation. If so, the process proceeds to step S40 to end the arithmetic operation, but otherwise, step S41.
Then, the process proceeds to step S11 and the information indicating the next state of the external device is fetched from the input unit A11 and stored in the data memory A15. In step S42, the previous input information and the current input information are compared, and if there is a change in the input information, step S4
3, the data change flag memory A37 of FIG.
At 1, the change flag at the address (data memory number) storing the input information is set to "1". This sets that the input information has changed.

The processing for one scan is completed as described above, and the process returns to step S15 again to proceed to the next scan.

Since the data in the current input fetch is the same as the data in the previous input fetch and the input information has no change, the network execution flag due to the change flag being set to "0" as described above. Is set to “0”, the steps S16 → S17 →
In the closed loop routine of S18, as a result of the network number being incremented, the sequence operation of the part related to the input information is not performed. However, for the portion related to the internal information changed in the previous scan (in this portion, the change flag is set to "1" and the network execution flag is "1"), step S17 →
By proceeding to S19, the sequence calculation is performed only on the portion related to the changed internal information. If there is no change in the internal information, the input operation is performed again without shifting to the sequence operation routine.

As described above, only the necessary parts for the change of the input information and the internal information are calculated. However, since unnecessary calculation is avoided, the processing time of the ladder sequence calculation is reduced. Can be shortened,
The responsiveness to changes in input information can be improved.

The above-described sequence operation is generally executed by a general-purpose central processing unit (CPU), but it is better to execute it in parallel with the main CPU using dedicated hardware. A faster calculation can be realized.

[0049]

According to the ladder sequence program computing device of the present invention, unnecessary computation is not executed for changes in input information and changes in internal information, so that the processing time for ladder sequence computation is greatly shortened. You can That is, since the ladder sequence calculation can be speeded up and a change in information from an external device can be responded more quickly, the efficiency of operation of the external device can be significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a programmable controller as an example of a ladder sequence program operation device according to an embodiment of the present invention (common to conventional examples).

FIG. 2 is a circuit diagram of a ladder sequence circuit corresponding to the ladder sequence instruction word of FIG. 3 in the embodiment.

FIG. 3 is a memory content diagram showing a network number, a ladder sequence command word, and a next execution network memory in association with each other in the embodiment.

FIG. 4 is a memory content diagram showing a data memory, an initial network memory, and a data change flag memory in association with each other in an embodiment.

FIG. 5 is a memory content diagram showing a network number and a network head program address memory in association with each other in an embodiment.

FIG. 6 is a flowchart (part) used for explaining the operation of the ladder sequence program processing of the embodiment.

FIG. 7 is a flowchart (continuation of FIG. 6) provided for explaining the operation of the embodiment.

FIG. 8 is a flowchart (continuation of FIG. 7) used for explaining the operation of the embodiment.

FIG. 9 is a flowchart (continuation of FIG. 8) provided for explaining the operation of the embodiment.

FIG. 10 is a circuit diagram of a ladder sequence circuit shown for explaining a conventional ladder sequence program operation device.

FIG. 11 is an exemplary diagram of a ladder sequence program (ladder sequence command word) shown for explaining a conventional ladder sequence program arithmetic device.

FIG. 12 is a flowchart for explaining the operation of a conventional ladder sequence program calculation device.

[Explanation of symbols]

PC: Programmable controller (an example of ladder sequence program arithmetic unit) A11 ... Input unit A12 ... Central processing unit A13 ... System program memory A14 ... Sequence program memory A15 ... Data memory A16 ... Output unit A17 ... ... Peripheral device interface A21 ... Ladder sequence circuit A31 ... Ladder network number A32 ... Address A33 ... Ladder sequence command A34 ... Next execution network memory A35 ... Data memory A36 ... Initial network memory A37 ... Data change Flag memory A38 …… Network number A39 …… Network execution address memory A40 …… Network execution flag memory A50 to A56 …… Ladder network

Claims (3)

[Claims] 1. A means for storing a network number for each ladder network of the ladder sequence program, and storing the start address information of the ladder network of the network number corresponding to the network number, and each address. When the data of the same is the same as the data of other ladder network, the means to store the next execution network number corresponding to the address, the means to detect the change of the input information, and the change to the internal information are detected. Means, a means for setting a change flag for the changed information part, a means for reading the corresponding next execution network number from the storage means for storing the next execution network number, and the read next execution network number being a number. Means for resetting the change flag when indicating no , Means for determining whether the change flag is set, and when it is determined that the change flag is set,
A means for setting a network execution flag in association with the start address information based on a network number corresponding to the read next execution network number; a means for determining whether or not the network execution flag is set; When it is determined that the network execution flag is set, the addresses of other networks for which the network execution flag is not set are skipped, and the network execution flag is set. Ladder comprising means for moving an address indicated by information to an address executed by the central processing unit, and means for resetting the network execution flag for the network on which the operation is performed when the operation is performed. Sequence program Beam computing device. 2. The means for resetting the network execution flag, after the means for judging the setting of the network execution flag judges that the set, and the central operation of the address indicated by the head address information in the network to be executed next. The processing device is configured to operate before moving to an address executed by the processing device.
Ladder sequence program calculation device according to item 1. 3. The means for determining the change flag setting includes:
The central processing unit is configured to operate after completion of execution of an operation at one address and before reading an instruction at the next address. Ladder sequence program calculation device described.