JPH0328905A - Input/output transfer method for programmable controller - Google Patents

Abstract

PURPOSE:To shorten the processing time or the I/O transfer by producing previously the input and output transfer control tables and performing the output transfer of a DMA controller and the input transfer of a CPU in parallel with each other. CONSTITUTION:A CPU 1 produces the I/O array information based on the attachment information on an actual I/O substrate and then produces the input and output transfer control tables based on the I/O array information to store it into a RAM 4. When the I/O transfer is started, the information on the output transfer control table is set to a DMA controller 2. Then an output transfer command is supplied to the controller 2 to start it. Thus the output transfer is successively carried out. At the same time, the CPU 1 repeats the reading of the information of the input transfer control table and the input transfer until the process is through with all contents of the table. Under such conditions, the controller 2 works in a cycle steal state to the CPU 1 and therefore the input transfer and the output transfer are processed in parallel with each other. Thus the processing speed is improved for the I/O transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output transfer method for a programmable controller (hereinafter referred to as a PC).

[Prior Art] FIG. 8 is a flowchart showing a conventional PC human output transfer method. When the power is turned on, one of the initial setting processes is to create input/output (hereinafter referred to as I/O) array information according to the mounting information of the actual input and output boards and store it in a memory such as RAM ( S81). Then, when the 1/O transfer calculation operation starts while the PC is operating (S8
2) Read the I/O array information created in advance (S
83), and then determines whether the processing has finished (
Sll4) If the process has not been completed, it is determined whether the next process is input transfer or output transfer (S85).
), if it is determined that it is an input transfer, the on/off information of the input board is taken into the internal status area (98B
).

If it is determined that it is an output transfer, the on/off information in the internal status area is output to the output board (38B).

[Problem to be solved by the invention] In the conventional PC I/O transfer method as described above,
It was only possible to process either input transfer or output transfer, and there was a limit to processing speed.

This invention was made in order to solve such problems, and it is a PC that makes it possible to improve the processing speed of I/O transfer.
The purpose of this invention is to obtain an I/O transfer method.

[Means for solving the problem] A PC I/O transfer method according to the present invention (Claim 1!t
) includes a table creation step of creating an input transfer control table and an output transfer control table in advance based on the mounting information of the input board and output board, setting the output transfer information of the output transfer control table in the DMA controller, and DM
An output transfer step in which the A controller outputs output data to the output board based on the output transfer information, and input transfer information in the input transfer control table is set in the central processing unit, and the central processing unit outputs the output data to the input board based on the input transfer information. and an input transfer step of reading input data from and inputting it. Then, the output transfer step and the input transfer step are performed in parallel.

Further, the PC I/O transfer method according to the present invention (claim 2
Although the table creation process is the same as the above, the difference is that the input transfer process is performed by a DMA controller, and the output transfer process is performed by a central processing unit. That is, in the input transfer step, the input transfer information of the input transfer control table is set in the DMA controller,
The DMA controller inputs input data from the input board based on the input transfer information. In the output transfer step, output transfer information in the output transfer control table is set in the central processing unit, and the central processing unit outputs output data to the output board based on the output transfer information.

[Function] In this invention (claim 1), the input transfer control table and the output transfer control table are each created in advance. In the l/0 transfer, output transfer by the DMA controller and input transfer by the central processing unit are performed in parallel.

Further, in the present invention (claim 2), similarly to the above, an input transfer control table and an output transfer control table are respectively created in advance. During I/O transfer, input transfer by the DMA controller and output transfer by the central processing unit are performed in parallel. [Example] Fig. 3 shows a PC that implements a method according to an example of the present invention.
FIG. 2 is a block diagram showing the hardware configuration of the computer.

In the figure, <1) is the CPU, and (2) is the DMA controller. This DMA controller (2) is
It is assumed that the CPU (1) can operate by stealing cycles. (3) is ROM, (4) is RAM,
(5) is an I/O board. These are interconnected via a bus (6).

FIG. 1 is a flowchart showing the I/O transfer operation of the PC in FIG. 3, and FIG.
3 is a flowchart showing the operation of interrupt processing by.

In the flowchart in Figure 1, when the power is turned on,
The CPU (1) creates I/O array information according to the installation information of the actual I/O board (5) and stores it in the RAM (4> (Sll). Figure 4 shows the I/O array information. This table is composed of input board or output board identification information and the number of points for that board, for each board in ascending order of I/O number.Next, input transfer is performed based on this I/O arrangement information. A control table and an output transfer control table are respectively created and stored in RAM (4) (S12).

FIG. 5 is a diagram showing an input transfer control table, which is composed of groups of input boards that are consecutively arranged next to each other. This table is made up of status area addresses corresponding to input board groups, input boat addresses corresponding thereto, and instructions to jump to addresses in ROM (3) where actual processing is performed.

Figure 6 shows the output transfer control table. It is created in the same way as the input transfer control table, but it is made up of a group of output boards arranged next to each other and the input boat address. for the output boat address,
Also, the difference is that the number of bytes transferred is specified for the jump instruction.

Returning to the flowchart in FIG. 1, when the /0 transfer process starts (Sl3), first the output control information in the output transfer control table is read (S14), and the presence or absence of output processing is checked (Sl5). , if it is determined that there is, the information in the output transfer control table is transferred to the DMA controller (2
) and supplies an output transfer command to the DMA controller (2) to start it up (81B).

The DMA controller (2) sequentially performs output transfer based on the output control information of the set output transfer control table.

On the other hand, the CPU (1) continues to read the input control information from the input transfer control table (817), determines whether the processing has finished or not (Sl. 8), and if it has not finished, input transfer. (S19). During this input transfer, reading the input control information from the input transfer control table and input transfer are repeated (8
17) (819), and continues until processing of all contents of the input transfer control table is completed (81g).

Output transfer by the DMA controller (2) is processed by the DMA controller (2) to the CPU (1) by cycle stealing, so the above step (
The input transfers of Sl7) to (SL9) and the output transfers of the DMA controller (2) are processed in parallel.

In the DMA controller (2), when the output transfer based on the output control information of the output transfer control table is completed,
An interrupt is applied to CPU (1), and the interrupt processing shown in the flowchart of FIG. 2 is activated. In this interrupt processing, first, the contents of the register of CPU (1) are saved (S21), output control information is read from the output transfer control table (S22), and if the processing is not completed (823), The output control information of the output transfer control table is set in the DMA controller (2), and an output transfer command is output to the DMA controller (2) to start it (S24). Thereby, the DMA controller (2) starts output transfer again according to the output control information.

On the other hand, CPU (1) is a DMA controller (2)
After outputting an output transfer command, the contents of the register are restored (S26), and then the process returns to the one before the interrupt.

For example, if an interrupt occurs during input transfer (S19) in FIG. 1, the input transfer process is restarted.

Each time the output transfer by the DMA controller (2) is completed, the interrupt processing shown in FIG. Controller (2
) ends the interrupt processing (S25), restores the contents of the register of CPU (1) (82G), and returns to the processing before the interrupt, as in the case described above.

FIG. 7 is a flowchart showing the input/output transfer operation of a PC according to another embodiment of the present invention.

In this embodiment, after processing the input transfer (S19), the process returns to step (Sl4), and before starting the calculation operation of the input transfer, the control information of the output transfer is read and a transfer command is issued to the DMA controller (2). DMA controller (2
) to transfer the output using 814XS15) (S
l6) Input transfer by CPU (1) is performed, and even if interrupt processing is not performed for CPU (1), input transfer and output transfer can be performed as in the above embodiment. Parallel processing is possible.

By the way, in the transfer (cycle steal) by the DMA controller (2), the speed at which one output point is transferred by output transfer is several times faster than the speed at which one input point is transferred by input transfer. On the other hand, in the above embodiment, originally unnecessary D
Transfer time by MA controller (2) is required,
Although this causes an increase in processing time, since the output transfer is extremely fast and the time is short as described above, the processing time is reduced by about 10 to 30% compared to the conventional method.

Note that in the embodiments shown in FIGS. 1 and 2 and the embodiment shown in FIG. may be performed by a DMA controller, and output transfer may be performed by a central processing unit. In that case, in the embodiments of FIGS. 1 and 2, steps (Sl4) to (S14) of the flowchart of FIG.
"Output..." in S16) is replaced with "input" and processing related to input transfer is performed, and steps (S17) to (3)
19), "input..." is replaced with "output" and output transfer is performed. Further, each step in the flowchart of FIG. 2 is replaced with processing for input transfer to perform input transfer.

Further, the same applies to the flowchart of FIG. 7, and the "output..." in steps (314) to (31B) is replaced with "input" to perform processing related to input transfer, and the process related to input transfer is performed in steps (S17) to (319). Replace "input..." with "output" and perform output transfer.

Furthermore, in the block diagram of FIG. 3, it goes without saying that the DMA controller (2) may be included in the CPU (1).

[Effects of the Invention] As described above, according to the present invention, an input transfer control table and an output transfer control table are created in advance, and output transfer or input transfer (cycle steal) by the DMA controller and input transfer or output by the central processing unit are performed. Since the transfer is performed in parallel, the processing time for I/O transfer is significantly faster.

[Brief explanation of drawings]

FIG. 1 shows a PC that implements a method according to an embodiment of the present invention.
A flowchart showing the I/O transfer operation of
FIG. 3 is a flowchart showing the operation of interrupt processing by the MA controller, and FIG.
A block diagram showing the hardware configuration of a PC implementing the O transfer method, Figure 4 is a diagram showing a table of I/O array information, Figure 5 is a diagram showing an input transfer control table, and Figure 6 is a diagram showing output transfer. A diagram showing a control table, FIG. 7 is a flowchart showing the I/O transfer operation of a PC implementing a method according to another embodiment of the present invention, and FIG. 8 shows a conventional I/O transfer method. It is a flowchart.

Claims (2)

[Claims] (1) A table creation process in which an input transfer control table and an output transfer control table are respectively created in advance based on the mounting information of the input board and output board, and the output transfer information of the output transfer control table is set in the DMA controller, and the DM
An output transfer step in which the A controller outputs output data to the output board based on the output transfer information; and an output transfer step in which the input transfer information of the input transfer control table is set in the central processing unit, and the central processing unit outputs the output data based on the input transfer information. An input/output transfer method for a programmable controller, comprising an input transfer step of reading and inputting input data from an input board, and performing the output transfer step and the input transfer step in parallel. (2) A table creation process in which an input transfer control table and an output transfer control table are respectively created in advance based on the mounting information of the input board and output board, and the input transfer information of the input transfer control table is set in the DMA controller, and the DM
An input transfer step in which the A controller inputs input data from the input board based on the input transfer information; and an input transfer step in which the output transfer information of the output transfer control table is set in the central processing unit, and the central processing unit inputs the input data based on the output transfer information. 1. An input/output transfer method for a programmable controller, comprising an output transfer step of outputting output data to an output board, the input transfer step and the output transfer step being performed in parallel.