JP2000242524A - Software simulator for processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a software simulator for a processor capable of easily returning to a halfway state of an instruction execution process after the instruction of a program to be debugged is executed. SOLUTION: Each time an instruction is carried out, a software simulator makes the resource values of a register model and a memory model held by a state information file 6. Furthermore, when an instruction for returning to a state for only one instruction is inputted after the instruction is executed, it returns the resource values of the register model and the memory model to the previous state for only one instruction from the current state on the basis of the contents of the file 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a software simulator for a processor used for debugging a program.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a conventional software simulator of a processor.

[0003] The software simulator includes a simulator engine unit 11 composed of a program that performs the same operation as the processor, a register group model 12 that realizes a register group built in the processor in software, and a data memory built in the processor in software. And a program memory model 14 in which a program memory incorporated in the processor is implemented in software. The program memory model 14 stores a program to be debugged.

When an execution start command is input to the simulator engine unit 11, a program to be debugged is executed. In such a conventional processor software simulator, during execution of a program, once the instruction of the program to be debugged is executed,
Could not return to the state during the execution process. Therefore, when it becomes necessary to verify a state in the middle of the execution process, it was necessary to perform the simulation again up to that state.

[0005]

SUMMARY OF THE INVENTION The present invention provides a software simulator for a processor which can easily return the state of a software simulator to a state in the course of instruction execution after executing an instruction of a program to be debugged. The purpose is to provide.

[0006]

According to a first aspect of the present invention, there is provided a software simulator of a first processor, wherein each time one instruction is executed, a resource value of a register model and a memory model is held in a state information file; When an instruction for returning the state by one instruction is input after executing the instruction, the resource values of the register model and the data memory model are changed by one instruction from the current state based on the contents of the state information file. It is characterized by having means for returning to the previous state.

A software simulator for a second processor according to the present invention includes means for holding a resource value of a register model and a memory model in a state information file each time one instruction is executed, and for executing the instruction after executing the instruction. Means for returning the resource values of the register model and the memory model to the state of the designated stage based on the contents of the state information file when a command for returning the state to a predetermined stage during the execution process is input. It is characterized by having.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a configuration of a software simulator of a processor.

The software simulator includes a simulator engine unit 1 composed of a program that performs the same operation as the processor, a register group model 2 that implements a register group incorporated in the processor in software, and a data memory incorporated in the processor in software. And a program memory model 4 in which a program memory incorporated in the processor is implemented in software, a state management unit 5 for managing the state of the simulator, and a state information file 6. The program memory model 4 stores a program to be debugged.

The simulator engine unit 1 receives an instruction to start or stop the operation of the state management unit 5 together with an execution start instruction (the range of a program to be executed can also be specified). State management unit 5
When a command to stop the operation of the software simulator is input to the simulator engine unit 1, the operation of the software simulator is exactly the same as the conventional one.

When a command for making the operation by the state management unit 5 into an operating state is input to the simulator engine unit 1 together with the execution start instruction, the state management unit 5 performs the following operation during execution of the program. Do.

That is, each time the simulator engine unit 1 executes one instruction, the state management unit 5 sets the resource value of each register model of the register group model 2, the resource value of the data memory model 3, and the content of the executed instruction. Is output to the state information file 6. Status information file 6
Are the number of the latest predetermined instructions output from the state management unit 5,
For example, resource values and execution instructions for the latest 10 instructions are held.

As described above, when a command for returning the state by one instruction is input to the simulator engine unit 1 after all the instructions have been executed, the state management unit 5
Reversely rewrites the resource value of the register group model 2 and the data memory model 3 to the value of one instruction before based on the resource value of one instruction before by following the state information file 6. In this example, by sequentially performing the operations as described above, it is possible to return to the state nine instructions earlier.

As shown in FIG. 2, the resource value of the register model R1 and the address of the data memory model 0x10
When the instruction A for updating the resource value of 0 is executed, the resource value before the execution is held in the state information file 6, so that after the execution of the A instruction, the state information file 6 is updated.
To return to the state before the execution of the A instruction.

After the instruction is executed, when a command for returning the state to a predetermined stage in the course of the instruction execution is input to the simulator engine unit 1, the register model and the register model are updated based on the contents of the state information file. The resource value of the data memory model may be rewritten to a resource value at a specified stage.

[0018]

According to the present invention, the state of the software simulator can be easily returned to the state in the course of the instruction execution after the execution of the instruction.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a software simulator of a processor.

FIG. 2 is a schematic diagram showing information held in a state information file when an instruction A for updating a resource value of a register model R1 and a resource value of an address 0x100 of a data memory model is executed.

FIG. 3 is a block diagram showing a configuration of a conventional software simulator of a processor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Simulator engine part 2 Register group model 3 Data memory model 4 Program memory model 5 State management part 6 State information file

Claims (2)

[Claims] 1. A means for holding a resource value of a register model and a memory model in a state information file each time one instruction is executed, and
When a command to return the status by the command is input,
Means for returning the resource values of the register model and the memory model to a state one instruction prior to the current state based on the contents of the state information file. 2. A means for holding a resource value of a register model and a memory model in a state information file every time one instruction is executed, and after execution of the instruction, a state is set at a predetermined stage in the instruction execution process. Means for restoring the resource values of the register model and the memory model to the state at the specified stage based on the contents of the state information file when a command for returning is input.