JPH08185341A - Cpu simulator - Google Patents

Abstract

PURPOSE: To reexecute a target program from the same point even when state information stored in a file is reduced. CONSTITUTION: In the case of debugging a target program from a prescribed point plural times, the states of respective addresses or the like of registers and memories in a target CPU of which state is changed from an initial state when a point immediately before the prescribed point is executed at first are previously stored in a state storing file 32. At the time of executing the prescribed point and after, a flag corresponding to a resource of which state is updated out of plural flags corresponding to the addresses or the like of respective registers and memories which are stored in an updating position storing table 42 is turned on. In the case of executing debugging again from the prescribed point, the state is restored to the state obtained at the time of executing the point immediately before the prescribed point at first based upon the contents stored in the file 32 and the contents of the table 42.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU simulator for simulating the operation of a target CPU.
In particular, the present invention relates to a CPU simulator capable of efficiently debugging a program developed for a target CPU (target program).

[0002]

2. Description of the Related Art As a technique for debugging a target program developed for a target CPU before a target machine including the target CPU is completed or before debugging on the target machine, a CPU different from the target CPU is included. There is a technique for simulating the operation of a target CPU according to a target program on a CPU simulator.

When debugging a target program, it may be necessary to perform debugging several times from the same point in the target program in different ways. For example, when debugging a target program including a boot processing unit that performs initialization processing of registers and the like and recognition processing of another connected device, and a subsequent application unit, the debugger starts from the start point of the application unit. You may need to debug several times in different ways.

In such a case, if the program is executed from the beginning of the target program, a lot of useless time is spent until the application part, which is the debug target part, is executed. Therefore, conventionally, at the time of the first debugging, the state of the memory and the register of the target CPU at the time when the start processing unit of the target program is completed is executed by executing the program from the beginning of the target program, and all the states are stored in a file. For the second and subsequent debuggings, the state of the memory and registers saved in the above file is used to restore those states to the state at the time of termination of the startup processing unit. The program is executed (for example, Japanese Patent Laid-Open No. Hei 4-332553).
By doing so, it is not necessary to execute the startup processing unit at the time of the second and subsequent debuggings, so that debugging can be performed efficiently.

[0005]

However, the above-mentioned conventional technique has a problem that a large capacity file is required because all states of the memory and the register are stored in the file. Since a large amount of information must be read from the file device, there is a problem that restoration takes time.

Therefore, an object of the present invention is to enable the target program to be re-executed from the same point even if the state information stored in the file is reduced.

[0007]

According to the present invention, a target CP to be simulated is provided to achieve the above object.
In a CPU simulator that simulates the operation of the U target program, the state may be updated when the operation of the target CPU of the target program is simulated.
And an update position storage table having a flag for each resource of the target CPU whose initial state is determined, and when the state of the resource is updated while simulating the operation of the target CPU according to the target program, An update position storage circuit for changing a flag in the update position storage table corresponding to the resource whose status has been updated to one indicating that the update has been completed; and the update position storage table when the target program has been executed to a certain point. And a state of the resource in which the flag in the update position storage table indicates that the update has been completed is stored in a state storage file, and the update processing unit clears the update position storage table. At the time of restoration, the flag in the update position storage table indicates that the update has been completed. For each of the resources, if the corresponding flag stored in the state save file indicates an update, that state is restored to the state saved in the state save file, and When the corresponding stored flag indicates that the flag has not been updated, the restoration processing means for restoring the state to the initial state is provided.

According to the present invention, in order to achieve the object of further reducing the amount of information stored in a file, the update position storage table stores each of the memories of the target CPU into which the target program is loaded. An address and a flag for each address of the memory of the target CPU used as a work area by the target program, the update position storage circuit includes:
When the target program is loaded, the flag of each address of the memory where the target program is loaded is changed to a flag indicating that the memory has been updated, and when the state of the memory is updated when a simulation is executed, the updated If the flag corresponding to the address of the memory has not been updated, the flag is changed to that indicating the update, and when the target program has been executed up to a certain point, the flag in the update position storage table is updated. The state where the target program was loaded and the memory state of the address of the work area where the memory state was updated, indicating the updated state, are stored in the state holding file, and the restoration processing means stores the updated position in the updated position storage table. For each address in the memory where the flag of If the corresponding flag stored in the state save file indicates an update, the memory state is restored to the state saved in the state save file, and the corresponding state saved in the state save file is restored. When the flag to indicate that it has not been updated, the memory state is restored to the initial state.

[0009]

With respect to the resources of the registers and the buffers for input / output ports whose initial states are determined among the resources of the target CPU, when the states are updated during the simulation, the update position storage circuit stores The flag corresponding to the above resource is changed to the one indicating that the resource has been updated.

When the target program is executed up to a specific point, for example, a point immediately before the first debugging start point, the storage processing means stores the contents of the update position storage table and the update position storage table. The state of the resource whose inside flag indicates that the resource has been updated is stored in the state storage file, and then the update position storage table is cleared.

Thereafter, when the portion to be debugged of the target program is executed, the update position storage circuit performs the same processing as described above, and updates the flag in the update position storage table corresponding to the resource whose status has been updated. Change to what shows. Therefore, of the flags in the update position storage table, only the flag corresponding to the resource whose status has been updated during execution of the part after the debug start point indicates that the status has been updated.

At the next debugging, the restoration processing means
Based on the contents of the update position storage table and the state storage file, the resources of the target CPU are restored to the state when they were executed up to the point immediately before the debug start point. That is,
For each resource for which the flag in the update position storage table indicates “updated”, if the corresponding flag stored in the state storage file indicates “update”, the state is stored in the state storage file. The state is restored, and if the corresponding flag stored in the state storage file indicates “not updated”, the state is restored to the initial state.

For each address of the memory of the target CPU into which the target program is loaded and each address of the memory of the target CPU used as a work area by the target program, when the target program is loaded, the update position storage circuit stores The flag corresponding to the address at which the program was loaded is changed to indicate that the program has been updated. In addition, when the contents of the memory are updated during the simulation, the update position storage circuit changes the flag corresponding to the memory address to the one indicating that the update has been completed.

When the target program is executed up to the point immediately before the debug start point, the memory state of the address of the memory whose corresponding flag indicates that the update has been completed, that is, the address and the memory state at which the target program was loaded, is changed. The updated memory state of the address of the work area is stored in the state storage file by the storage processing unit. Here, in the work area, the memory state of the address whose state has not been updated from the initial state is not stored in the state storage file, so that the amount of information stored in the state storage file can be reduced.

Thereafter, when the debug target portion of the target program is executed, the update position storage circuit performs the same processing as described above, and sets the flag in the update position storage table corresponding to the address of the memory whose status has been updated. Change it to indicate that it has been updated.

At the next debugging, the restoration processing means
Based on the contents of the update position storage table and the state storage file, the memory state of each address of the memory is restored to the state at the time of execution up to the point immediately before the debug start point.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which comprises a memory 1, a CPU 2, a file device 3, and an update position storage device 4.

The memory 1 has a memory section 11 for storing the state of the memory of the target CPU to be simulated, a register section 12 for storing the state of the register of the target CPU, and an I / O (input / output) of the target CPU. (Output) port buffer state is stored in the I / O port unit 13.

The memory 1 also stores a simulation program 14, a storage processing program 15, and a restoration processing program 16.

The simulation program 14 has a function of simulating the operation of the target CPU according to the target program. The save processing program 15 stores the memory state of each address of the memory of the target CPU stored in the memory unit 11, the register unit 12, and the I / O port unit 13, the state of each register, and each I / O port.
Among the states of the O port buffer, the update position storage table 42 has a function of storing in the state storage file 32 in the file device 3 the corresponding flag in the update position storage table 42 indicating that the update position storage table 42 has been updated. It has a function of saving the contents of 42 in the state saving file 32. The restoration processing program 16 restores the states of the memory unit 11, the register unit 12, and the I / O port unit 13 to the state immediately before the debug starting point according to the contents of the state save file 32 and the contents of the update position storage table 42. Have a function.

The file unit 3 includes an executable file 3
1 and a state storage file 32 are stored.

The executable file 31 includes a target C
An executable target program to be executed by the PU is stored. As the executable file 31, for example, an Intel OMF file, an Intel extended HEX file, or the like can be used.

The state save file 32 includes the contents of the update position storage table 42, the memory unit 11 and the register unit 1.
2, the target C stored in the I / O port unit 13
Among the memory status of each address of the PU memory, the status of each register, and the status of each I / O port buffer, the status indicating that the corresponding flag in the update position storage table 42 has been updated is stored.

The update position storage device 4 has an update position storage circuit 41 and an update position storage table 42.

The update position storage table 42, as shown in FIG. 2, is a flag corresponding to each address of the memory of the target CPU into which the target program is loaded and each address of the memory of the target CPU used as a work area by the target program. FM1 to FMi,
Flag FR1 corresponding to each register of the target CPU
FRj and flags FB1 to FBk corresponding to each i / O port buffer of the target CPU. The flag is off in the initial state. The work area, registers, and I / O port buffers are 0 in the initial state.

When the target program stored in the execution format file 31 is loaded into the memory unit 11, the update position storage circuit 41 selects one of the flags FM1 to FMi.
The function of turning on the flag corresponding to the address where the target program is loaded, the function of turning on the flag corresponding to the updated address of the flags FM1 to FMi, and the updated of the flags FR1 to FRj The function to turn on the flag corresponding to the register and the flag FB1
Among FBk, it has a function of turning on a flag corresponding to the updated I / O port buffer.

Next, as shown in FIG. 3, the operation of this embodiment is composed of a start-up processing unit 31a for performing processing for initializing registers and the like, a processing for confirming connected devices, and an application unit 31b. Target program 31
The case where the application unit 31b of P is debugged will be described as an example.

First, as shown in FIG. 4, the target program 31P stored in the executable file 31 is loaded into the memory unit 11. At this time, the update position storage circuit 41 sets the flag corresponding to the address at which the target program 31P is loaded among the flags FM1 to FMi stored in the update position storage table 42 and corresponding to each address of the memory of the target CPU. turn on. Here, the flag is turned on only at the address where the target program 31P is loaded, and the flag corresponding to the address used as the work area by the target CPU is not turned on.

When the loading of the target program 31P is completed, the simulation program 1
4, the activation processing unit 3 of the target program 31P
1a is executed, and further, a breakpoint command placed at a point immediately before the start of the application unit 31b is executed. During the execution of the activation processing unit 31a, the update position storage circuit 41
Are the flags FM1 to FM in the update position storage table 42.
Among the Mi, FR1 to FRj, and FB1 to FBk, the flag corresponding to the updated address, register, and I / O port buffer is turned on.

When the CPU 2 executes the breakpoint instruction, the CPU 2 performs a save process in accordance with the save process program 15. That is, the contents of the update position storage table 42 are saved in the state save file 32, and the states of the addresses, registers, and I / O port buffers for which the corresponding flags in the update position storage table 42 are turned on are saved. Save in the file 32, and then turn off all the flags in the update position storage table 42. Here, with regard to the registers and I / O port buffers, only the registers and I / O port buffers whose states have been changed from the initial state save the state in the state saving file 32. Since only the address at which the target program is loaded and the address whose state has changed from the initial state in the work area, the amount of state information stored in the state storage file 32 can be reduced.

When the saving process is completed, the CPU 2 executes the application section 31b of the target program 31P according to the simulation program 14, and debugs the application section 31b. During the execution of the application unit 31b, the update position storage circuit 41 updates the flags FM1 to FMi,
Flags corresponding to updated addresses, registers, and I / O port buffers among FR1 to FRj and FB1 to FBk are turned on.

Then, again, the target program 31
When debugging is performed from the application unit 31b of the P, the restoration processing according to the restoration processing program 16 is executed by the CP.
U2 is executed to restore the state of the memory, register, and I / O port buffer of the target CPU to the state immediately before the start of the execution of the application unit 31b.

That is, for the addresses, registers, and I / O port buffers for which the flags in the update position storage table 42 are turned on, the CPU 2 reads the update position storage table stored in the state storage file 32. It is determined whether or not the corresponding flag is on. If it is determined that the corresponding flag is on, the state is restored to the state stored in the state storage file 32, and it is determined that the flag is off. If so, the state is restored to the initial state (for example, 0).

For example, if the flag FR1 corresponding to the register R1 in the update position storage table 42 is ON, it is determined whether the flag RF1 of the update position storage table stored in the state storage file 32 is ON. If it is on, the memory state of the address corresponding to the register R1 in the register section 12 is restored to the state stored in the state storage file 32, and it is determined that it is off. If so, the state is restored to the initial state.

Thereafter, the CPU 2 executes the target program 31P from the application section 31b according to the simulation program 14.

[0037]

As described above, according to the present invention, for resources such as registers whose initial state is determined, only the state of the resource whose state is changed while the target program is executed up to a certain point is saved. Since it suffices to save the file in a file, there is an effect that the file capacity can be reduced as compared with the conventional technique that needs to save the state of all resources.

Further, according to the present invention, for a memory having an address whose initial state changes depending on the loaded target program, the memory state of the address where the target program is loaded and the target program is executed from the beginning to a certain point. It is sufficient to save the memory status of the address whose status was updated during the process in the status save file, and it is not necessary to save the memory status for the address of the work area whose memory status was not updated. The file capacity can be further reduced as compared with the conventional technique in which the memory state of all the addresses of the memory needs to be stored.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of contents of an update position storage table 42.

FIG. 3 is a diagram showing an example of a target program stored in an execution format file 31.

FIG. 4 is an operation explanatory diagram of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory 11 ... Memory part 12 ... Register part 13 ... I / O port part 14 ... Simulation program 15 ... Save processing program 16 ... Restoration processing program 2 ... CPU 3 ... File device 31 ... Execution format file 32 ... State Save file 4 ... Update position storage device 41 ... Update position storage circuit 42 ... Update position storage table

Claims (3)

[Claims] 1. A CPU simulator for simulating an operation of a target CPU to be simulated according to a target program, wherein the target CP of the target program is simulated.
An update position storage table having a flag for each resource of the target CPU whose state may be updated when simulating the operation of U and whose initial state has been determined; and the target CP associated with the target program.
An update position storage circuit for changing a flag in the update position storage table corresponding to the resource whose state has been updated to one indicating that the resource has been updated when the state of the resource is updated while simulating the operation of U; Saving the contents of the update position storage table when the target program has been executed to a certain point, and the state of the resource whose flag in the update position storage table indicates that the update has been completed, in a state storage file. Save processing means for clearing the update position storage table; and when restoring the state of the CPU simulator, each resource whose flag in the update position storage table indicates that the update has been completed is stored in the state storage file. If the corresponding flag indicates an update, the state is restored to the state stored in the state storage file. CPU simulator, and corresponding flags are stored in the state storing files If it shows a non-updated, characterized in that a restoration processing means for restoring the state to the initial state. 2. The CP according to claim 1, wherein the resource is a register or an input / output port buffer.
U simulator. 3. The target CPU on which the target program is loaded, wherein the update position storage table is
Of each memory and a flag for each address of the memory of the target CPU used as a work area by the target program, the update position storage circuit loads the target program when the target program is loaded. If the flag corresponding to the updated memory address is not updated when the state of the memory is updated when the simulation is executed, and the flag of each address of the updated memory is updated. When the target program is executed up to a certain point, the storage processing means changes the flag in the update position storage table to indicate that the target program is loaded. Address and memory status of the work area The memory state of the dress is stored in the state storage file, and the restoration processing unit stores in the state storage file for each address of the memory in which the flag in the update position storage table indicates that the update has been completed. When the corresponding flag indicates update, the memory state is restored to the state saved in the state save file, and the corresponding flag saved in the state save file indicates not updated. In that case, the memory state is restored to the initial state.
U simulator.