JPS62297954A - Memory control system - Google Patents

Abstract

PURPOSE:To facilitate the production of a program and to increase the processing speed by adding a control circuit having a function equivalent to that of a relay program. CONSTITUTION:A column latch circuit 6 saves and stores the memory selection data stored in a program latch 3 and also stored again said selection data in the latch 3. Then this selection data stored in the latch 3 is read to the latch 64 of the circuit 6 to be saved and stored for a period during which an instruction stored in a memory under selection produces a call instruction for an instruction stored in another memory and then the execution of the called instruction is started when the memory under selection is switched to another memory in the same address space. Then said memory selection data is stored again in the latch 3 after the executions are through with the called instruction and a series of instructions following said called instruction and a resetting instruction is produced for reset to the instruction given before switching memories. Thus a memory set before switching memories is selected again.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Industrial Field of Application) The present invention relates to a memory control method, and more specifically, the present invention relates to a memory control system that has a memory space larger than that of a microprocessor. This relates to a memory system for controlling the memory i+lI.

(Prior Art) Microprocessors are currently used in many devices, and the capabilities of these N8 devices are becoming more sophisticated year by year. For this reason, there are many cases where the memory capacity of the microprocessor is insufficient, and various memory control methods have been devised to expand the memory space.

However, in the conventional memory control method, the creation of a program is very complicated and the processing speed during execution is also considerably reduced.

FIG. 7 is a block diagram of a microprocessor circuit using a conventional memory control method.

In FIG. 7, main memory 1 is for storing programs for a microprocessor (MPU) 2, and this main memory 1 is connected to a microprocessor (MPU) 2 by a program column latch 3 and a data column latch 4 connected to the data bus. The memory space is expanded from the memory space that the processor 2 originally has.

In other words, the contents of the program column latch 3 and the data column latch 4 can be read or written to 0 through the data bus by the input/output command of the microprocessor 2 and the accompanying write/read pulse IOR/W. . The address of the main memory 1 is determined by decoding the address data output from the address bus of the microprocessor 2 and the outputs of these latches 3.4 by the address decoder 5.

Figure 8 shows the structure of this main memory 1.
Here, the original address space of microprocessor 2 is divided into 64 bytes, that is, addresses 0000-FFFF (
Hexadecimal display - From now on, addresses will be displayed in hexadecimal. ).

The area between addresses 3000 and 3FFF is a stack area used to store a return address at the time of a subroutine call, the area between addresses 4000 and 7FFF is a program data area, and the area between addresses 8000 and FFFF is a program area.

The data area and program area have a column structure, and multiple memories #0 to #3 are assigned to the same address.
Alternatively, #O and #1 are arranged. One of them is selected according to the contents of the data column latch 4 and the program column latch 3.

Consider the case where program A in column number #0 of the program area in Figure 8 calls a subroutine to block B in column number #1.

First, when program A is being executed, it is necessary to change the contents of program column latch 3 to #1 using an input/output command. However, this input/output command cannot be performed within program A. This is because immediately after changing the contents of program column latch 3 from #O to #1, the instruction at the address corresponding to the next instruction of the input/output instruction just executed in program column number #1 is executed. This is because the execution of program A will stop midway. As a result, an instruction that calls program B from program A cannot be executed.

In order to solve this problem, it is necessary to place a relay program within addresses 0000 to 2FFF, which do not have a column structure, and to change the contents of the program column latch 3 in this relay program.

The operation of the relay program will be explained using FIGS. 9(a) and 9(b). After program A executes a certain process 1, if it wants to call block B as a subroutine, it first loads the entry address of program B into the A register in microprocessor 2, and then loads the program column number of program B into another N register. do. After that, call the relay program. By executing this call instruction, the return address to program A is automatically stored in the stack area.

Therefore, the contents of address 3FFF in the stack area are as shown in FIG. Here, data is stored in the stack area by PUSH or POP in order from a high address to a low address.

In the relay program, first the contents of the current program column latch 3 (#O) and the data column latch 4 are
The contents (#1) are stored at addresses 3FFF and 3FFD in the stack area. This operation is performed when program B returns to program A.
This is necessary to return to the program column and data column at the time of calling.

Next, the program column '#I@ of program B stored in the N register is set in the program column latch 3 using an input/output command. Since the relay program is located in a memory area that does not have a column structure, even if the contents of the program column latch 3 are changed, the relay program will not be stopped midway.

The relay program finally calls the address of 70 grams B stored in the A register. By this call instruction, the return address from program B to the relay program is automatically written in the stack area (address 3FFC in FIG. 10).

When program B is executed and a subroutine return instruction is executed at the end, the return address is read from the stack area, and as a result, the program returns to the relay program again.

The relay program sets the data column number and progera l-column number when program A is being executed, stored in the stack area, in data column latch 4 and program column latch 3, respectively, and finally issues a subroutine return instruction. Execute.

As a result, the return address to program A is read from the stack area, and program A is returned.

(Problems to be Solved by the Invention) As described above, in the conventional memory control utl method, when subroutine calls are made to programs stored in different columns, a relay program is required. The problem is that the program has to be carefully designed, making the program design extremely complicated, and that the processing speed of the program is reduced by the amount of the relay program.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method that eliminates the above-mentioned drawbacks, allows easy program creation, and can speed up program execution.

[Structure of the Invention (Means for Solving Problems)] The present invention provides a control circuit that saves and stores memory selection data stored in a latch and re-stores the saved memory selection data in the latch. , When switching the currently selected memory to another memory in the same address space, an instruction stored in the currently selected memory generates a call instruction for an instruction stored in the other memory. The memory selection data stored in the latch is read into the control circuit and saved and stored until execution of the called instruction starts, and execution of the called instruction and a series of instructions following it is completed; When a return command is generated to return to the command before memory switching, the saved memory selection data is stored in the latch again, and the memory before memory switching is selected again.

(Function) For example, when program A stored in memory #0 is branched to a program stored in memory #1 in the same address space, when program A calls program B, a latch is activated when a calling instruction occurs. #O remembered
Memory selection data is saved and stored in the control circuit. Then, when program B returns to program A, when a return command to program A is issued, the #0 memory selection data that was saved in the control circuit is re-stored in the latch, and the #0 memory selection data is re-stored in the latch. Once selected, program A will be executed. In short, by adding a 2-capacity control circuit equivalent to that of the relay program, it is possible to simplify program creation and improve processing efficiency by 3mM.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention,
Components other than the column latch control circuit 6 surrounded by broken lines are basically the same as in FIG. 7.

The control circuit 6 has a column number memory 60. Control 2II pulse generation circuit 61. Instruction read detection circuit 62. Return command detection circuit 63. It is composed of a temporary memory rasochi 64,
Of these, the column number memory 60 has an address relationship with the main memory 1 as shown in FIG. 2, and corresponds to the stack area of the main memory 1. When the microprocessor 2 performs a read/write operation to the stack area of the main memory 1, the contents of the data column latch 4 and program column latch 3 at that time are simultaneously written to the column number memory 60. has been done.

On the other hand, the instruction read detection circuit 62 monitors the Shintan line of the microprocessor 2, detects that the microprocessor 2 sequentially reads instructions from the main memory 1, and detects that the microprocessor 2 sequentially reads instructions from the main memory 1.
As shown in >, a pulse synchronized with the instruction read timing is output. Further, when the microprocessor 2 reads a return instruction, the return instruction detection circuit 63 detects the return instruction as shown in FIG.
As shown in b), a pulse synchronized with the read timing of the instruction is output.

The operations of these circuits will now be explained along the flowchart of FIG.

In FIG. 5, when process 1 of program A is executed and it is desired to call program B as a subroutine next, program A sets the program column number of program B in the temporary storage latch 64 using an input/output command. At this point, the contents of the program column latch 3 have not changed yet, so program A is executed continuously, and the instruction following the input/output instruction is executed. Here, it is assumed that a call instruction (call, issue instruction) to program B is placed as the next instruction.

As shown in FIG. 4(b), the control pulse generation circuit 61 generates a write pulse to the temporary storage latch 64 by executing the input/output instruction 64, and then the next instruction is sent to the microprocessor 2. When the instruction read detection circuit 62 detects that the instruction has been read out, it generates a data transfer pulse shown in FIG. 4(C). Then, the contents of the -verse memory latch 64 are transferred and stored in the program column latch 3.

Through the above operations, when the call instruction to program B in the program is executed, the contents of the program column latch 3 at that point become the column number in which program B is stored. Therefore, the instruction executed next to the call instruction to program B is the instruction at the beginning of program B. Also, due to this call instruction to program B, the column number memory 60 in the same address space as the stack area contains the return address to program A as well as the data column number and program column number at the time of program A execution, as shown in FIG. be remembered.

Next, after executing the process of program B, when a return instruction is finally executed, the execution address of the program returns to the return address for program A stored in the column number memory 60. At that time, the control pulse generation circuit 61 shown in FIG.
), the two types of data transfer pulses are optically stopped, and h
The contents of the RAM number memory 60 are transferred and stored in the program column latch 3 and data column latch 4 after execution of the return instruction.

As a result, the execution address of the program becomes the return address within the program that is executed next to the return and instruction, and the continuation of process 1 of program A is executed as shown in FIG. On the other hand, the data column numbers have also returned to the state immediately before the subroutine call to program B was made.

Therefore, even if the contents of the data column latch 4 are changed in program B, there is no problem at all.

Note that although the above explanation uses a subroutine call as an example, the differences are exactly the same. Needless to say, it is not possible to jump to the IJ plum program.

E. Effects of the Invention 1 As explained above, according to the present invention, subroutines for columns stored in different memories can be called with a very simple procedure, making program creation very easy and It also has the advantage of greatly improving processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprocessor circuit to which the present invention is applied, FIG. 2 is a memory structure diagram showing the address relationship between the main memory and column number memory in the embodiment, and FIGS. 3 and 4. 5 is a time chart for explaining the operation of the column latch control circuit, FIG. 5 is a flowchart showing an example of a program when switching and using memory, FIG. 6 is a diagram showing the contents stored in the column number memory, and FIG. Figure 7 is a block diagram showing the configuration of a microprocessor circuit using a conventional memory control method.
FIG. 9 is a flowchart for explaining the operation of the conventional configuration, and FIG. 10 is a diagram showing the storage contents of the stack area in the conventional configuration. 1... Main memory, 2... Microprocessor,
3...Program column latch, 4...Data column latch, 5...Address decoder, 6...Column latch control circuit. Figure 6 Figure 10 Figure 9 (a) It's 10 miles away! ; ; 1: Figure 9(b)

Claims (1)

[Claims] A plurality of memories are arranged in the same address space, and each memory is individually selected by memory selection data output from a data bus and stored in a latch, and the address in the selected memory is In a memory control system in which address data is specified by address data output from an address bus, the control circuit saves memory selection data stored in the latch and stores the saved memory selection data in the latch again. When switching the currently selected memory to another memory in the same address space, after the instruction stored in the currently selected memory generates a call instruction for the instruction stored in the other memory. , the memory selection data stored in the latch is read into the control circuit and saved and stored until the execution of the called instruction is started, and the execution of the called instruction and the series of instructions following it is completed. The memory control method is characterized in that the saved memory selection data is stored in the latch again by generation of a return instruction to return to the instruction before memory switching, and the memory before memory switching is selected again.