JPS63141105A - Programmable controller - Google Patents

Abstract

PURPOSE:To accelerate a processing, by providing an I/O processor and a memory in a CPU unit. CONSTITUTION:A microprocessor 2 in the CPU unit 1 executes a sequence program based on an input data fetched in a first memory 3, and stores an arithmetic result in the memory 3 as an output data. After the execution of the sequence program is completed, the microprocessor 2 switches a bus 4 on a microprocessor side from the memory 3 to a second memory 7, and adversely, the bus 4 on an I/O processor side from the memory 7 to the memory 3, and transmits a sequence program execution completing signal 11 to the I/O processor 9. And the microprocessor executes the sequence program again based on the input data of the memory 7, and stores the arithmetic result in the memory 7 as the output data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is concerned with input/output control methods for programmable controllers.

[Conventional technology]

One example of a conventional programmable controller is the one shown in Figure 2.

(1) is the O that controls the entire programmable controller.
PU Unity, (2) is Microbrocerisa, (3)
is the memory 1, (4) is the data bus, (5) is the input unit, and (6) is the output unit.

Next, the operation will be explained.

C1' [Microprose I in J Unity Reward (1)
In step (2), the previously programmed sequence program is executed, and its operation is as follows.

First, microbrosé (2) is input (
The input data from 5) is taken into memory 1 (3) all at once.

Next, a sequence program is executed based on the captured input data, and the calculation results are stored in the memory 1 (3). Then, the calculation results stored in the memory 1 (3) are transferred all at once to the output controller (6). This is the CPU
It is executed repeatedly within UNI, , and (1).

[Problem that the invention attempts to solve]

The conventional CPU unit is configured as described above, and executes the sequence program and transfers input/output data in batches in series.1 This reduces the sequence program processing time by the transfer time. One drawback is that it is long.

This invention is intended to solve the above-mentioned problems, and by providing 110 blocks and an additional memory in the CPU Uni-LiD, batch transfer of input/output data can be performed at the same time as the sequence program is executed. The aim is to provide a complete programmable controller capable of
, is there.

[Means for solving problems]

In the programmable controller according to the present invention, a memory is further provided in the CPU unit.

[Effect]

The 110 blocks and Js in this invention have the function of performing batch transfer of input/output data in parallel with execution of a sequence program.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (1) represents the entire programmable controller as 11yIll! (2) is the microprocessor unit, (3) is the memory 1, (4) is the data bus, (5) is the input unit, (6) is the output unit, ( 7) is an additional memory 2, (8) is bus switching, and (9) is an l/U flow that controls input/output data. 11Q11 is a sequence program execution end signal.

Next, the operation will be explained.

First, CPU unit I; (1) I'E's micro-pro 7, lsu (2) micro-pro 7, 'J' side bus (4)
into memory 1 (3), l/(J process/I side bus (
4) is stored in memory 2 (7) and the bus is switched (8).

The micro processor 7 in the CPU unit (1) is
2) is taken into m-v: +) 1 (3) tl,
7 A sequence program is executed based on the two-manpower data, and the result of the calculation is stored in the memory 1 (3) as output data. When the sequence program is finished, the microprocessor 7...I (2) connects the bus (4) on the side of the microprocessor 7 from memory 1 (3) to memory 2 (7), and
On the other hand, 1/Q Brosse.

memory 2 (7) to memory 1 (3)
Then, a sequence program execution end signal (b) is sent to the 110 program (9). Then, the sequence program is executed again based on the input data of the memory 2 (7), and the calculation result is stored in the memory 2 (7) as output data. In the same way, when the sequence program ends, the microblossom page (2
) is Microbrosse, the bus on the Tusa side (4) La Memory 2 (
7) to memory 1 (3), switch the bus (4) on the I10 Broce Lisa side from Memory 1 (3) to Memory 2 (7), and finish executing the sequence program for I10 Broce Lisa (9). ! Send i%(6). In this way, the microbrochure (2) repeats this operation. In parallel with this, the 110 processor (9) directs the bus (4) toward itself and transfers the output data stored in the memory to the output unit (6) in bulk. The input data continues to be taken into the memory from the input unit (5) until the sequence program execution end signal αυ is received.

As described above, the micro-brochure +) (2) and the 110-brochure (9) are processing in parallel. Therefore, it is not necessary for the microprocessor (2) to perform data transfer by only performing bus switching (81) between one sequence program and the next sequence program.

〔Effect of the invention〕

As described above, according to the present invention, an additional memory is provided in the C1'U unit and the execution of the sequence program and the batch transfer of input/output data are performed simultaneously. This has the effect of shortening the sequence program processing speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a programmable controller according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a conventional programmable controller, and FIG. This is a diagram showing the timing of transfer. 1st. @2 (1) in figure is CI
'[]Unit, (2) Half-microphone controller, (3) is memory 1, (41 is data bus, (5) is input unit, (6) is output unit, etc. (7)
is the memory 2, (81 is the bus switching, (9) is the I10 broset, S4+, QG is the bus switching signal %, and αD is the sequence program execution end signal. In addition, the same symbols in the figure indicate the same - or corresponding parts. Hosu.

Claims (1)

[Claims] A programmable controller comprising an I/O processor and a data memory section in a CPU unit, characterized in that the programmable controller can perform batch transfer of input/output data simultaneously with execution of a sequence program.