JPH02304664A - Data output device - Google Patents

Abstract

PURPOSE:To always hold the utilization efficiency of an external device in a prescribed level or above by constituting this device so that an internal data output means outputs internal data to the outside in accordance with a first read-out instruction, and also, the internal data concerned is stored in an internal data storage means, as well. CONSTITUTION:An interface circuit 31 transfers control information obtained from a control signal S1 and an address signal S2 to a control circuit 32, and fetches internal data D0 outputted from a data latching circuit 34. The circuit 32 sends an operation result output instruction to a data arithmetic circuit 33, and sends an internal data output instruction to the circuit 34 in accordance with control information obtained through the circuit 31. When the operation result output instruction is given from the circuit 32, the circuit 33 outputs the data D0 being a result of operation obtained by performing a prescribed arithmetic processing to the circuit 34 and the circuit 31. The circuit 34 stores in advance the data D0 outputted from the circuit 33, and when the internal data output instruction is given from the circuit 32, the data D0 is outputted to the circuit 31.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used for semiconductor integrated circuits that perform data calculation, processing, storage, etc. under control from an external device such as a microprocessor. The present invention relates to a data output device that outputs internal data to the outside.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional integrated data output device that outputs internal data to the outside according to instructions from the outside.

As shown in the figure, the data output device 1 includes an interface circuit 11, a control circuit 12, and a data calculation circuit 13. The interface circuit 11 is connected to the control signal line L
1. It is connected to an external processor 10 via an address signal line L2 and a data signal line L3. Then, a control signal S1 and an address signal S2 are outputted via a control signal line L1, an address signal line L2, respectively, and a data signal S3 is outputted via a data signal line L3.

The interface circuit 11 transmits control information obtained from the control signal S1 and address signal S2 to the control circuit 12, and takes in internal data DO, which is a calculation result output from the data calculation circuit 13.

The control circuit 12 sends a calculation result output command to the data calculation circuit 13 in accordance with control information obtained from the interface circuit 11.

When the data calculation circuit 13 is given an operation result command from the control circuit 12, it performs predetermined calculation processing and outputs internal data DO, which is the calculation result, to the interface circuit 11.

FIG. 5 is a timing diagram showing the operation of the processor 10 to read out the calculation results of the data calculation circuit 13 in the data output device 1 shown in FIG.

The read operation will be explained below with reference to the same figure.

Using the rise of the control signal S1 as a trigger, the interface circuit 11 decodes the contents of the address signal S2 and provides a read command to the control circuit 12 as control information. Upon receiving this, the control circuit 12 sends a calculation result output command to the data calculation circuit 13.

The data arithmetic circuit 13 that has received the arithmetic result output command performs predetermined arithmetic processing, and then outputs the internal data DO, which is the arithmetic result, to the interface circuit 11. Then, the interface circuit 11 outputs the internal data DO to the data signal line L3 as a data signal S3. Furthermore, a data ready signal indicating that the requested internal data DO has been output to the data signal line L3 is output to the processor 10 via a signal line (not shown).

After receiving the data ready signal, the processor 10 receives the data signal S3 from the data signal line L3 from the data calculation circuit 1.
Read the internal data DO which is the result of operation 3.

In this manner, in the process of reading out the calculation result of the data calculation circuit 13 in the data output device 1 by the processor 10, after the processor 10 raises the control signal S1, the data ready signal is output from the interface circuit 11. The processor 10 continues in the standby state until the data ready signal is output, and the processor 10 connects the data signal line L.
Internal data DO, which is the calculation result of the data calculation circuit 13, is read from the data signal S3 of No. 3.

The above-described read processing can be said to be effective if the response speed (mainly arithmetic processing speed) of the data output device 1 to a read command from the processor 10 is fast, since the standby time of the processor 10 described above is short.

FIG. 6 is a block diagram showing another example of a conventional data output device.

As shown in the figure, the data output device 2 includes an interface circuit 21, a control circuit 22, a data calculation circuit 23, and a data latch circuit 24. The interface circuit 21 is connected to an external processor 1o via a control signal line L1, a read mode selection line L4, and a data signal line L3.

Then, a control signal S1 and a read mode selection signal S4 are transmitted via a control signal line L1 and a read mode selection line L4, respectively.
The input/output of the data signal S3 is performed manually via the data signal line L3.

The interface circuit 21 transmits control information obtained from the control signal S1, read mode selection signal 84, and data signal S3 to the control circuit 22, and takes in internal data DO output from the data latch circuit 24.

The control circuit 22 sends a calculation result output command to the data calculation circuit 23 and an internal data output command to the data latch circuit 24 in accordance with control information obtained via the interface circuit 21 .

When the data calculation circuit 23 receives a calculation result output command from the control circuit 22, it performs predetermined calculation processing and then outputs the internal data DO, which is the calculation result, to the data latch circuit 24.

The data latch circuit 24 stores internal data DO output from the data calculation circuit 23, and when an internal data output command is given from the control circuit 22, outputs the stored internal data DO to the interface circuit 21. There is.

FIG. 7 is a timing diagram showing the operation of the processor 10 to read out the calculation results of the data calculation circuit 23 in the data output bag Wt2. The read operation will be explained below with reference to the same figure.

After setting the read mode selection signal S4 to H level and setting the first read mode, when the control signal s1 is raised, the interface circuit 21 decodes the contents of the data signal s3 using the rise of the control signal S1 as a trigger. A latch transfer command is given to the control circuit 22 as control information. Upon receiving this, the control circuit 22 sends a calculation result output command to the data calculation circuit 23.

The data calculation circuit 23 that has received the calculation result output command performs predetermined calculation processing and then outputs the internal data DO, which is the calculation result, to the data latch circuit 24.

As a result, internal data DO is stored in data latch circuit 24.

After sufficient time has elapsed for the data calculation circuit 23 to output the internal data DO to the data latch circuit 24, the read mode selection signal S4 is set to L level to indicate the second read mode, and then the control When signal S1 is raised,
Using the rise of the control signal S1 as a trigger, the interface circuit 21 provides a latch content read command to the control circuit 22 as control information. Upon receiving this, the control circuit 22 gives an internal data output command to the data latch circuit 24.

The data latch circuit 24 that has received the internal data output command outputs the internal data DO to the interface circuit 21. Then, the interface circuit 21 takes in the internal data DO and outputs the internal data DO as a data signal S3 to the data signal line L3.

Thereafter, the processor 10 calculates the calculation result of the data calculation circuit 23 from the data signal S3 of the data signal line L3.
The internal data DO stored in the data latch circuit 34 is read.

In this way, in this conventional example, the processor 10 reads out the calculation results of the data calculation circuit 23 in the data output device 2 by executing an instruction twice. Therefore, the standby time of the processor 10 is the time it takes for the internal data DO output from the data latch circuit 24 to be output as the data signal S3 to the data signal line L3 via the interface circuit 21, which is a sufficiently short time. Become.

In the second read mode, the data calculation circuit 23 is configured to transmit a data ready signal to the processor 10 to notify that it has outputted the internal data DO to the data latch circuit 24, and when this data ready signal is received or received, the data ready signal is sent to the processor 10. It is also conceivable that the control signal S1 is raised after the read mode signal S4 is lowered.

If the response (arithmetic processing) speed of the data output device 2 is slow relative to the operating speed of the processor 10, the read processing described above is performed after the read command in the first read mode is executed, and then the read command in the second read mode is executed. This can be said to be an effective process because the processor 10 can execute other instructions until the process is executed.

[Problems to be Solved by the Invention] However, the two data output devices described above have the following problems.

In the data output device 1 shown in FIG.
After the control signal S1 is raised, the interface circuit 1
It is necessary to continue the standby state until the data ready signal is output from 1.

Therefore, if the response speed of the data output device 1 is slow compared to the operating speed of the processor 10, the above-described waiting time becomes a time that cannot be ignored for the operation of the processor 10, and in the worst case, the system itself including the processor 10 may be stopped. There was a problem in that the usage efficiency of the processor 10 was significantly lowered.

Further, in the data output device 2 shown in FIG. 6, the read operation of the processor 10 is performed by two instructions, thereby reducing the standby time of the processor 10 by the data latch circuit 2.
Since the period is limited to the period until the internal data DO outputted from 4 is outputted to the data signal line L3, the above-mentioned problem can be avoided.

However, if the response speed of the data output device 1 is approximately equal to or faster than the operating speed of the processor 10,
Although the read operation can be performed with a waiting time within an allowable range by one read command, the read operation is not performed by two commands, which reduces the utilization efficiency of the processor 10. was there.

This invention was made in order to solve the above-mentioned problems, and it provides data output that can always ensure a certain level of utilization efficiency of the external device, regardless of the operating speed of the external device such as a processor that performs the read operation. The purpose is to obtain equipment.

[Means to solve the problem]

The data output device according to the present invention includes an internal data output means for outputting internal data to the outside according to a first read command, and a data output device for storing the internal data output from the internal data output means, and a second read command. Accordingly, the apparatus is configured to include internal data storage means for outputting the stored internal data to the outside.

[Effect]

The internal data output means in this invention outputs the internal data to the outside according to the first read command, and also stores the internal data in the internal data storage means, so that the external device reads the internal data from the data output device. After executing the first read command, the internal data may be read by waiting until the internal data is output to the outside, or it may execute another command, etc. without waiting, and then perform the second read command. The internal data stored in the internal data storage means may be read by executing the command, and the internal data can be read in two ways.

〔Example〕

FIG. 1 is a block diagram showing a data output device which is an embodiment of the present invention.

As shown in the figure, the data output device 3 includes an interface circuit 31, a control circuit 32, a data calculation circuit 33, and a data latch circuit 34. The interface circuit 31 is connected to the external processor 10 via a control signal line L1, an address signal line L2, and a data signal line L3. Then, a control signal line L1, an address signal line L
2, a control signal S1 and an address signal S2 are input manually, respectively, and a data signal s3 is outputted via a data signal line L3.

The interface circuit 31 transmits control information obtained from the control signal S1 and address signal S2 to the control circuit 32, and transmits internal data D output from the data latch circuit 34.
It also incorporates O.

The control circuit 32 sends a calculation result output command to the data calculation circuit 33 and an internal data output command to the data latch circuit 34 in accordance with control information obtained via the interface circuit 31.

When the data calculation circuit 33 receives a calculation result output command from the control circuit 32, the data latch circuit 33 transfers the internal data DO, which is the calculation result obtained by performing predetermined calculation processing, to the data latch circuit 33.
and is output to the interface circuit 31.

The data latch circuit 34 stores the internal data DO output from the data calculation circuit 33, and outputs the internal data DO to the interface circuit 31 when an internal data output command is given from the control circuit 32.

FIG. 2 shows the timing of the read operation of the calculation result of the data calculation circuit 13 in the data output device 3 by the processor 10 when the response speed of the data output device 3 is almost equal to or faster than the operation speed of the processor 10. It is a diagram. The read operation in this case will be described below with reference to the same figure.

Using the rising edge of the control signal S1 as a trigger, the interface circuit 31 decodes the contents of the address signal S2 and provides an operation result read command to the control circuit 32 as control information.

Upon receiving this, the control circuit 32 sends a calculation result output command to the data calculation circuit 33.

The data calculation circuit 33 that has received the calculation result output command performs predetermined calculation processing, and then outputs the internal data DO, which is the calculation result, to the interface circuit 31 and to the data latch circuit 34.

Then, the interface circuit 31 outputs the internal data DO to the data signal line L3 as a data signal S color. At this time, a data ready signal indicating that the requested internal data DO has been output to the data signal line L3 is output to the processor 10 via a signal line (not shown).

After receiving the data ready signal, the processor 10 receives the data signal S3 from the data signal line L3 from the data calculation circuit 3.
Read the internal data DO which is the result of operation 3.

In the process of reading out the calculation results of the data calculation circuit 33 in the data output device 3 in this case, after the processor 10 raises the control signal S1, the processor 10 continues to operate until the data ready signal is output from the interface circuit 31. When the standby state continues and the data ready signal is output, the processor 10 converts the data signal S3 of the data signal line L3 into internal data D, which is the calculation result of the data calculation circuit 33.
Reading O.

If the arithmetic processing speed of the data output device 3 is approximately equal to or faster than the operating speed of the processor 10, this waiting time falls within an allowable range and does not reduce the utilization efficiency of the processor IO.

FIG. 3 shows a case where the response speed of the data output device 3 is slow compared to the operating speed of the processor 10.
2 is a timing chart showing a read operation of the calculation result of the data calculation circuit 13 in the data output device 3 according to the data output device 3. FIG. The read operation in this case will be described below with reference to the same figure.

When the control signal S1 rises, the interface circuit 31 decodes the content of the address signal S2, and provides the Wi control circuit 32 with an operation result read command as control information.

Upon receiving this, the control circuit 32 sends a calculation result output command to the data calculation circuit 33.

The data calculation circuit 33 that has received the calculation result self-blade command performs predetermined calculation processing, and then outputs the calculation result, internal data DO, to the interface circuit 31 and to the data latch circuit 34. As a result, internal data DO is stored in data latch circuit 34.

Then, when the control signal S1 is raised again after sufficient time has elapsed for the data calculation circuit 33 to output the internal data DO to the data latch circuit 34, the interface circuit 31 is triggered by the rise of the control signal S1. The content of the address signal S2 is decoded and a latch content read command 6 is given to the control circuit 32 as control information. Upon receiving this, the control circuit 32 gives an internal data output command to the data latch circuit 34.

The data latch circuit 34 that has received the internal data output command outputs the internal data DO to the interface circuit 31. Then, the interface circuit 31 takes in the internal data DO and outputs the internal data Do as a data signal S3 to the data signal line L3.

Thereafter, the processor 10 reads the internal data DO, which is the calculation result of the data calculation circuit 33, stored in the data latch circuit 34 by the calculation result read command from the data signal S3 of the data signal line L3.

In this case, the data calculation circuit 33 in the data output device 3
In the process of reading out the calculation result, the processor 10 performs the read operation twice using two commands, and during the period after the calculation result read command is output until the data calculation circuit 33 outputs the calculation result to the data latch circuit 34, Processor 10 executes other instructions and the like. Thereafter, by outputting a latch content read command and reading the internal data DO stored in the data latch circuit 34, the data calculation circuit 33
The calculation result is being read. Therefore, processor 10
The waiting time is the internal data DO of data latch circuit 3-4.
This is the time it takes for the signal to be output as the data signal S3 to the data signal line L3, which is a sufficiently short time.

Moreover, as in this case, when the arithmetic processing speed of the data output device 3 is slower than the operating speed of the processor 10, even if the read operation is performed by two read commands, two
Since there is an advantage that other instructions can be executed between the read instructions, the utilization efficiency of the processor 10 is improved.

In addition, in the operation of the latch contents read command in this case, the data calculation circuit 33 is configured to transmit a data ready signal to the processor 10 notifying that the internal data DO has been output to the data latch circuit 34, and this data ready signal is transmitted to the processor 10. It is also conceivable to raise the control signal S1 when the signal is received.

In this way, when the data output device 3 of this embodiment is given an operation result read command from the outside, it outputs the operation result obtained from the data operation circuit 33 to the interface circuit 31 and also outputs it to the data latch circuit 34. are doing.

Therefore, the processor lo side can arbitrarily select the processing after giving the operation result read instruction from among the two shown below.

(2) After waiting until the calculation result appears as the data signal S3 on the data signal line L3 via the interface circuit 3, the calculation result is read out (operation shown in FIG. 2).

■ Instead of waiting as in (■), give commands to other devices and perform other processing, and then execute the U-Sochi content read command to retrieve the internal data DO stored in the data latch circuit 34.
The calculation result is read from (operation shown in FIG. 3).

The processor 10 side can appropriately select the processes (1) and (2) described above so as to increase the usage efficiency of the processor 10 by comparing the operating speed of the processor 10 and the response speed of the data output device 3.

Therefore, when reading the calculation results of the data output device 3, the processor 10 can always ensure a certain level of utilization efficiency or higher, regardless of its operating speed.

In this embodiment, the data calculation circuit 34 that outputs a predetermined calculation result is shown as the internal data output means of the data output device, but it is also possible to use a storage means such as a RAM that outputs pre-stored internal data. Alternatively, it may be a means for capturing the output of an externally provided storage means and outputting the captured data in accordance with a read command.

Also, depending on the configuration of the system including the processor 10 or the software that controls the instructions of the processor 10, the data read processing from the data output device (■, ■ above) may be switched for each instruction or depending on the situation. It is also possible.

〔Effect of the invention〕

As explained above, according to the present invention, the internal data output means outputs the internal data to the outside according to the first read command, and also stores the internal data in the internal data storage means, so that the data output device After executing the first read command, the external device that reads the internal data may wait until the internal data is output to the outside and then read the internal data, or it may execute another command without waiting. Then, the second read command may be executed to read the internal data stored in the internal data storage means, and the internal data can be read in two ways.

Therefore, depending on its operating speed, an external device that reads internal data from this data output device may read internal data only by executing the first read command, or may read internal data by executing another read command after executing the first read command. Since it is possible to select whether to execute the second read command after the processing is performed, there is an effect that the utilization efficiency of the external device can always be maintained at a certain level or higher.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data output device which is an embodiment of the present invention, FIGS. 2 and 3 are timing diagrams showing the read operation of the data output device, and FIGS. 4 and 6 are diagrams showing a conventional data output device. A block diagram showing the data output device, FIG.
7 is a timing diagram showing the read operation of the data output device shown in FIG. 6. FIG. 7 is a timing chart showing the read operation of the data output device shown in FIG. In the figure, 10 is a processor, 31 is an ink-face circuit, 32 is a control circuit, 33 is a data calculation circuit, and 34
is a data latch circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Internal data output means for outputting internal data to the outside in accordance with a first read command; and internal data output means for storing the internal data output from the internal data output means, and storing the stored internal data in accordance with a second read command. A data output device comprising an internal data storage means for outputting data to the outside.