JPH031265A - Interface circuit - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU by providing a setting means which can set arbitrary data, and a comparing means for comparing the data set by this setting means and receiving data and outputting a data coincidence interruption request signal to the CPU, when both the data coincide with each other. CONSTITUTION:This circuit is provided with a setting means 11 which can set arbitrary data, and a comparing means for comparing the data set by this setting means 11 and receiving data and outputting a data coincidence interruption request signal to a CPU, when both the data coincide with each other. That is, in the comparing circuit 12, the contents (D7 -D0) of a receiving buffer register 8 and the contents (D7' - D0') of a data setting register 11 are compared at every bit. As a result, only when all the bits coincide, its output signal, namely, the data coincidence interruption request signal becomes an H level through a NAND gate and a NOT gate. In such a way, it becomes unnecessary that the CPU 10 reads out the contents of the receiving buffer register 8 and executes a comparison check, whenever reception is completed, and the load is reduce.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface circuit for an information processing device, and particularly to a receiving section thereof.

[Prior Art] FIG. 3 is a block diagram showing a receiving section of a conventional serial interface circuit. In the figure, 1 is an external clock input terminal, 2 is an internal clock generation circuit, and a selection switch 3 selects one of the clocks. 4 is a reception control circuit which inputs a clock via the selection switch 3 and outputs a reception clock and a reception completion interrupt request signal based on the contents of the control register 5; Reference numeral 6 denotes a data input terminal, and 7 a reception register which takes in serial data manually input to the data input terminal 6 in accordance with a reception clock from the reception control circuit 4, which is constituted by a shift register. Reference numeral 8 denotes a receive buffer register to which data fetched into the receive register 7 is transferred upon completion of reception of a predetermined number of bits. device) 10.

Next, the operation will be explained.

External clock manually input from external clock input terminal l,
Alternatively, either one of the internal clocks generated by the internal clock generation circuit 2 is input to the reception control circuit 4 through the selection switch 3.

The reception control circuit 4 controls generation and stop of the reception clock according to the contents of the control register 5. The control register 5 is connected to the CPU 10 via a data bus 9, and the contents of the control register 5 can be read or rewritten by executing an instruction. i.e. -Cr'U
The start and stop of reception can be controlled by executing the command in step 10. The reception register 7 has a shift register configuration, and takes in the data inputted to the data input terminal 6 into the register in synchronization with the reception clock from the reception control circuit 4. When data of a predetermined length (in this example, 8 bits length) has been received, the contents of the receive register 7 are transferred to the receive buffer register 8. At the same time, the reception control circuit 4 generates a reception completion interrupt request signal to notify the CPU 10 that reception has been completed.

[Problems to be Solved by the Invention] In such a conventional serial interface circuit, when detecting specific data from continuously received data, the CPU updates the receive buffer register every time reception is completed. It was necessary to read the contents and compare them with specific data on the CPU. As a result, the CPU is occupied by the serial interface circuit, or even if the CPU is doing other work in parallel, the work is interrupted by an interrupt every time reception is completed, resulting in a decrease in efficiency. was there.

This invention was made to solve the above-mentioned problems, and aims to provide an interface circuit that can reduce the load on the CPU.

[Means for Solving the Problems] The interface circuit according to the present invention includes a setting means that can set arbitrary data, and compares the data set in the setting means with the received data, and when they match, sends data to the CPU. and comparison means for outputting a read-in request signal.

[Operation] The interface circuit of the present invention has the function of comparing and ticking the received data and the data set in the setting means, so the CPU reads the received data every time reception is completed and performs a comparison tick, as in the conventional case. There is no need to do so.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a receiving section of a serial interface circuit according to the present invention, and the same parts as those in the conventional example shown in FIG. In the figure, 11 is a data setting register connected to data bus 9, and reception buffer register 8
It has the same bit length (in this case, 8 bit length). 1
2 is a comparison circuit that compares the contents of the data setting register 11 and the contents of the reception buffer register 8 bit by bit, and when they match, a data rescue agent loading request signal is sent to C.
Output to PU10.

Next, the operation will be explained.

First, a command to write data to the data setting register 11 is executed by the CPU 10 to set specific target data. In the comparison circuit 12,
The contents of this data setting register 11 and the contents of the reception buffer register 8, that is, the received data, are constantly compared, and when these two contents match, a data rescue agent loading request signal is generated to the CPU 10. .

An example of the configuration of the data setting register 11 and the comparison circuit 12 is shown in FIG. 2. In FIG. 2, a portion surrounded by a dashed line indicates a repetition of the same circuit, and a portion surrounded by a dashed line indicates a repetition of the same circuit, and a portion indicated by a dashed line indicates an inverted signal of WR. The above WR is a write signal that goes to L' level when an instruction to write data to the data setting register 11 is executed.This opens the bidirectional gate of the data setting register 11, and the CPU IQ causes the data bus 9 to be
The data output from B7 to DBO enters the first stage latch part of the register, and when writing is completed, WR becomes L'
When the level returns, the written data is transferred to the second stage latch portion and the contents of the register are updated. Comparison circuit 1
2, the contents of the receive buffer register 8 (D7~
DO) and the contents of the data setting register 11 (D7''~
DO'') is compared bit by bit, and only when all bits match, the output signal, that is, the data match interrupt request signal to the CPU UIO, is set to the ')-I' level via the NAND gate and NOT gate.

As a result of the above, the CPU 10 does not need to read and compare the contents of the receive buffer register 8 every time reception is completed, and the load is significantly reduced.

In the above embodiment, the case where the bark is applied to the receiving register 7 and the receiving buffer register 8 having an 8-bit length is shown, but the present invention can be applied to any bit length.

Furthermore, although the above embodiments have been described with reference to serial interface circuits, they can also be applied to parallel interface circuits.

[Effects of the Invention] As described above, according to the present invention, the interface circuit includes a setting means that can set arbitrary data, and when the data set in the setting means and the received data are compared, Since the CPU is equipped with a comparison means that outputs a data match interrupt request signal to the CPU, when detecting specific data from among continuously received data, it is possible to detect specific data from among data that is continuously received. C)) Since there is no need to read this and compare check with U, CI)
The load on U is reduced and the interface circuit is in operation.
The PU can efficiently execute other jobs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part configuration of a serial interface circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the data setting register and comparison circuit shown in FIG. 1, and FIG. 1 is a block diagram showing the configuration of main parts of a conventional serial interface circuit. FIG. ■ is an external clock input terminal, 2 is an internal clock generation circuit, 3 is a selection switch, 4 is a reception control circuit, 5 is a control register, 6 is a data input terminal, 7 is a reception register, 8 is a reception buffer register, 9 is data Bus, 10 is CPU
(central processing unit), 11 is a data setting register (setting means), and 12 is a comparison circuit (comparison means). In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa (2 idiots) (voluntary)

Claims (1)

[Scope of Claims] An interface circuit that outputs a reception completion interrupt request signal to a central processing unit every time reception of a predetermined number of data is completed, comprising a setting means capable of setting arbitrary data, and a data set in the setting means. An interface circuit comprising comparing means for comparing received data and outputting a data match interrupt request signal to the central processing unit when they match.