JPH04195316A - Power saving circuit - Google Patents

Abstract

PURPOSE:To eliminate a wait time and to the processing speed from decreasing by starting supplying electric power or a clock prior to the operation start of a device according to a detection signal indicating that a CPU reads a specific area of a memory. CONSTITUTION:The CPU 1 sends an address and a read signal to the memory 7 when reading a vector. When a detecting circuit 8 detects a vector for placing a device A2a in operation being read from the address and read signal, a control signal A is outputted to a control circuit A4a. The control circuit supplies the electric power or clock from a supply source A3a to the device A2a. When the detecting circuit 8 detects a vector for placing a device B2b in operation being read, the control circuit operates similarly. A control circuit B4b which receives a control signal B supplies the electric power or clock from a supply source B3b to the device B2b.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a power saving circuit in a battery-powered information processing device.

(Prior Art) In battery-powered information processing devices, efforts have been made to reduce power consumption in order to extend the operating time of the device using batteries.

In electronic equipment, multiple devices with various functions are combined to form a single device, but these devices do not operate all the time, but operate only when their functions are required. However, power consumption remains the same whether the device is operating or not.

Therefore, methods have been adopted to reduce power consumption by turning off the power and clock of devices that are not operating.

Figure 5 shows the power saving method, where 1 indicates the CPU
, 2 is a device, 3 is a power supply or clock supply source (hereinafter simply referred to as a supply source), and 4 is a power supply or clock control circuit (hereinafter simply referred to as a control circuit) that controls the supply/stop of power or clock from the supply source 3 to the device 2. circuit). When the device 2 is not operating, the CPU instructs the control circuit 4 to turn off the power or clock.
The supply of power or clock from the supply source 3 to the device 2 is stopped. Thereby, power consumption in the device 2 can be eliminated. When device 2 operates, CP
When the UI instructs the control circuit 4 in advance to supply power or clock, the supply is started and the device 2 becomes operational.

Instructions from the CPUI to the control circuit 4 are normally given using control signals by software. However, since a command for this control signal is added, it is necessary to change the software, and the change has the drawback of being a heavy burden.

In order to overcome these drawbacks, there is a method in which instructions are given to the control circuit 4 using hardware without placing a burden on the software. Figure 6 shows the method.
Items with the same reference numerals as those in the figures represent the same items. Here, a signal giving an instruction to the control circuit 4 is generated by the access detection circuit 5. That is, by monitoring the signal between the CPUI and the device 2, the device 2 operates, that is, the C
The access detection circuit 5 detects that the device 2 is accessed from the PUI, and based on this, provides an instruction signal to the control circuit 4, thereby starting supply of power or clock to the device 2.

However, in this method, the CPUI is
It is necessary to wait a predetermined period of time when accessing. In other words,
As shown in FIGS. 7 and 8, the power supply or clock is accessed and the control circuit 4 receives a signal instructing the supply of power, etc., until the device 2 can actually operate. In other words, it takes one hour for the power supply or clock to stabilize. For this reason, CPU1
When attempting to access the device 2, it is necessary to wait for one hour, and a Wait circuit 6 for the CPUI to wait is also required. As described above, this method has the problem that the circuit becomes complicated and the execution speed decreases due to waiting time T.

(Problems to be Solved by the Invention) The present invention solves the above-mentioned problems of the prior art. It is a simple circuit that does not require changes to conventional software, and does not reduce execution speed. The purpose is to provide power circuits.

(Means for Solving the Problem) In order to achieve this object, the present invention includes a control circuit that controls the supply of power or a clock to at least some blocks constituting an information processing device, and a control circuit that controls the supply of power or a clock to at least some blocks that constitute an information processing device, and It is equipped with a detection circuit that detects that one or more of the above specific areas has been read and outputs a signal for each specific area, and the control circuit is driven by the signal output from the detection circuit, and the power supply or clock The configuration is such that supply starts.

Further, the specific area is used as an interrupt vector section.

(Function) According to the above configuration, it is detected that the CPU has read a specific area on the memory, and based on the detection signal, the supply of power or clock is started before the device starts operating. , no waiting time required, and of course no software changes.

(Example) Hereinafter, embodiments will be described in detail based on the drawings.

First, the software of an information processing device generally has a configuration as shown in FIG. That is, there is a BIO 312 that operates the hardware 11 constituting the device, a 0313 exists above it, and an application 14 exists above it. There is no direct operation of the hardware 11 from the application 14, and 0313 or some BI
Requests an operation to hardware II through O312. Application 14 is 0313 or BIO31
When making a request to 2, enter INT XX (XX is a number)
This can be executed by specifying a number for a specific device in place of xx in the specific command.

Furthermore, FIG. 3 shows that an application 14 is stored on the memory 7,
This shows how the BIOs 312 and 0813 exist, and are arranged separately together with the vector 15. BIO 812 and vector 15 are fixed by the device. Here, vector means that when the application 14 issues an INTXX command, the software execution process is transferred from the application 14 to the BIO 312.
Or 0313 jump, but data representing the jump location is stored.

FIG. 4 shows the operation flow when the application 14 requests the use of a device. When a device use request occurs on the application (21), the application issues an INTXX command and
8 to request device operation (22). Next, the CPU sets the jump destination by the INT XX (7) instruction to INT
It reads from the vector location corresponding to the number XX in X (23).

The CPU performs processing such as saving register values in order to be able to jump (24). After this, jump to BiO2 or OS (25). The process of operating the device in the jumped BiO2 or O8 is started 26), and the operation is finished (27).Then, the CPU performs processing in order to return the software execution process to the application (28), and Return to jump destination (29), the application receives and receives the results of using the device (3)
0), and moves on to the next process (31).

In the conventional techniques shown in Figures 5 and 6, the supply of power or clock to the device is started by software or hardware at step (26) of the flow in Figure 4, so the device actually operates. I had to wait until it was possible. However, in the present invention, the supply of power or clock to the device is started at step (23) so that there is no need to wait at step (26).

FIG. 1 shows an embodiment of the present invention, where l is CP
U, 2a, 2b are devices A and B, 3a.

3b are power or clock supply sources A and B, 4a;

Reference numeral 4b designates control circuits A and B that control supply/stop of power or clock to the device, 7 a memory shown in FIG. 3, and 8 a detection circuit that detects reading of the vector 15.

At (23) in FIG. 4, when the CPUI comes to read the vector, it issues an address and a read signal to the memory 7. When the detection circuit 8 detects that the vector for operating the device A2a is read from the address and read signal, it outputs the control signal A to the control circuit A4a. The control circuit A4a that has received the control signal A supplies the power or clock from the supply source A3a to the device A2a. The same operation occurs when the detection circuit 8 detects that it has come to read the vector for operating the device B2b. That is, the control circuit B4b which outputs the control signal B from the detection circuit 8 and receives the control signal B supplies the power or clock from the supply source B3b to the device B2b.

In this embodiment, the configuration is not such that the power supply or clock supply is stopped from the operating state, but (27) in FIG.
) at the end of the device operation, a signal to stop the supply of power or clock may be given to the control circuits A and B, or when the devices A and B do not operate for a certain period of time, the supply may be stopped.

(Effects of the Invention) As explained above, according to the present invention, (1) software compatibility can be maintained because there is no change or burden on software;

(2) Since there is no waiting time when starting the operation, it is possible to prevent a decrease in processing speed.

(3) Since no waiting circuit is required, the hardware configuration is simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a configuration diagram of the software of the information processing device; FIG. 3 is a layout diagram of the application, BrO3, O8, and vectors on the memory; FIG. 4 is a flowchart showing the operation when the application requests device use; FIGS. FIG. 6 is a block diagram showing a power saving method in the prior art, and FIGS. 7 and 8 are diagrams showing the waiting time until the power supply or clock becomes stable in the prior art. 1-CPU, 2a, 2b--Debye, 7. A, B. 3a, 3b...Power or clock supply sources A, B. 4a, 4b...power supply or clock control circuit A, B, 7
...Memory, 8...Detection circuit. Patent applicant Ricoh Co., Ltd. Figure 2 Figure 3 Figure 4 Figure 5

Claims (2)

[Claims] (1) A control circuit that controls the supply of power or clock to at least some of the blocks constituting the information processing device, and a control circuit that detects that the CPU reads one or more specific areas on the memory. 1. A power-saving circuit comprising: a detection circuit that outputs a signal for each specific area; and the control circuit is driven by the signal output from the detection circuit to start supplying power or a clock. (2) The power saving circuit according to claim (1), wherein the specific area is an interrupt vector section.