JPH04227519A - Microcomputer system - Google Patents

Abstract

PURPOSE:To provide the microcomputer system which surely realize a power- saving function in a key input wait state by utilizing the execution of a HALT instruction at the time of key input control by a key input routine. CONSTITUTION:A buffer check routine for judging whether or not key input data are stored in a key-in buffer 121 is executed and when the system is in the key input wait state, the HALT instruction is executed. The halt operation by this HALT instruction is reset with an interruption signal from a series- parallel converting circuit 14 or a timer 13. Consequently, the power saving function of a microprocessor 11 is made to function in the key input wait state.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system having a power saving function when waiting for key input.

0002

2. Description of the Related Art In recent years, advances in semiconductor technology have made it possible to construct a high-performance computer system and easily design the system simply by combining a microprocessor and its family of peripheral control LSIs.

By the way, many microprocessors used in personal computers and the like are constructed from N-channel MOS circuits. This N channel MO
The S-circuit system does not take into consideration the power saving function, and tends to relatively increase power consumption when a computer system is constructed. In a computer system, key input data is input from a keyboard, but a state where key input from the keyboard is waited may occur. If there is no power save function, the amount of power consumed increases, so to speak, when the device is in the state of waiting for key input. Particularly in battery-powered microcomputer systems, the power save function is one of the important functions because it is necessary to prolong the battery power supply.

On the other hand, recently, microprocessors configured with CMOS circuits have been developed;
Devices that have a power-saving function that utilizes the low power consumption characteristics of circuits are emerging.

[0005] Such microprocessors include CP
When U executes a HALT command and stops execution of an application program, the power consumption is reduced compared to normal operation, and there are some devices that save power to about 1/10. When executing this HALT command,
Since the number of accesses to the memory is also reduced, the power consumption of the memory is also reduced.

By the way, in a typical microcomputer system, key input control is executed by a key input routine of a BIOS (basic input/output system), as shown in FIG. The key input routine consists of a one-character input routine shown in FIG. 5A and a buffer check routine shown in FIG.

The one-character input routine is a control routine for capturing one character's worth of key-input data (step S11) when key-input data is stored in the key-in buffer (YES in step S10). be. On the other hand, the buffer check routine is a routine for checking whether key input data is stored in the key-in buffer (step S12).

[0008]

[Problem to be Solved by the Invention] In a conventional microcomputer system, a HALT command is inserted during key input control by a key input routine (step S13 shown in FIG. 3(A)) to save power while waiting for key input. It is possible to consider

However, during the single character input routine, H
Even if an ALT instruction is inserted, a buffer check routine is executed first when an application program is executed. Therefore, when there is no key input data in the key-in buffer, that is, in the key input waiting state, the CP
U will perform an operation of checking the key-in buffer. Therefore, the power save function cannot be realized while waiting for a key input.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer system that can reliably realize a power saving function in a key input waiting state by utilizing the execution of a HALT command during key input control by a key input routine. It is in.

[0011]

[Means for Solving the Problems] The present invention provides determining means for determining whether key input data is stored in a key-in buffer means as a microprocessor executes an application program, and a key input waiting state. The present invention is a microcomputer system comprising a halting means for executing a halting operation at times, and a canceling means for canceling the halting operation of the halting means when an interrupt is generated by the interrupt generating means.

0012

According to the present invention, a buffer check routine is executed to determine whether or not key input data is stored in the key-in buffer means, and if the key-in buffer means is in a key input waiting state, a HALT command is executed. The halt operation by this HALT command is canceled by an interrupt from the interrupt generating means. This allows the microprocessor to save power while waiting for key input.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a microcomputer system according to the same embodiment. This system consists of a CPU board 1 and a keyboard unit 3 connected via a serial interface transfer path 2.

The CPU board 1 is equipped with a microprocessor (CPU) 11, a memory unit 12, a timer 13, and a serial/parallel conversion circuit 14. The CPU 11 is composed of a CMOS circuit and has a power saving function by executing a HALT command. The memory unit 12 has a key-in buffer 121 , and stores key input data (key-in data) input from the keyboard unit 3 in the key-in buffer 121 .

The serial/parallel conversion circuit 14 is connected to the keyboard unit 3 through the serial interface transfer path 2, converts serial key input data into parallel data, and transfers the data to the key-in buffer 121. Further, the serial/parallel conversion circuit 14 connects the CPU 11 to the CPU 11 through the interrupt line INT2.
The CPU 11 is connected to the CPU 11 and transfers interrupt signals generated by key input from the keyboard unit 3 to the CPU 11.

[0017] The timer 13 is, for example, a HAL of the CPU 11.
This LSI counts a predetermined timer time from the execution of the T instruction and outputs a timer-out interrupt signal to the CPU 11 via the interrupt line INT1. Next, the operation of this embodiment will be explained.

First, when key input data is input in response to key operations on the keyboard unit 3, it is transferred to the serial/parallel converter circuit 14 through the serial interface transfer path 2. When the serial/parallel conversion circuit 14 receives, for example, 1 byte worth of key input data, the serial/parallel conversion circuit 14 connects the interrupt line INT2
An interrupt signal is output to the CPU 11 through the CPU 11. CPU1
1 is 1 from the serial/parallel conversion circuit 14 in response to an interrupt signal.
Bytes of key input data DATA are stored in memory unit 1.
2 and stores it in the key-in buffer 121. The CPU 11 performs various data processing using the key input data stored in the key-in buffer 121 as the application program is executed.

By the way, the CPU 11 executes key input control using the BIOS key input routine. The key input routine of this embodiment consists of a single character input routine shown in FIG. 2(A) and a buffer check routine shown in FIG. 2(B).

Here, when the CPU 11 executes the application program, it first executes a buffer check routine to check whether key input data is stored in the key-in buffer 121 (step S4). If key input data is stored in the key-in buffer 121 (YES in step S1), a single character input process is executed to capture key input data for one character (
Step S2).

That is, when one character's worth of key input data is input from the keyboard unit 3, the CPU 11 takes in the one character's worth of key input data stored in the key-in buffer 121. The CPU 11 executes various data processes using the obtained key input data for one character as the application program is executed.

Here, after the check processing of the buffer check routine, the CPU 11 checks the H
The ALT command is executed (step S5). This results in
The CPU 11 enters a HALT state in which execution of the program is stopped. This HALT state is canceled by an interrupt signal from the serial/parallel conversion circuit 14 or the timer 13.

In this manner, even if the buffer check routine is executed first with the execution of the application program, the CPU 11 executes the HALT command and enters the HALT state. When this HALT state is canceled by an interrupt signal from the timer 13, for example, the routine shifts to a one-character input routine. In this one-character input routine, if there is no key input data in the key-in buffer,
That is, in the key input waiting state, the CPU 11 executes the HALT command and enters the HALT state (step S3).

Therefore, when in the key input waiting state, the CPU 11 always executes the HALT command and enters the HALT state. This HALT state is canceled by an interrupt signal from the serial/parallel converter circuit 14 or timer 13, and the HALT state
The T state and release will be repeated. As a result, when in the key input waiting state, the device is always in the HALT state, so that the power saving function can be reliably realized and unnecessary power consumption can be reduced.

[0025]

As described in detail above, according to the present invention, the HALT command is always executed during the key input waiting state where no key input data exists, thereby reliably realizing the power saving function during the key input waiting state. can do. Therefore, as a result, unnecessary power consumption can be reduced, and the power consumption of the system can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing main parts of a microcomputer system according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

FIG. 3 is a flowchart for explaining a conventional method.

[Explanation of symbols]

3...Keyboard unit, 11...CPU, 121...Key-in buffer, 13...Timer, 14...Serial-to-parallel conversion circuit.

Claims (1)

[Claims] 1. A microprocessor for executing an application program; keyboard means for generating key input data; key-in buffer means for storing the key input data input by the keyboard means; determining means for determining whether or not the key input data is stored in the key-in buffer means as an application program is executed; halting means for executing a halting operation for stopping execution of the application program by a microprocessor; interrupt generating means for generating an interrupt for the microprocessor; and halting means for halting the halting means when an interrupt is generated by the interrupt generating means. A microcomputer system characterized by comprising a release means for canceling an operation.