AU665354B2 - Power savings with MS-DOS idle loop - Google Patents

Description

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OPI DATE 27/04/93 APPLN. ID AOJP DATE 24/06/93 PCT NUMBER 21455/92 PCT/US92/04405 S1111111 lllllllI 111111 1111llllll I AU9221455 Y (PCT) (51) International Patent Classification 5 (11) International Publication Number: WO 93/06545 GO6F 1/32 Al (43) International Publication Date: 1 April 1993 (01.04.93) (21) International Application Number: PCT/US92/04405 (81) Designated States: AU, CA. JP, European patent (AT, BE, CH, DE, DK, ES, FR, GB, GR, IT, LU. MC. NL. SE).

(22) International Filing Date: 26 May 1992 (26.05.92) Published Priority data: With international search report.

759,024 13 September 1991 (13.09.91) US (71)Applicant: WANG LABORATORIES, INC. [US/US]; 6 One Industrial Avenue, MS 014-B7D, Lowell, MA 01851

(US).

(72) Inventors: BARRETT, David, N. 45 Beverlee Road.

Tyngsboro, MA 01879 MARTIN. Patricia, A. 120 Hayden Road, Groton, MA 01450 (US).

(74) Agents: SHANAHAN, Michael. H. et al.; One Industrial Avenue, MS 014-B7D, Lowell, MA 01851 (US).

(54)Title: POWER SAVINGS WITH MS-DOS IDLE LOOP i

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i Il.Ss| (57) Abstract In a portable computer, a device driver program causes the system to conserve power whenever the processor is idle. The program detects the idle processor via a unique interrupt generated by the operating system's idle loop. After detecting the idle state, the program conserves power usage by slowing the system clock speed and halting the processor. The system returns to its normal operating state when the processor detects an external interrupt. Although an operator action generates an external interiupt, the 55 ms petiodic timer typically awakens the processor. In addition, the program blocks the power saving measures in cases where the operator would notice -performance degradation.

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"r WO 93/06545 PCr/US92/04405 POWER SAVINGS WITH MS-DOS IDLE LOOP Background of the Invention Portable computers allow users to take computing power wherever they go. As portable computers become smaller and lighter, their mobility increases. In addition, a portable computer's usefulness increases as processing power and battery life are increased.

All portables, however, are powered by batteries. The demand for smaller and lighter portables place restrictions on battery size. Presently, the battery pack in a six pound portable computer usually weighs approximately one pound. Thus, a portable computer's size and weight is significantly influenced by the battery. Manufacturers, therefore, are driven to produce portable computers with even smaller batteries.

At the same time, manufacturers are driven to produce more powerful portables. Manufacturers have increased processing speeds and available memory. As a result, portable computers are approaching the capabilities of stationary personal computers. These performance increases, however, place a greater drain on battery power.

A typical battery pack will power a notebook size computer for approximately two hours of continuous use. A portable computer's usefulness, as a result, is limited. By carrying a spare battery pack, a user can extend the portable computers usefulness another two hours. However, the additional battery pack reduces the computer's portability.

o 00 00 0 00 0 0 t0, 0 0 0 o o o 000 o* o a 0 #0 6 0 0 +i e e .0 0 o 0 04 «f a 0 o e o 0 0 0 o a e B O a 0 00004 0 ltn .u i- (J U1 Summary of the Invention In a first aspect the invention provides a data processing system including a processor and having software instructions stored in memory for processing by the processor at a clock frequency, the software instructions including at least one application program, a plurality of system service functions, and anl idle sequence, the processor and software instructions further comprising: a limiter coupled between the programs and the system service functions to identify processing of predetermined system service functions by the processor the predetermined system service functions being subject to substantial degradation upon halting the processor; an idle state detector for automatically detecting processing of the idle sequence; and a sleeper coupled to the limiter and the idle state detector to provide a HALT instruction to the processor the halt the processor when the idle a a astate detector has detected processing of the idle sequence, but the limiter has not identified processing of a predetermined system service function.

Optionally the system further comprises a shared memory area coupled between the limiter and the sleeper, wherein the limiter sets data in a a~ 20 the shared memory area to indicate that a predetermined system service is i a a::being processed by the processor and the sleeper reads data from the shared :memory area. Optionally the idle state detector comprises an interrupt vectr moifie totransfer control to the sepri epnet a predetermined idle ioop interrupt. Optionally the sleeper isan interrupt handler. Optionally the system further comprises software instructions to decrease the clock frequency. Optionally the memory has a power-saving mode entered when no memory accesses are occurring. Optionally the memory is pseudo-static memory.

Optionally the limiter is an interrupt handler responsive to calls to system service functions.

Optionally the processor continues normal operation upon receipt of any interrupt subsequent to the halting of the processor. Optionally the sleeper returns control to the idle sequence upon continuing normal operation.

Optionally the idle sequence generates a predetermined idle loop interrupt.

A 1 fl 1./2 In a further aspect, the present invention provides a method of conserving power usage on a data processing system including a processor and having software instructions stored in memory for processing by the processor at a clock frequency, the software instructions including at least one application program, a plurality of system service functions, and an idle sequence, the method comprising the steps of: identifying processing of predetermined system service functions that are subject to a substantial degradation upon halting the processor; automatically detecting processing of the idle sequence; and providing a HALT instruction to the processor to halt the processor upon detection of the idle sequence except when a predetermined system service function had been identified.

Optionally the step of detecting is the response to a predetermined idle loop interrupt generated by the idle sequence. Optionally the step of providing a HALT instruction is in response to the predetermined idle loop interrupt. Optionally the step of identifying is in response to calls to system service functions.

:i se Optionally the method further comprises before the step of providing 20 a HALT instruction, the step of decreasing the clock frequency upon detection of the idle sequence except when a predetermined system service function had been identified.

In a further aspect, the invention provides a data processing system 2 including a processor and having software instructions stored in memory for processing by the processor, the software instructions including an idle sequence, the processor and software instructions further comprising: an idle state detector for detecting an idle sequence; a sleeper for providing a HALT instruction to the processor to halt processing of software instructions when the idle state detector detects an idle sequence; and an interrupt mechanism to resume processing of software instructions in response to an external interrupt signal. Battery power is conserved by embodiments of the present invention without any effort from the user or any noticeable affect on the computer's performance.

Embodiments of the present invention extend battery life by decreasing the power drain while the portable computer is idle. Whenever 1/3 the operating system waits for an event, it enters an idle sequence.

Embodiments of the present invention takes advantage of the idle sequence.

Embodiments of the invention comprises an idle state detector, which detects an idle sI oa o o* a S a a i 1 WO 93/06545 PCT/US92/04405 2 sequence, and a sleeper, which provides an instruction to halt the processor when the idle state detector detects the idle sequence. In the preferred embodiment, the idle sequence generates a unique interrupt. The unique interrupt, in turn, triggers a specific interrupt handler. By thus detecting the unique interrupt, the specific interrupt handler detects the idle state. The sleeper is implemented as the specific interrupt handler program. Whenever the sleeper program executes, the processor is in the idle state.

In particular, the preferred sleeper interrupt handler reduces the system clock speed, turns down hardware devices having a power saving mode, and halts the processor. The processor remains halted until an external interrupt occurs. After the processor services the external interrupt, processing continues until the processor returns to the idle sequence.

In the preferred embodiment, there are identified situations where executing the sleeper program leads to noticeable performance degradation.

In response, the Applicant's invention includes a limiter, which detects the identified situations and prevents the sleeper from executing. In particular, the limiter sets a flag in shared data while an identified system service i function is executing and maintains a cleared flag otherwise. In the S,,preferred embodiment, both the sleeper and the limiter are interrupt handler I programs installed as device drivers. Application program calls to MS-DOS system services trigger execution of the limiter program. Any program call to the MD-DOS idle sequence causes the sleeper program to execute. *1 Brief Description of Drawings Fig. 1 shows the logical system overview of a normal computer system operating under Microsoft DOS.

Fig. 2 shows the logical system overview of a computer system operating under Microsoft DOS and enhanced by the present invention.

Fig. 3 is a flowchart of the sleeper.

Fig. 4 is a flowchart of the limiter.

Description of the Preferred Embodiment In the preferred embodiment, the portable computer is notebook

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WO 93/06545 PCT/US92/04405 3 sized. The central processing unit (CPU) is an Intel model 80386SX microprocessor, norm&aly operating at 16 MHz. The system is operated under Microsoft DOS (MS-DOS).

Fig. 1 depicts the normal operation of MS-DOS. The Intel family of processors support up to 256 interrupts, numbered 0 through 255. During initialization, the boot strap program creates a table 20 indexed by interrupt number for containing each interrupt's vector transfer address. The boot strap program, MS-DOS 30 and application programs 10 load the vectors for defined interrupts 22,24 into the table 20. The processor services interrupts by transferring control to the interrupt's vector address 22,24 which the processor looks up in the table 20. At the vector address is a program called an interrupt handler. Users, however, can cause a new interrupt handler to execute when the processor services a particular interrupt.

Although there are several methods for implementing interrupt handlers, MS- DOS provides standardized mechanisms. See R. Duncan, Advanced MS-DOS, pps. 207-257 (Microsoft Press 1986).

Application programs 10 communicate with MS-DOS 30 using software interrupts. When an application 10 requests a system service, it issues the system service interrupt 15. The processor reads the vector address 22 for the system service interrupt 15 from the vector table 20 and transfers control to the MS-DOS System Service 35. In the preferred embodiment, the system service interrupt 15 is interrupt number 33 (21 hex).

A code in the AH register identifies the particular system service function 37 requested by the application program The system service function 37 may need to wait for an event. If that is the case, the function 37 enters an idle loop 40. The processor continuously executes the instructions in the idle loop 40 until the awaited event occurs. When the event occurs, control returns to the function 37, which then returns control to the application 10. One instruction in the idle loop 40 is an instruction to issue an idle loop interrupt 45. In the preferred embodiment, the idle loop interrupt 45 is interrupt number 40 (28 hex).

Upon receiving the idle loop interrupt instruction 45, the processor WO 93/06545 PCT/US92/04405 4 transfers control to the idle loop interrupt handler 50 based on the vector address 24. The idle loop interrupt handler 50 executes its software instructions and returns control to the idle loop As depicted in Fig. 2, the present invention installs an MS-DOS Device Driver 90 to modify the interrupt interface for the MS-DOS System Service calls 15 and the idle loop interrupt 45. R. Duncan, supra., discusses the details of implementing device drivers. In particular, the device driver's initialization routine checks the BIOS version, stores the original vector addresses for the system service interrupt 22 and idle loop interrupt 24 in shared data 80, and modifies the vector addresses 22,24 to point to the limiter 60 and sleeper 70 programs. By using the device driver approach, the present invention realizes a reduced memory requirement because MS- DOS reclaims the memory used for the first-time initialization instructions.

The present invention is installed as a character device driver, with the initialization routine coded at the end of the driver. The initialization routine relays its start address to MS-DOS as the first usable memory address.

Therefore, MS-DOS is free to reuse the memory occupied by theo initialization routine.

An application program 10 calls MS-DOS System Services 35 using the system service interrupt 15. The present invention modifies the interrupt interface 20 to include a limiter interrupt handler program 60. Likewise, the instant invention supplies a sleeper interrupt handler program 70 for the idle loop interrupt 45. The limiter program 60 communicates with the sleeper program 70 via shared data Fig. 3 shows the flowchart of the sleeper program 70, which contains the actual power saving instructions. Upon entry, the sleeper program checks 71 the flag in shared memory 80. If the flag is set then the limiter program 60 is restricting the functioning of the sleeper program 70 and the sleeper program 70 does not implement the power saving features. Instead, the sleeper program exits 78 by transferring control to the original idle loop interrupt handler 50 based on the original vector address. On the other hand, if the flag in shared memory 80 is not set then the limiter program 4; I 3 WO 93/06545 PCT/US92/04405 is not restricting the functioning of the sleeper program 70 and the sleeper program 70 implements the power saving features.

In the preferred embodiment, the system clock frequency is decreased to its minimum value. In addition, the preferred embodiment requires there be no floppy disk accesses in progress. Reducing the system clock speed while a floppy disk access is in progress results in a Direct Memory Access (DMA) failure. To prevent a DMA failure, the sleeper program 70 checks 72 a flag maintained by the ROM Basic Input/Output System (BIOS) to see if a floppy disk access is in progress and, if not, the sleeper program 70 reduces 73 the clock speed. Otherwise, the sleeper program 70 does not reduce the clock speed. In eiether case, however, the next step is to enable interrupts 74 so the suspened processor detecis external interrupts. The sleeper program 70 next issues a halt instruction which suspends processor activity. The processor stays suspended until the processor detects an external interrupt.

Halting the processor results in two power saving benefits. First, the 0:o0 halt reduces the amount of transistor switching within the processor itself.

Therefore, the processor requires less power to operate. Second, system bus activity stops. In the preferred embodiment, the portable computer uses o: pseudo-static memory. Pseudo-static memory chips enter a low-power, selfrefresh mode while not accessed, and, once accessed, return to full-power 4 mode. Hereth et al., in U.S. Patent Number 4,710,903, herein incorporated by reference, discuss the operatin of pseudo-static memories in detail.

ooii Because there is no buss activity, there are no memory accesses occurring.

Becuase there are no memory accesses occurring, the pseudo-static "Ia memory automatically goes into the low-power, self-refresh mode.

Therefore, memory decreases its power demands as a direct result of the t: halt instruction 75. These power saving features continue until an external interrupt occurs.

The external interrupt results from a user keystroke, cursor movement WO 93/06545 PCT/US92/04405 6 provided by a mouse, electromagnetic stylus or light pen device, or another hardware event. The most common hardware event to occur and, thus, wake the processor is the periodic system timer, which triggers an external interrupt every 55 milliseconds. Thus, the computer does not remain in the suspended state indefinitely.

A hardware mechanism services 76 the external interrupt. The resulting memory accesses cause the pseudo-static memory to power up.

In the preferred embodiment, a hardware mechanism automatically increases the system clock frequency during processing of the external interrupt. After servicing the interrupt, control returns to the sleeper program at the instruction after the halt instruction. The sleeper program corrects rE-isters 77 reflecting tne system speed. The sleeper program then exits 78 by transferring control to the original idle loop interrupt handler based on the original vector address.

Fig. 4 shows the flowchart of the limiter program 60. Upon entry, the AH register contains the system service function code identifying the particular system service function 37 called by the application 10. Halting the processor during the idle loop 40 degrades several identified system service functions. To reduce visible degradation, the limiter program compares 61 the code in the AH register with the codes corresponding to the identified functions. The identified funrctions are the Character Output (code Auxiliary Output (code Printer Output (code Direct Console Input/Output (code Output Character String (code and Get Input I Status (code 11) functions. If the code in the AH register does not correspond to any identified function, then the limiter program exits by transferring control 62 to the system service interrupt handler 35 based on the original vector address. As a result of the exit, the system service returns directly to the application 10 upon completing the requested function.

On the other hand, if the AH register contains an identified function code then the limiter program 60 signals the sleeper program 70 by setting 63 a flag located in shared memory 80. Next, the limiter program 60 calls 64 the original system service 35 using the original interrupt vector. As a WO 93/06545 PCT/US92/04405 7 result of the call 64, the system service 35 returns control to the limiter program 60 upon completion of the requested function. After control returns r to the limiter program 60, it pushes 65 the results returned from the system service call onto the system stack. The limiter program 60 clears 66 the flag in shared memory 80 and exits by returning 67 to the application program Although this invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

For example, the applicants implemented the limiter program and sleeper program as device driver interrupt handlers. The applicants recognize the interrupt handlers could also be implemented as MS-DOS Term inate-and-Stay- Resident programs. In addition, the operating system code could be modified to include the limiter and sleeper program instructions in-line. Some functions of the limiter and sleeper p.ograms also could be implementted through hardware devices, instead of -5tirely through software instructions.

Although the preferred embodiment relies on a particular hardware arrangement, the invention could be used on any MS-DOS computer with only minor modifications. For example, another computer's DMA implementation might not be affected by a reduction in clock speed. In that case, there would be no need for the sleeper program to check for floppy 4 disk accesses. Another Computer may have additional devices with a software selectable power-saving mode. Software instructions to place these devices into low-power mode could be added to the sleeper program.

'I Furthermore, the invention is not limited to computers using pseudo-static memory. Any computer memory with a low-power mode will benefit from the lack of memory accesses. In any case, any portable computers will benefit from halting the processor while it is idle.

Claims (12)

1. A data processing system including a processor and having software instructions stored in memory for processing by the processor at a clock frequency, the software instructions including at least one application program, a plurality of system service functions, and an idle sequence, the processor and software instructions further comprising: a limiter coupled between the programs and the system service functions to identify processing of predetermined system service functions by thib processor, the predetermined sysfam service functions being subject to substantial degradation upon halting the processor; an. idle state detector for automatically detecting processing of the idle sequence; and a sleeper coupled to the limiter and the idle state detector to provide a HALT instruction to the processor to halt the processor when the idle state detector has detected processing of the idle sequence, but the limiter has not identified processing of a predetermnined system service function.

2. The data processing system of claim 1 further comprising a shared a memory area coupled between the limiter and the sleeper, wherein the limiter sets data in the shared memory area to indicate that a predetermined sytmservice is being prcse by the processor and the sleeper reads data from the shared memory area.

3. The data processing system of claim 2 wherein the idle state detector comprises an interrupt vector modified to transfer control to the sleeper in ,.response to a predetermined idle loop interrupt.

4. The data processing system of claim 3 wherein the sleeper is an interrup~t handler, The data processing system of claim 1 wherein the sleeper further comuprises software instructions to decrease the clock frequency. The data processing system of claim 1 wherein the memory has a power-saving mode entered when no memory accesses are occurring.

7. The data processing system of claim 6 wherein the memory is pseudo-static mremory.

8. The data processing system of claim I wherein the limiter is an interrupt handler responsive to calls to system service functions. I- I 9

9. The data processing system of claim 1 wherein the processor continues normal operation upon receipt of any interrupt subsequent to the halting of the processor. The data processing of claim 9 wherein the sleeper returns control to the idle sequence upon continuing normal operation.

11. The data processing of claim 1 wherein the idle sequence generates a predetermined idle loop interrupt. 12, A method of conserving power usage on a data processing system including a processor and having software instructions stored in memory for processing by the process or at a clock frequency, the software instructions including at least one application prograr., a plurality of system service functions, and an idle sequent, the method comprising the steps of: identifying processing of predetermined system service functions that are subject to a substantial degradation upon halting the processor; automatically detecting processing of the idle sequence; and providing a HALT instruction to the processor to halt the processor 'upon detection of the idle sequence except when a predetermined system service function had been identified.

13. The method of claim 12 wherein the step if detecting is the response to a predetermined idle loop interrupt generated by the idle sequence.

14. The method of claim 13 wherein the step of providing a HALT instruction is in response to the predetermined idle loop interrupt. t 15. The method of claim 12 wherein the step if identifying is in response to calls to system service functions. 25 16. The method of claim 12 further comprising, before the step of :providing a HALT instruction, the step of decreasing the clock frequency upon detection of the idle sequence except when a predetermined system service function had been identified. 4,l ,17. A data processing system including a processor and having software instructions stored in memory for processing by the processor, the software instructions including an idle sequence, the processor and software instructions further comprising: an idle state detector for detecting an idle sequence; a sleeper for providing a HALT instruction to the processor to halt processing of software instructions when the idle state detector detects an idle sequence; and CDA Z -1 -rV O'0 ~Vrok nr an interrupt mechanism to resume processing of software instructions in response to an external interrupt signal.

18. A data processing system substantially as herein described with reference to Figures 2, 3 and 4 of the accompanying drawings.

19. A method of conserving power usage or a data processing system substantially as herein described with reference to Figures 2, 3 and 4 of the accompanying drawings. DATED this 10th day of October 1995 WANG LABORATORIES INC Patent Attorneys for the Applicant: F.B. RICE CO. *0 o so 0. toss *r I o CI *9 941 0* 4( 94SS U J A4 LU ~VT