JPH05298239A - Direct memory access control circuit - Google Patents

Abstract

PURPOSE:To enable DMA transfer between the systems having DMA transfer control functions in a simple constitution. CONSTITUTION:When a DMA control circuit 103 activates a /DREQ signal, a host system 101 or a subsystem 102 activates a /DACK signal. When the /DACK signal is activated, the circuit 103 inactivates a READY signal. Then, the circuit 103 activates the READY signal and the system 101 or 102 inactivates the /DACK signal. This process is defined as one cycle and repeated to carry out the DMA transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA control circuit capable of performing direct memory access (hereinafter referred to as DMA) transfer between systems.

[0002]

2. Description of the Related Art A conventional DMA transfer between a system and an external peripheral device will be described with reference to FIG.

The system shown in FIG. 2 has a function of controlling a DMA transfer, that is, a DMA controller (hereinafter, DM).
It is called AC. ) 202. The operation for DMA transfer will be described below.

First, the CPU 201 in the system instructs the DMAC 202 in the system via the address bus 203, the data bus 204, and the control bus 205 about the processing content. Next, the DMAC 202 follows the address bus 203, according to the processing content instructed by the CPU 201.
The control bus 205 is controlled to perform DMA transfer between the system memory 206 inside the system and the external peripheral device 207 outside the system via the data bus 204.

That is, the DMAC 202 has the control bus 2
In response to a DMA request signal (hereinafter referred to as a DREQ signal) 208 from the external peripheral device 207, the D
MA acceptance signal (hereinafter referred to as / DACK signal) 209
And a signal that controls reading from the external peripheral device 207 (hereinafter referred to as / IORD signal) 210 or a signal that controls writing to the external peripheral device 207 (hereinafter referred to as /
It is called IOWR signal. ) 211 is output. The timing adjustment at this time is performed using the READY signal 212.

For the system memory 206, a signal for designating a memory address via the address bus 203 and controlling reading from the system memory 206 via the control bus 205 (hereinafter referred to as "/ MERD signal") 2
13 or a signal (hereinafter, referred to as / MEWR signal) 214 for controlling writing to the system memory 206 is output.

On the other hand, the conventional DMA transfer between external peripheral devices is described in, for example, Japanese Unexamined Patent Application Publication No.
No. 280257.

[0008]

However, in the above-mentioned prior art, the structure shown in FIG.
Even with the configuration described in Japanese Patent No. 80257, no consideration has been given to DMA transfer between systems.

That is, when the DMA transfer is attempted between the system and the system rather than between the system and the external peripheral device by using the configuration shown in FIG. 2, a standardized data transfer protocol is used. , For example, SCSI (Smal
l Computer System Interface: ANSI X3.131-1986 standard)
It was necessary to prepare complicated dedicated interface hardware and dedicated interface protocol software.

Further, in the configuration described in Japanese Patent Laid-Open No. 2-280257, D between the external peripheral device and the external peripheral device is set.
The MA transfer is only realized by the system having the function of controlling the DMA transfer, and the DMA transfer between the systems has not been realized yet.

An object of the present invention is to provide a DMA control circuit capable of performing DMA transfer between systems with a simple structure.

[0012]

In order to achieve the above object, the present invention provides a first system (hereinafter referred to as a host system) having a function of controlling DMA transfer, and a DMA.
A DMA control circuit is interposed between a second system (hereinafter referred to as a subsystem) having a function of controlling transfer.

The DMA control circuit has, as a first configuration, /
The detection circuit detects the front edge of the DACK signal, and the detection circuit detects that both the DMAC of the host system and the DMAC of the subsystem are in the DMA transfer enable state.

The DMA control circuit has, as a second configuration, first DMA request means for activating a DMA request signal for the host system in response to a DMA start signal or a DMA acceptance signal of the subsystem, and a host. Storage means for storing data output from the system and outputting the stored data to the subsystem, and second DMA for activating a DMA request signal for the subsystem
It consists of request means.

[0015]

The DMA control circuit performs an operation equivalent to that two systems (host system and subsystem) independently execute DMA transfer to the peripheral device.

In the first configuration of the DMA control circuit,
When the / DACK signal is input, the READY signal is generated by the detection circuit that detects the leading edge of the / DACK signal. As a result, the READY signal changes from the ready state to the not ready state. Host system DMA
The READY signal changes from the not ready state to the ready state by the output signal of the detection circuit that detects that both C and the subsystem DMAC are in the DMA transfer enable state. The / DACK signal becomes inactive after waiting for the READY signal to become ready. With the above process, one cycle of DMA transfer is completed.

In the second configuration of the DMA control circuit,
When the host system activates the DMA start signal, the first DMA request means sends D to the host system.
Since the MA request signal is activated, the host system outputs the transfer data. The storage means stores this data and the second DMA request means DMs to the subsystem.
A Start signal is activated. When the subsystem reads the data output by the storage means, it activates the DMA acceptance signal. The first DMA request means sends D to the host system in response to the DMA acceptance signal from the subsystem.
Since the MA request signal is activated, DMA transfer can be performed one after another.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a hardware block diagram showing an embodiment of the present invention.

The DMA control circuit 103 is interposed between the host system 101 and the subsystem 102. It should be noted that both systems have a function for controlling DMA transfer,
That is, it has a DMAC.

The DMA control circuit 103 receives the / H_DACK signals 104, / H_IORD from the host system 101.
Signal 105, / H_IOWR signal 106 from subsystem 102 / S_DACK signal 107, / S_IOR
The D signal 108 and / S_IOWR signal 109 are input, and the H_DREQ signal 110 and H_READY signal 111 are output to the host system 101, and the S_DREQ signal 112 and S_READY signal 113 are output to the subsystem 102, respectively. Further, the data is the H_DATA bus 11 which is the data bus of the host system 101.
4 and subsystem 102 data bus S_DA
It is transferred via the TA bus 115.

The function of the main signal in this embodiment will be described. / H_DREQ signal 110 is DMA
This is a transfer start request signal, and when it becomes the active state (L level), the host system 101 starts the DMA transfer operation.

The / H_DACK signal 104 is / H_DRE
It is a reception signal of the Q signal 110, and / H_DREQ signal 1
When 10 becomes the active state (L level), it becomes the active state and remains active until the transfer of one data is completed.

The H_READY signal 111 is a signal for putting the CPU of the host system 101 into a standby state, and the CPU of the host system 101 sends the H_READY signal 111.
Is in the inactive state (L level), the standby state is set.

The / S_DREQ signal 112 is a DMA transfer start request signal, and the subsystem 102 starts the DMA transfer operation when it enters the active state (L level).

The / S_DACK signal 107 is / S_DRE
It is a reception signal of the Q signal 112, and / S_DREQ signal 1
When 12 becomes the active state (L level), it becomes the active state and remains active until the transfer of one data is completed.

The S_READY signal 113 is a signal for putting the CPU of the subsystem 102 in a standby state, and the CPU of the subsystem 102 is in a standby state while the S_READY signal 113 is in the inactive state (L level).

The DMA transfer control procedure in this embodiment is such that when the / DREQ signal, which is the DMA request signal from the DMA control circuit 103, becomes active (L level), it indicates that the DMA transfer request has been accepted / DACK.
The signal becomes active (L level). And /
When the DACK signal becomes active (L level),
When the READY signal becomes inactive (L level) and then the READY signal becomes active (H level), the / DACK signal becomes inactive (H level).
Level). That is, when the / DREQ signal becomes the active state (L level), the / DACK signal changes from the inactive state (H level) to the active state (L level), and then becomes the inactive state (H level) again. With this process as one cycle, the DMA transfer is repeatedly executed.

FIG. 3 is a block diagram showing a concrete circuit example of the DMA control circuit 103 of FIG. The circuit operation of FIG. 3 will be described with reference to the timing chart of FIG.

In the DMA control circuit 103 of FIG. 3, / DA
A D latch circuit is used as a detection circuit for detecting the front edge of the CK signal.

At the time of resetting the / RESET signal 303 to the L level, the output signal of the AND circuit 304, that is, the / PR signal 312, which is the preset terminal signal of the D latch circuit 301 and the D latch circuit 302, becomes the L level and D In the initial state of the latch circuit 301 and the D latch circuit 302, each Q terminal output (H_READ in FIG. 3) is output.
The Y signal 111 and the S_READY signal 113 themselves. ) Is set to the H level (FIG. 4A). Although the / RESET signal 303 is not shown in FIG. 1, the / RESET signal is input to the DMA control circuit 103 from the host system 101 and the subsystem 102, respectively, and is shown in FIG. 3 based on them. Not generated by wired OR.

Thereafter, the DMA in the host system 101
When C receives a predetermined command from the CPU, the / H_DACK signal 104 indicating that the DMA transfer request is accepted is L
Level (Fig. 4B). That is, the / H_DREQ signal 110 which is the DMA transfer request signal is sent from the DMA control circuit 103 to the host system 101 in FIG. 1, but in FIG. 3, the / H_DREQ signal 11 is sent.
DM in the host system 101 instead of sending 0
The AC automatically sets the / H_DACK signal 104 to the L level by receiving a predetermined command from the CPU using the software DMA request function. This also applies to the subsystem 102.

When the / H_DACK signal 104 becomes L level, the H_DACK signal 306 inverted by the inverting circuit 305 becomes H level (FIG. 4C). D latch circuit 30
1 is the H_DACK signal 306 input to the CLK terminal
Rising edge (Fig. 4C) (that is, / H_DACK
The falling edge, which is the leading edge of the signal 104 (see FIG.
B)), the signal level of the D terminal (fixed to L level) is latched, and the H_READY signal 111 output from the Q terminal is set to L.
Set to level (Fig. 4D).

Further, the data bus buffer 310 opens the bus gate when the / H_DACK signal 104 input to the G terminal is at L level, and is connected to the data bus (H_DATA bus 114) of the host system 101. The bus direction is controlled by the / H_IORD signal 105 input to the DIR terminal.

On the other hand, when the DMAC in the subsystem 102 receives a predetermined command from the CPU, the / S_DACK signal 107, which indicates that the DMA transfer request has been accepted, goes to L level (FIG. 4E) and is inverted by the inversion circuit 307. S
The _DACK signal 308 goes high (FIG. 4). D
The latch circuit 302 uses the S_DA input to the CLK terminal.
Rising edge of CK signal 308 (FIG. 4) (ie,
The signal level (fixed to L level) of the D terminal is latched at the falling edge (FIG. 4E) which is the front edge of the / S_DACK signal 107, and the S_READY signal 113 output from the Q terminal is set to L level (FIG. 4). G).

Further, the data bus buffer 311 opens the bus gate when the / S_DACK signal 107 input to the G terminal is at L level, and is connected to the data bus (S_DATA bus 115) of the subsystem 102. The bus direction is / S_IORD signal 1 input to the DIR terminal.
Controlled by 08.

Data to be DMA-transferred is output from the transfer source system to the DATA bus when the transfer source system sets the / DACK signal to the L level, and then the READY signal of the transfer source system is set to the L level. Become,
The output data is held on the DATA bus as it is because the CPU of the transfer source system is in the standby state. On the other hand, even in the transfer destination system, when the READY signal of the transfer destination system becomes L level, the CPU
Is in a standby state.

The OR circuit 309 is used for the host system 101.
Of the host system 101 and the S_READY signal 11 of the subsystem 102 are detection circuits that detect that both the DMAC of the subsystem 102 and the DMAC of the subsystem 102 are in the DMA transfer enable state.
When 3 and 3 are both inactive (L level),
The output signal of the OR circuit 309 becomes L level. As a result, / P which is a preset terminal signal of the D latch circuit 301 and the D latch circuit 302 is passed through the AND circuit 304.
The R signal 312 becomes L level (FIG. 4C), and the H_READY signal 111 and S_REA which are the outputs of the respective Q terminals.
The DY signal 113 is set to the active state (H level) (FIG. 4).

H_READY signal 111 and S_REA
DY signal 113 is in active state (H level)
(FIG. 4), the CPUs of the host system 101 and the subsystem 102 are released from the standby state,
Start operation again. As a result, the system at the transfer destination takes in the data held on the DATA bus.

Then, / S_ from subsystem 102
The DACK signal 107 becomes inactive (H level) (FIG. 4), and / H_D from the host system 101.
When the ACK signal 104 becomes inactive (H level) (FIG. 4), one cycle of DMA transfer is completed.

In FIG. 3, the DMAC in the system uses the software DMA request function to
Automatically by receiving a predetermined command from / DAC
Although the K signal is at the L level, the DMA control circuit 103
The / DREQ signal may be generated in-house and sent to the system. Further, the / RESET signal 303 is generated by the wired OR based on the / RESET signal from the host system 101 and the / RESET signal from the subsystem 102, but even if generated in the DMA control circuit 103. good.

Next, FIG. 5 shows the DMA control circuit 103 of FIG.
It is a block diagram which shows the other specific example of a circuit. The circuit operation of FIG. 5 will be described with reference to the timing chart of FIG.

Even in the DMA control circuit 103 of FIG. 5, / DA
A D latch circuit is used as a detection circuit for detecting the front edge of the CK signal.

At the time of resetting the / RESET signal 303 to the L level, the output signal of the AND circuit 502, that is, / PR which is the preset terminal signal of the D latch circuit 501.
When the signal 503 becomes L level and the D latch circuit 501 is in the initial state, the Q terminal output 504 is set to H level and the / Q terminal output (in FIG. 5, the H_DREQ signal 110 itself) is set to L level. (Fig. 6A). Although the / RESET signal 303 is not shown in FIG. 1, the / RESET signal is input to the DMA control circuit 103 from the host system 101 and the subsystem 102, respectively, and is shown in FIG. 5 based on these signals. Not generated by wired OR.

Thereafter, the DMAC in the subsystem 102 is
Receives a predetermined command from the CPU, the / S_DACK signal 107 indicating that the DMA transfer request has been accepted goes low (FIG. 6B). That is, in FIG. 1, it is described that the DMA control circuit 103 sends the DMA transfer request signal / S_DREQ signal 112 to the subsystem 102. However, in FIG. 5, instead of sending the / S_DREQ signal 112, the subsystem 102 is sent. DMAC in
Using the software DMA request function,
Automatically / S by receiving a predetermined command from PU
The _DACK signal 107 is set to L level. Note that in FIG. 5, the / S_DACK signal 107 from the subsystem 102 is always / H_DAC from the host system 101.
It goes to L level before the K signal 104.

When the / S_DACK signal 107 becomes L level, the S_DACK signal 507 inverted by the inverting circuit 506 becomes H level (FIG. 6C). D latch circuit 50
1 is the S_DACK signal 507 input to the CLK terminal
Rising edge (Fig. 6C) (that is, / S_DACK
The falling edge that is the leading edge of the signal 107 (see FIG.
(B)), the signal level of the D terminal (fixed to the L level) is latched, the Q terminal output 504 is set to the L level, and the H_DREQ signal 110 that is the / Q terminal output is set to the H level (FIG.
D). When the Q terminal output 504 becomes L level, the S_READY signal 113 which is the output of the AND circuit 505 becomes L level (FIG. 6E).

After that, when the / H_DACK signal 104 becomes L level (see FIG. 6), the AND circuit 502 causes
/ PR which is a preset terminal signal of the D latch circuit 501
Signal 503 goes to L level (Fig. 6), Q terminal output 5
04 is set to the H level, and the H_DREQ signal 110, which is the / Q terminal output, is set to the L level (FIG. 6C).

After that, when the / H_DACK signal 104 becomes H level (FIG. 6), the S_READY signal 113
Becomes the H level, which is the DMA transfer enable state (see FIG. 6).
Nu). In FIG. 5, since the H_READY signal 111 is always at the H level, S_R can be used by both the host system 101 and the subsystem 102 to know the DMA transfer enable state.
Only the EADY signal 113 needs to be detected (the DMA transfer enable state of the host system 101 is / H_DAC
The K signal 104 reflects the S_READY signal 113. ).

The data bus buffers 310 and 311 are also provided.
Is the / H_DACK signal 10 input to each G terminal.
4, when the / S_DACK signal 107 is at L level, the bus gate is opened and connected to the system data bus (H_DATA bus 114, S_DATA bus 115). In addition,
The bus direction is input to each DIR terminal / H_IO
It is controlled by the RD signal 105 and the / S_IORD signal 108.

Therefore, when performing DMA transfer from the host system 101 to the subsystem 102, in the transfer destination subsystem 102, the S_READY signal 113 is in the inactive state (L level), and the CPU is in the standby state. Transfer source host system 101
DM while the / H_DACK signal 107 is at the L level.
The data to be transferred A is output to the H_DATA bus 114. Then, when the S_READY signal 113 becomes active (H level), the CPU of the subsystem 102
Is released from the standby state, starts operation again, and S_DATA
The data on the bus 115 will be fetched.

On the contrary, when performing DMA transfer from the subsystem 102 to the host system 101, the subsystem 10
2 outputs the data to be DMA-transferred to the S_DATA bus 115 when the / S_DACK signal 107 is set to the L level, and then the S_READY signal 113 is set to the L level and the CPU of the subsystem 102 enters the standby state. The output data is retained on the DATA bus as it is. After that, the transfer source host system 1
01, while / H_DACK signal 107 is at L level,
The data on the H_DATA bus 114 will be fetched.

When the / H_DACK signal 104 becomes H level (FIG. 6), the H_DREQ signal 110 becomes H level, and then / S_ from the subsystem 102.
When the DACK signal 107 becomes inactive (H level) (FIG. 6), one cycle of DMA transfer is completed.

In FIG. 5, the / S_DACK signal 107 is automatically set to the L level when the DMAC in the subsystem 102 uses the software DMA request function to receive a predetermined command from the CPU.
The / S_DREQ signal may be generated in the DMA control circuit 103 and sent to the subsystem 102. Also, the / RESET signal 303 indicates that the host system 101
From the / RESET signal and from the subsystem 102
Although it is generated by the wired OR based on the RESET signal, it may be generated in the DMA control circuit 103.

In FIG. 3 and FIG. 5 explained above, / IOW
The R signal is not used in particular, but the direction of the bus buffer is switched, the logical product is obtained with the / DACK signal and DM
It may be used as a detection signal of the A transferable state.

In FIGS. 3 and 5 described above, the DMA transfer mode (single, demand, block), the amount of data (the number of bytes and the number of words) necessary for setting the DMA transfer, the start address of the system memory For etc., by general-purpose communication means such as RS232C,
It is assumed that the systems have already communicated with each other.

FIG. 7 is a hardware block diagram showing another embodiment of the present invention. The DMA control circuit 803 is interposed between the host system 801 and the subsystem 802. Both systems have a function of controlling DMA transfer, that is, a DMAC.

The function of each signal in this embodiment will be described. The / H_DREQ signal 810 is a DMA transfer start request signal, and when in the active state (L level), the host system 801 starts the DMA transfer operation.

/ H_DACK signal 811 is / H_DRE
It is a reception signal of the Q signal 810, and the / H_DREQ signal 8
When 10 becomes active, it becomes active,
It remains active until one data transfer is completed.

The / H_IOW signal 812 is a signal which becomes an active state (L level) when the host system 801 outputs data to the H_DATA bus 814. Validate the data on 814.

The / H_IOR signal 813 is a signal which becomes an active state (L level) when the host system 801 inputs the data of the H_DATA bus 814. Capture data.

The DIR signal 815 is a signal indicating the data transfer direction. When the DIR signal 815 is at the H level, it indicates transfer from the host system 801 to the subsystem 802, and when it is at the L level, it indicates transfer from the subsystem 802 to the host system 801.

The START signal 816 is the DMA control circuit 8
03 operation start request signal (negative pulse), and the DMA control circuit 803 outputs D at the rising edge of the START signal 816.
Start MA transfer control.

The / RESET signal 817 is a signal for the host system 801 to reset the DMA control circuit 803. When the active state (L level) is entered, the DMA control circuit 803 is reset.

The / S_DREQ signal 818 is a DMA transfer start request signal, and when in the active state (L level), the subsystem 802 starts the DMA transfer operation.

/ S_DACK signal 819 is / S_DRE
It is a reception signal of the Q signal 818, and the / S_DREQ signal 8
When 18 is in the active state (L level), the active state is maintained until the transfer of one data is completed.

The / S_IOW signal 820 is a signal which becomes an active state (L level) when the subsystem 802 outputs data to the S_DATA bus 822. The subsystem 802 is at least delayed by the rising edge of the / S_IOW signal 820. Validate the data on 822.

The / S_IOR signal 821 is a signal that is brought into an active state (L level) when the subsystem 802 inputs the data of the S_DATA bus 822, and the subsystem 802 is on the S_DATA bus 822 at the rising edge of the / S_IOR signal 821. Capture data.

FIG. 8 is a block diagram showing a concrete circuit example of the DMA control circuit 803 of FIG. Data selector 93
0, 931, 932, 933 and 934 output the same level as the A terminal to the Y terminal when the S terminal input is at the H level, and the same level as the B terminal when the S terminal input is at the L level to the Y terminal. ..

The host system 801 switches the DIR signal 815 according to the transfer direction, and the data selector 93
The DMA control circuit 803 controls the level of the S terminal input of each of 0, 931, 932, 933, and 934.
Switch the data transfer direction of.

First, the case where the transfer direction is from the host system 801 to the subsystem 802 will be described.

The host system 801 sets the DIR signal 815 to H level before starting the DMA transfer. Therefore,
At this time, (1) the A terminals of the data selectors 930, 931, 932, 933 and 934 are equivalent to being connected to the Y terminals. (2) The 3-terminal negative logic AND circuit 920 has the c terminal input fixed to the L level by the inverting circuit 910. (3) Since the c terminal input of the 3-input negative logic AND circuit 921 is fixed at the H level, the G terminal input of the 3-state D latch circuit 909 is at the H level, and the D terminal output is always in the high impedance state. , Can be omitted.

From the above, the circuit of FIG. 8 is equivalent to the circuit shown in FIG. Note that, in FIG. 9, the same symbols are given to the means representing the same functions as in FIG.

Next, the operation of the circuit of FIG. 9 will be described with reference to the timing chart of FIG. When the / RESET signal 817 is at the L level, the negative logic OR circuits 902 and 9
Both the outputs of 06 become the L level, and the D latch circuit 903
And 904 are reset, and the / H_DREQ signal 810 and the / S_DREQ signal 818 become inactive (H level) (FIG. 10A).

The DMA transfer control is started from the rising edge of the negative pulse of the START signal 816 generated by the host system 801. The negative pulse of the START signal 816 is
C of the D latch circuit 903 through the negative logic OR circuit 901
It is supplied to the LK terminal. The D latch circuit 903 latches the D terminal input (fixed to H level) at the rising edge of the CLK terminal input, and outputs its inverted output from the / Q terminal. Therefore, the / H_DREQ signal 810 becomes active (L level) (FIG. 10B).

When the / H_DREQ signal 810 becomes active, the host system 801 brings the / H_DACK signal 811 indicating that the DMA transfer request has been received into the active state (L level).

When the / H_DACK signal 811 becomes L level, the D latch circuit 90 is passed through the negative logic OR circuit 902.
The CLK terminal input of 3 becomes L level. Then, / H_
The DREQ signal 810 becomes inactive (H level) (FIG. 10C).

The host system 801 sets the / H_IOW signal 812 to the L level and then sets the data to be DMA transferred to the H level.
Output to the _DATA bus 814. That is, H_DATA
The level of the bus 814 is determined (FIG. 10D). The 3-state D latch circuit 908 latches the data on the H_DATA bus 814 at the rising edge of the / H_IOW signal 812 (FIG. 10E).

The D latch circuit 904 outputs the / H_IOW signal 8
At the rising edge of 12, the D terminal input (H level fixed) is latched and its inverted output is output from the / Q terminal. Therefore, the / S_DREQ signal 818 is in the active state (L level) (FIG. 10).

When the / S_DREQ signal 818 goes into the active state, the subsystem 802 brings the / S_DACK signal 819, which indicates that the DMA transfer request has been received, into the active state (L level), and then sets the / S_IOR signal 821 to L level. .. When the / S_DACK signal 819 becomes L level, the CLR terminal input of the D latch circuit 904 becomes L level through the negative logic OR circuit 906.
_DREQ signal 818 is inactive (H level)
become. The 3-input negative logic AND circuit 920 is / S_DAC
Since both the K signal 819 and the / S_IOR signal 821 are L level, the L level is output.

The 3-state D latch circuit 908 keeps the Q terminal output in a high impedance state while the G terminal input (gate signal) is at the H level, but since the G terminal input becomes at the L level, it is latched. Sending certain data from the Q terminal
Output to the _DATA bus 822 (FIG. 10C).

Subsystem 802 uses the / S_IOR signal 8
21 is started and the data on the S_DATA bus 822 is received, and then the / S_DACK signal 819 is set to the H level. Since the G terminal input of the 3-state latch circuit 908 becomes H level, the Q terminal output is returned to the high impedance state (FIG. 10).

When the / S_DACK signal 819 becomes H level, the D latch circuit 903 makes the CLK terminal input becomes H level through the negative logic OR circuit 901.
The EQ signal 810 is set to the active state (L level) (FIG. 10N).

At the start of the DMA transfer control, the / H_DREQ signal 810 was activated at the falling edge of the START signal 816.
RT signal 816 is not required. Subsystem 802 / S
When the _DACK signal 819 rises, / H_DREQ
The signal 810 becomes the active state, and by repeating the operation described above (from FIG.
A transfer is performed.

The amount of transfer data is determined in advance by other communication means not described in the host system 801 and the subsystem 802, and the host system 801
Detects the end of transfer of all data by means of transfer data amount detecting means inside the DMAC.

In the circuit of FIG. 9, the / H_DREQ signal 810 becomes active even after the last data transfer (FIG. 10), but the DMA in the host system 801 is
By setting the transfer data amount in advance by using the transfer data setting function of C, even if the / H_DREQ signal 810 becomes active, DM in the host system 801
Since AC does not accept the / H_DREQ signal 810,
No extra data is transferred.

Further, the host system 801 sets the / RESET signal 817 to the active state (L level) after the completion of the transfer of all data, so that the / H_DREQ signal 810
Can be deactivated (FIG. 10).

Next, a case where the transfer direction is from the subsystem 802 to the host system 801 will be described. The host system 801 sets the DIR signal 815 to the L level before starting the DMA transfer. Therefore, at this time, (1) the B terminals of the data selectors 930, 931, 932, 933 and 934 are equivalent to being connected to the Y terminal. (2) The 3-terminal negative logic AND circuit 921 can be regarded as having a fixed L-level input to the c terminal. (3) Since the c terminal input of the 3-input negative logic AND circuit 920 is at the H level, the G terminal input of the 3-state D latch circuit 908 is at the H level, and the D terminal output is always in the high impedance state. It can be omitted.

From the above, the circuit of FIG. 8 becomes equivalent to the circuit shown in FIG. Note that, in FIG. 11, the same symbols are given to the means representing the same functions as in FIG.

Comparing FIG. 11 and FIG. 9, / S_DACK
Signal 819 and / H_DACK signal 811, / S_DRE
Q signal 818 and / H_DREQ signal 810, / S_IO
W signal 820 and / H_IOW signal 812, / S_IOR
Signal 821 and / H_IOR signal 813, S_DATA bus 822 and H_DATA bus 814 are the same circuit except that the signal names of subsystem 802 and host system 801 are interchanged. Therefore,
In this case, contrary to the case described above, the subsystem 802
Data can be transferred from the host to the host system 801. The transfer procedure is the same as in the case of FIG.

By the way, in the above-described conventional DMA transfer between the system and the external peripheral device, R is used until the DMA transfer process in the transfer destination external peripheral device is completed.
Since the CPU waits due to the EADY signal, the CPU in the transfer source system cannot use the address bus and the data bus, which may interrupt the processing.

However, in the DMA transfer in this embodiment, the DMA controller 803 latches the data from the transfer source system, so that even if the DMA processing in the transfer destination system is not completed, It is not necessary to make the system of (1) wait by READY signal or the like. Therefore, the destination system receives the data and
MA transfer start request signal (/ H_DREQ signal or /
The CPU in the transfer source system can use the address bus and the data bus until the S_DREQ signal) becomes active. Therefore, DM in this embodiment
In the A transfer, the CPU in the transfer source system can perform other processing even during the waiting time when the transfer processing time of the transfer destination system is slow, so that efficient CPU operation can be performed.

In this embodiment, the START signal 81
6 and / RESET signal 817 are both host system 80
However, even if the subsystem 802 or another system occurs, it does not affect the data transfer operation, so that the DMA transfer can be performed normally. Further, the logic circuit may be capable of generating the START signal 816 and / RESET signal 817 from any of the host system 801, the subsystem 802, and other systems.

Further, in FIG. 8, the H_DATA bus 8
14 and S_DATA bus 822 are described as 1 bit each for simplification of description, but 2 bits or more (normal 8
It is clear that the DMA transfer is carried out in the same procedure even if it becomes a bit, 16-bit, 32-bit bus, etc.).

[0093]

According to the present invention, DMA transfer can be performed between systems with a simple configuration. Further, in each system, since the other party's system can be regarded as a mere external peripheral device and DMA transfer control can be performed, transfer software is easy.

[Brief description of drawings]

FIG. 1 is a hardware block diagram showing an embodiment of the present invention.

FIG. 2 is a DMA between a conventional system and an external peripheral device.
It is a block diagram for explaining transfer.

3 is a block diagram showing a specific circuit example of a DMA control circuit 103 in FIG.

FIG. 4 is a timing chart showing the timing of main signals in FIG.

5 is a block diagram showing another specific circuit example of the DMA control circuit 103 of FIG.

FIG. 6 is a timing chart showing the timing of main signals in FIG.

FIG. 7 is a hardware block diagram showing another embodiment of the present invention.

8 is a block diagram showing a specific circuit example of a DMA control circuit 803 in FIG.

9 is a block diagram showing the equivalent circuit of FIG. 8 in the case where the transfer direction is from the host system to the subsystem.

FIG. 10 is a timing chart showing the timing of main signals in FIG.

11 is a block diagram showing the equivalent circuit of FIG. 8 in the case where the transfer direction is from the subsystem to the host system.

[Explanation of symbols]

101 ... Host system, 102 ... Subsystem, 10
3 ... DMA control circuit, 201 ... CPU, 202 ... DMA
C, 206 ... System memory, 207 ... Peripheral device, 30
1, 302, 501 ... D latch circuit, 304, 502,
505 ... AND circuit, 309 ... OR circuit, 305, 30
7, 506 ... Inversion circuit, 310, 311 ... Data bus buffer, 801, ... Host system, 802 ... Subsystem, 803 ... DMA control circuit, 901, 902, 906
... Negative logic OR circuit, 903,904 ... D latch circuit, 9
08,909 ... 3-state D latch circuit, 910 ... Inversion circuit, 920, 921 ... 3-input negative logic AND circuit, 93
0,931,932,933,934 ... Data selector.

Claims (16)

[Claims] 1. A first system and a second system, each of which has a function of controlling a direct memory access (hereinafter, referred to as DMA) transfer, are arranged between the first system and the second system, and between the first system and the second system. The timing of the DMA transfer signal exchanged with each of the two systems is controlled so that D is transmitted between the first system and the second system.
DMA characterized in that MA transfer is performed
Control circuit. 2. The DMA control circuit according to claim 1, wherein, of the DMA transfer signals, a DMA reception signal input from the first and second systems and indicating that a DMA transfer request has been received. First to detect the leading edge
Of the DMA transfer signal and a predetermined signal from the DMA transfer signal, both the first and second systems are DM
A DMA control circuit, comprising: a second detection unit that detects that the A transfer enabled state is set. 3. The DMA control circuit according to claim 2, wherein the first detecting means is a D latch circuit. 4. The DMA control circuit according to claim 2 or 3, wherein the second detection means is an OR circuit, and the predetermined signal is the first and / or second signal.
A DMA control circuit for inputting a ready signal output to the above system. 5. The DMA control circuit according to claim 2, 3 or 4, wherein the ready signal output to the first and / or the second system is used among the signals for DMA transfer. A DMA control circuit characterized in that the first system and the second system are synchronized with each other. 6. The DMA control circuit according to claim 1, wherein among the signals for DMA transfer, a DMA request signal (hereinafter, / H_DREQ signal) output to the first system for requesting DMA transfer. A first DMA requesting means for activating the above), first storing means for storing the data inputted from the first system, and outputting the stored data to the second system, Second DMA request means for activating a DMA request signal (hereinafter referred to as / S_DREQ signal) for requesting DMA transfer, which is output to the second system;
A DMA control circuit comprising: 7. The DMA control circuit according to claim 6, further comprising second storage means for storing data input from the second system and outputting the stored data to the first system. A DMA control circuit characterized by the above. 8. The DMA control circuit according to claim 6, wherein the first DMA request means is the DMA.
Of the transfer signals, the DMA start signal (hereinafter referred to as START signal) input from the first or second system or the DMA acceptance signal (hereinafter referred to as / S_DACK signal) input from the second system Depending on,
The / H_DREQ signal is activated, and the second DMA request means activates the / S_DREQ signal in response to a DMA acceptance signal (hereinafter referred to as / H_DACK signal) input from the first system. A DMA control circuit comprising: 9. The DMA control circuit according to claim 8, wherein when the DMA transfer is performed from the second system to the first system, the first DMA requesting means selects one of the DMA transfer signals. , The START signal or H
A DMA control circuit characterized in that the / S_DREQ signal is activated in response to the _DACK signal, and the second DMA requesting means activates the / H_DREQ signal in response to the / S_DACK signal. 10. The DMA control circuit according to claim 6, wherein the first DMA request unit is the DM.
Of the A transfer signals, the / H_DREQ signal is made inactive in response to a reset signal (hereinafter referred to as / RESET signal) input from the first or second system, and the second DMA requesting means is provided. Is the / RE
A DMA control circuit characterized in that the / S_DREQ signal is made inactive in response to a SET signal. 11. The DMA control circuit according to claim 6, wherein the first storage unit is responsive to a write signal input from the first system among the DMA transfer signals. A DMA control circuit which stores the data input from the first system and outputs the stored data to the second system in response to a read signal input from the second system. .. 12. The DMA control circuit according to claim 7, wherein the second storage unit is configured to perform the second storage in response to a write signal input from the second system among the DMA transfer signals. The DMA control circuit, which stores the data input from the system, and outputs the stored data to the first system according to a read signal input from the first system. 13. The DMA control circuit according to claim 7, wherein the DMA is transferred from the first system to the second system.
The second storage means keeps its output in a high-impedance state when the transfer is performed, and the first storage means when the DMA transfer is performed from the second system to the first system. Is a DMA control circuit which maintains its output in a high impedance state. 14. The DMA control circuit according to claim 6 or 7, wherein the first and / or second system has a START signal generating means for generating the START signal. .. 15. The DMA control circuit according to claim 7, wherein the first and / or second system is the D
Of the MA transfer signals, a signal that distinguishes between the case where the DMA transfer is performed from the first system to the second system and the case where the DMA transfer is performed from the second system to the first system (hereinafter, A DMA having a DIR signal generating means for generating a DIR signal)
Control circuit. 16. The DMA control circuit according to claim 15, wherein among the signals for DMA transfer, the START signal, the DIR signal, and the reset signal (hereinafter, referred to as / RESET signal) are input from the first system. In this case, the first system generates the START signal to start the DMA transfer after finishing the setting of the DMA transfer data amount to the built-in DMA controller and the determination of the level of the DIR signal, and A DMA control circuit characterized in that the / RESET signal is activated after the transfer is completed.