JPH05120204A - Dma control circuit - Google Patents

Abstract

PURPOSE:To provide mutual data transfer between systems which have functions for controlling DMA transfer only by adding a simple circuit. CONSTITUTION:The DMA control circuit 103 consists of a detecting circuit which detects the leading edge of a DMA response signal and a detecting circuit which detects both the DMAC of the host system 101 and the DMAC of the subsystem 102 becoming ready for the DMA transfer. Consequently, the mutual data transfer between the systems which have the functions for controlling the DMA transfer is provided only by adding the simple control circuit 103. The DMA transfer can be controlled while the other system is regarded merely as an external peripheral device, so transfer software is simple.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mutual data transfer between systems having a function of controlling DMA transfer.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional system having a function of controlling DMA transfer. DM in the system
For A transfer, the CPU 201 uses the direct memory access controller (hereinafter referred to as DMAC) 202.
Then, the processing contents are instructed via the address bus 203, the data bus 204, and the control bus 205.
The DMAC 202 performs DMA transfer between the system memory 206 and the external peripheral device 207 via the data bus 204 by controlling the address bus 203 and the control bus 205 according to the processing content instructed by the CPU 201.
The DMAC 202 responds to a DMA request signal (hereinafter referred to as a DREQ signal) 208 from the external peripheral device 207 via the control bus 205 with a DMA response signal (hereinafter referred to as −DA).
It is called CK signal. 209 and a signal for controlling reading from an external peripheral device (hereinafter referred to as "IORD signal") 2
10 or a signal (hereinafter referred to as a —IOWR signal) 211 for controlling writing to an external peripheral device is output. Timing adjustment is performed using the READY signal 212.
Address bus 203 for system memory 206
Via the control bus 205, a signal for controlling reading from the system memory 206 (hereinafter referred to as "MERD signal") 213 or a signal for controlling writing to the system memory 206 (hereinafter referred to as "MEWR"). A signal) 214 is output.

Regarding the DMA control circuit, one related to the present invention is Japanese Patent Laid-Open No. 2-280257.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
A DMA data transfer between systems having a function of controlling A transfer is not considered, and a standardized data transfer protocol such as SCSI (Small Computer Syste) is used.
m Interface: ANSI X3.131-1986 standard). Therefore, complicated dedicated interface
It required hardware and dedicated interface protocol software.
The DMA control circuit described in Japanese Patent No. 280257 only realizes DMA data transfer between external peripheral devices by a system having a function of controlling DMA transfer, and DMA data transfer between systems having a function of controlling DMA transfer. Had not arrived.

An object of the present invention is to realize data transfer between systems having a function of controlling DMA transfer by simply adding a simple control circuit.

[0006]

In order to achieve the above object, the present invention provides a first system (hereinafter referred to as a host system) having a function of controlling DMA transfer and a first system having a function of controlling DMA transfer. A DMA control circuit is interposed between the two systems (hereinafter referred to as subsystems).

The DMA control circuit is basically a DAC.
The detection circuit that detects the front edge of the K signal, and the detection circuit that detects that the DMAC of the host system and the DMAC of the subsystem are both ready for DMA transfer.

[0008]

The DMA control circuit performs an operation equivalent to that two systems (host system and subsystem) independently execute DMA transfer to the peripheral device.

When a _DACK signal is input, a _DAC
The REA is detected by the detection circuit that detects the front edge of the K signal.
Generate a DY signal. As a result, the READY signal changes from the ready state to the not ready state. The READY signal changes from the not-ready state to the ready state by the output signal of the detection circuit that detects that both the DMAC of the host system and the DMAC of the subsystem are in the DMA transfer enable state. Waiting for the READY signal to become ready, the DACK signal becomes inactive. With the above process, one cycle of DMA transfer is completed.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a hardware block diagram for implementing the present invention.

Host system 101 and subsystem 10
The DMA control circuit 103 is interposed between the two.

The DMA control circuit 103 receives the _H_DACK signal 104 and _H_IOR from the host system 101.
The D signal 105, the H_IOWR signal 106, and the subsystem S-DACK signal 107 and the S_I from the subsystem 102.
The ORD signal 108 and the S_IOWR signal 109 are received, and the H_DREQ signal 11 is sent to the host system 101.
0, H_READY signal 111 and subsystem 102
To S_DREQ signal 112, S_READY signal 11
3 is generated. Also, the data is the host system 1
01_data bus H_DATA bus 114, and
The data is transferred via the S_DATA bus 115 which is the data bus of the subsystem 102.

The DMA transfer control procedure in the system is such that a DRE which is a DMA transfer request signal is input as an input signal.
When Q becomes active (H level), it indicates that a DMA transfer request has been accepted as an output signal.
The K signal is activated (L level). ￣ DAC
The K signal becomes active while the READY signal is inactive (L level), and becomes inactive (H level) when the READY signal becomes active. That is, when the DREQ signal becomes active, the DACK signal goes from the inactive state to the inactive state via the active state. This process is 1
As a cycle, DMA transfer is repeatedly executed.

FIG. 3 is a concrete circuit diagram showing one embodiment of the present invention. The circuit operation will be described with reference to the timing chart of FIG.

A D latch circuit is used as a detection circuit for detecting the leading edge of the DACK signal.

D latch circuit 301 and D latch circuit 30
The initial state of 2 is at reset (--RESET signal 303
Becomes the L level. ), The output signal (-PR signal) 312 of the AND circuit 304 becomes L level, that is, the preset terminal signal (-PR signal) 312 of the D latch circuit 301 and the D latch circuit 302 becomes L level, and the Q terminal output (this embodiment). In the example, H_READY signal 111 and S_R
It is the EADY signal 113 itself. ) Is set to the H level (FIG. 4A).

The H_DACK signal 104 is supplied to the inverting circuit 3
It is inverted by 05 and becomes the H_DACK signal 306. D
The latch circuit 301 uses the H_DA input to the CLK terminal.
The rising edge of the CK signal 306 (Fig. 4C), that is,
The signal level (L level) of the D terminal is latched at the falling edge (FIG. 4B), which is the front edge of the H_DACK signal 104, and output from the Q terminal (FIG. 4D). This output signal becomes the H_READY signal 111. Similarly, S_D
The ACK signal 107 is inverted by the inverting circuit 307, and S
It becomes the _DACK signal 308. The D latch circuit 302 is
The rising edge of the S_DACK signal 308 input to the CLK terminal (see FIG. 4), that is, the S_DACK signal 1
D at the falling edge (Fig. 4E), which is the leading edge of 07
The signal level (L level) of the terminal is latched and output from the Q terminal (FIG. 4G). This output signal becomes the S_READY signal 113.

The OR circuit 309 is a DM of the host system.
Both the AC and the subsystem DMAC are detection circuits that detect that the DMA transfer is enabled, and the H_READY signal 111 of the host system and the S_READY signal 113 of the subsystem are both inactive (L Level), the output signal of the OR circuit 309 becomes L level. That is, when either one is in the active state (H level), it becomes H level. As a result, the preset terminal signal (_PR signal) 312 of the D latch circuit 301 and the D latch circuit 302 becomes L level (FIG. 4C) via the AND circuit 304, and the Q terminal is set to H level. That is, the H_READY signal 111
Also, the S_READY signal 113 is set to the active state (H
Level) (Fig. 4).

DAC of host system and subsystem
K signal is inactive (S_DACK signal 10
As shown in FIG. 4, the H_DACK signal 104 in FIG. 4 is in the state shown in FIG. 4L), and one cycle of the DMA transfer is completed.

Data is transferred to the host system data bus (H_DATA bus 114) through the data bus buffer 310 whose bus direction is controlled by the _H_IORD signal 105 and whose bus gate is controlled by the _H_DACK signal 104.
Combine with. Similarly, it is coupled to the subsystem data bus (S_DATA bus 115) via the data bus buffer 311 whose bus direction is controlled by the _S_IORD signal 108 and whose bus gate is controlled by the _S_DACK signal 107.

In the embodiment of FIG. 3, the DMA from the peripheral device
Although the software DMA request function which is the function of the DMAC is used as the DREQ signal which is the transfer request signal, it may be individually generated by the I / O port of the system. _RESET signal 30 in the embodiment of FIG.
Although 3 is generated by a wired OR of the host system RESET signal and the subsystem RESET signal, it may be generated by the system I / O port.

Another embodiment of the present invention will be described with reference to the concrete circuit diagram of FIG. 5 and the timing chart of FIG.

A D latch circuit is used as a detection circuit for detecting the front edge of the DACK signal.

The initial state of the D latch circuit 501 is at reset (when the RESET signal 303 becomes L level).
The output signal (--PR signal) 503 of the AND circuit 502 is L
That is, the level, that is, the preset terminal signal (_PR signal) 503 of the D latch circuit 501 becomes L level, the Q terminal output 504 is at H level, and the _Q terminal output (in this embodiment, H level).
This is the _DREQ signal 110 itself. ) Is set to L level. The S_READY signal 113 is output from the Q terminal 5
04 and _H_DACK signal 104 as input, AN
The output signal of the D circuit 505 is used, and the initial state is H
It is a level (Fig. 6A).

The S_DACK signal 107 is supplied to the inverting circuit 5
It is inverted by 06 and becomes the S_DACK signal 507. D
The latch circuit 501 uses the S_DA input to the CLK terminal.
The rising edge of the CK signal 507 (Fig. 6C), that is,
The signal level (L level) of the D terminal is latched at the falling edge (FIG. 6B), which is the front edge of the S_DACK signal 107, and is output from the Q terminal and the Q terminal (FIG. 6D).
The output signal from the Q terminal is the H_DREQ signal 110
Become. The S_READY signal 113 is output from the Q terminal 504.
Is the output signal of the AND circuit 505 that receives the _H_DACK signal 104 as an input, and thus becomes the L level (see FIG. 6).
E). When the _H_DACK signal 104 becomes L level (Fig. 6), the preset terminal signal (_PR signal) 503 of the D latch circuit 501 is set to L level via the AND circuit 502 (Fig. 6G), and the Q terminal. The output 504 is set to H level and the Q terminal output is set to L level (Fig. 6C). Further, the S_READY signal 113 becomes H level which is a DMA transferable state when the H_DACK signal 104 becomes H level (FIG. 6L) (FIG. 6N). In the present embodiment, the H_READY signal 111 is always at the H level, so that both the host system and the subsystem DMA.
Only the S_READY signal 113 needs to be detected to know the transferable state. (The DMA transfer enable state of the host system depends on the H_DACK signal 104.
It is reflected in the READY signal 113. ) S_DA
One cycle of the DMA transfer ends when the CK signal 107 is in the inactive state (FIG. 6).

The state of data combination is the same as that of the embodiment shown in FIG. 3, and therefore the description thereof is omitted here.

In the embodiment of FIG. 5, S_DREQ which is a DMA transfer request signal from the peripheral device in the subsystem.
As a signal, software DMA which is the function of DMAC
Although the request function is used, it may be generated by the I / O port of the system.

In the embodiment described above, the _IOWR signal is not particularly used, but it is used for the direction switching of the bus buffer, the logical product of the _DACK signal and the detection signal of the DMA transfer enable state, and the like. Good.

In the embodiment described above, DM
Regarding the DMA transfer mode (single, demand, block), the amount of data (the number of bytes, the number of words), the start address of the system memory, etc. necessary for setting the A transfer, the general communication means such as RS232C can be used to inter-system transfer. Therefore, it is assumed that communication has been completed in advance.

[0031]

According to the present invention, mutual data transfer between systems having a function of controlling DMA transfer can be realized only by adding a simple control circuit.

Further, as the system, the DMA transfer can be controlled by regarding the other system as a mere external peripheral device, so that the transfer software is easy.

There are effects such as the following.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional system having a function of controlling DMA transfer.

FIG. 3 is a specific circuit diagram showing an embodiment of the present invention.

FIG. 4 is a timing chart diagram in the embodiment of FIG.

FIG. 5 is a specific circuit diagram showing another embodiment of the present invention.

FIG. 6 is a timing chart diagram in the embodiment of FIG.

[Explanation of symbols]

 101 ... Host system, 102 ... Subsystem, 103 ... DMA control circuit, 201 ... CPU, 202 ... DMAC, 206 ... System memory, 207 ... Peripheral device, 301, 302, 501 ... D latch circuit, 304, 502, 505 ... AND circuit, 309 ... OR circuit, 305, 307, 506 ... Inversion circuit, 310, 311 ... Data bus buffer.

Claims (4)

[Claims] 1. A DMA between an external peripheral device and a system memory.
Two independent systems with a built-in DMA controller for controlling the transfer, a detection circuit interposed between the two independent systems to detect the leading edge of the DACK signal, and the two independent systems both perform the DMA transfer. In a system including a DMA control circuit configured by a detection circuit that detects that the DMA is enabled, the DMA
A DMA control circuit, wherein the control system allows the independent systems to consider the other systems as external peripheral devices and perform DMA transfer. 2. The DMA control circuit according to claim 1, wherein a D latch circuit is used as a detection circuit for detecting the leading edge of the DACK signal. 3. The two independent systems are both D
3. The DMA control circuit according to claim 1 or 2, wherein an OR circuit which receives the READY signal of the independent system is used as a detection circuit for detecting that the MA transfer is possible. 4. Between the two independent systems,
4. The DMA control circuit according to claim 1, wherein synchronization between systems is performed by using a READY signal.