JPS61223968A - Data controller for multi-microprocessor - Google Patents

Abstract

PURPOSE:To improve the efficiency of data communication by using a processor to receive an input/output macro-command, decoding and executing it and applying data transfer control with other processor through an external bus. CONSTITUTION:An I/O control circuit 14 receives an input/output macro- command to apply data communication with other processor through an external bus BUS via a CPU local bus interface circuit 141 from a processor (CPU) (not shown). The said command is decoded by an input/output macro-command decoding section 142 and sent to a command execution section 143. Then a DMA control section 144, an interrupt control section 145 and an external bus I/O control section 146 are controlled so as to apply data communication by using an external bus BUS.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a data controller for a multi-microprocessor for efficiently transferring and controlling data when forming a multi-microprocessor. This relates to a system that allows data transfer operations and data transfer control to be performed all at once without using software.

[Technical background of the invention and its problems] When a multi-microprocessor is conventionally formed,
The most important issue is to efficiently transfer and control data. This data transfer and control includes high-speed data transfer (DMA, direct memory access) control, data interleaved control, data synchronization, and the like. Conventionally, a method has generally been adopted in which circuits for the above-mentioned data transfer and control are separately provided and controlled by software of each CPU (central processing unit). The configuration of a conventional data transfer and control means is shown in FIG.

That is, in this data transfer and control means, the CPU
11, a first circuit consisting of a memory 12 and a bus control circuit 13;
a second data processing section B consisting of a CPU 21, a memory 22 and a bus control circuit 23;
Data bus (common bus)
One function is completed by transmitting all commands, parameters, control data, and original data to the second data processing section B through the second data processing section B. Therefore, the CPLJll software distinguishes between these attributes and controls each one. However, in such conventional data transfer and control means, C
This is extremely inefficient because the software load on the PU increases each time one function is added.

[Object of the Invention] This invention was made to improve the above-mentioned problems, and provides a data controller for a multi-microprocessor that can efficiently communicate data in a multi-processor format. The purpose is to

[Summary of the Invention] That is, a data controller for a multi-microprocessor according to the present invention includes an interface circuit for inputting macro commands generated in an arithmetic unit, and a type of macro command input to the interface circuit. It has an input/output macro/command interpreter that discriminates and extracts preset input/output execution command data according to the discriminated type, and a plurality of input/output operation functions. The present invention is characterized by comprising a command execution unit that selectively executes an input/output operation function based on input/output execution command data.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. However, in FIG. 1, the same parts as in FIG. 3 are denoted by the same reference numerals, and only the different parts will be described here. -Figure 1 shows its configuration,
The first and second data processing units A and B are provided with an input/output (Ilo) control circuit 14°24 instead of the bus control circuits 13 and 23, and the CPtJ11.21
generate one macro command each from I1.
By inputting to the 0 control circuit 14.24, each CPU
I10 control circuit 14 performs data transfer and control of 11 and 21.
It is designed to be entrusted to ゜24.

FIG. 2 shows the configuration of the I10 control circuit 14. In the figure, reference numeral 141 is a CPU local bus interface circuit that performs I10 control of the CPU 11 and data. is input to the input/output macro command interpreter 142 via this interface circuit 141. This input/output macro command interpreter 142 determines the type of input macro command, and extracts preset I10 execution command data according to the determined type.This I10 execution command data is used to execute commands. The information is input to section 143. The command execution unit 143 executes the I10 control unit 144, the interconnected control unit 145, the external path I10 control unit 146, etc. based on the input I10 execution command data.
10 operations are selected and executed.

That is, each I10 control circuit 14.24 has a CP
Interprets macro commands from U11.21 and selects and executes corresponding I10 operations. Therefore, each CPtJ11.21 becomes completely unrelated to I10 operations. In addition, the DMA control section 144 in the I10 control circuit, the interconnected control section 145, and the external path I1
I10 operations such as the 0 control unit 146 can also be integrated into one chip by forming all major functions on one semi-custom integrated circuit (IC).

Here, a DMA macro command will be explained as an example of the above-mentioned macro command. This DMA macro command includes ■parameters (number of transfers, initial address...These parameters are stored in the memory 12. It is made up of two things: 1) and 2) run command. Here, the parameters in ■ should normally be initialized in the CPLJ's I10 routine, but in this case we are assuming a microprocessor or real-time device, so the parameters are coded to lighten the burden on the software. By doing so, it is also possible to refer to it from within the memory 12. This also applies to the second data processing section B.

Therefore, the multi-microprocessor data controller configured as described above can automatically execute a series of I10 controls and I10 operations by generating input/output macro commands from the CPU <processor. The I10 operation includes DMA, interconnected, data cycle, data check, etc., and when housed in one single chip IC, it can be used as a small and inexpensive multi-microprocessor. In other words, in the conventional system, CPLI software was involved for each input/output function, resulting in considerable overhead, but if the I10 control circuit is housed in this one-chip IC as described above, multi-CPU
This enables efficient data transfer between the two.

[Effects of the Invention] As described in detail above, the present invention can provide a data controller for a multi-microprocessor that can efficiently communicate data in the form of a multi-processor.

[Brief explanation of drawings]

FIG. 1 is a block circuit configuration diagram showing an embodiment of a data controller for a multi-microprocessor according to the present invention, FIG. 2 is a block circuit diagram showing the configuration of an I10 control circuit of the same embodiment, and FIG. 1 is a block circuit diagram showing the configuration of a conventional multi-microprocessor data controller; FIG. 11, 21...-CPLJ, 12.22...Memory,
13.23...Bus control circuit, 14.24...I1
0 control circuit, 15... data bus. Applicant's agent Patent attorney Takehiko Suzue 1F9F Mu, 14 Figure 3 u5

Claims (1)

[Claims] In a multi-microprocessor data controller used in a multi-microprocessor having a plurality of arithmetic units and controlling transfer of various data processed by the arithmetic units via an external bus, a macro command generated in the arithmetic unit an input/output macro command interpreter that determines the type of macro command input to the interface circuit and extracts preset input/output execution command data according to the determined type; A multifunction device having a plurality of input/output operation functions and a command execution unit that selectively executes an input/output operation function based on input/output execution command data extracted by the input/output macro command interpretation unit.・Data controller for microprocessor.