JPH02135513A - Data processor - Google Patents

Abstract

PURPOSE:To speed up the processing by providing a means to execute the setting control of the CPU processing speed of a clock control circuit in accordance with a special key input and a means to execute the setting control of the bus timing of a bus control circuit in accordance with other special key input, recognizing the key input with a CPU, and independently setting the environment for a bus and the CPU. CONSTITUTION:When a special key operation such as a special function key input form a keyboard is executed, a CPU 2 decides the instruction contents. When the instruction contents are the instruction concerning the processing speed of the CPU 2 itself, the CPU 2 sets and controls the clock timing of a clock control circuit 5, and when the special key input is the instruction concerning the processing speed of a bus 1, the CPU 2 sets and controls the bus timing of a bus timing control circuit 6 and the CPU2 controls the processing speed of the bus. In such a way, in accordance with the situation, the bus and CPU environment to use the feature is selected and the processing as a whole can be accelerated.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention enables the CPU processing speed and bus timing to be set independently of each other, and enables the CPU processing speed and bus timing to be set independently of each other.
The present invention relates to a data processing device that can set a PU environment.

(Prior art) With recent advances in semiconductor technology, microprocessors,
Memory and LSI became available at very low prices,
It has become possible to construct a relatively high-performance data processing device simply by appropriately combining these LSIs.

Incidentally, in the data processing apparatus described above, there is a synchronous relationship between the processing speed of the CPU and the processing speed of the bus. That is, since the same clock is used, the processing speed is left to the CPU clock, and if the CPU is fast, the bus is also fast, and if the CPU is slow, the bus is also slow.

In other words, the relationship between the mutual processing speeds of the CPU and the bus is such that both are fast or both are slow.

(Problems to be Solved by the Invention) However, in the conventional data processing device in which the CPU and the bus have a mutual processing speed relationship as described above, there are the following problems. That is, if both the CPU and the bus are operated at a high speed level, there will be an inconvenience that access will fail.

Also, if you want to take advantage of an option card, both the CPU and bus must operate at a slow level.

Therefore, in the conventional configuration described above, the capability of the CPU is not fully utilized. Furthermore, in order to maintain compatibility, some application software cannot be used unless the processing speed is the same as that of previous models.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a data processing device that can process option cards, application software, etc. faster and more efficiently.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a clock control circuit and a bus control circuit that control the processing speed and bus timing of a CPU according to a specific key input, and This feature is characterized in that by recognizing each, an independent bus/CPU environment can be set.

(Function) As described above, the present invention is characterized by dynamically and separately controlling the CPU processing speed and bus timing by recognizing specific key inputs. The clock control circuit that controls the bus timing and the bus timing control circuit that controls the bus timing are separately controlled by the CPU.

This realizes a state in which both the CPU and the bus are fast and both slow, as well as a state in which one of the CPU and the bus is fast and the other is slow.

As a result, even in the case of an option card that cannot withstand fast access, only the access is slow and subsequent processing can be sped up. Furthermore, if fast processing is not required during execution, unnecessary time during access can be omitted by slowing down the CPU speed and increasing access speed. In other words, it is possible to select a bus/CPU environment that takes advantage of the characteristics depending on the situation, thereby speeding up the overall processing.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a bus, which exchanges data between the following components. A CPU 2 controls the entire system including clock timing setting control of a clock control circuit and timing setting control of a bus timing control circuit, which will be described later. 3 is the standard input/output device,
Generally, a keyboard (KB), CRT, printer, etc. are connected.

4 is a connector of the option card, which is a connection terminal for connecting with the option card. A clock control circuit 5 controls the processing speed of the CPU. A bus timing control circuit 6 performs bus timing control under the control of the CPU 2.

The operation of the embodiment of the present invention shown in FIG. 1 will be described below.

When a specific key operation, such as inputting a specific function key from the keyboard (KB), is performed, the CPU 2 determines the contents of the instruction.

Here, if the instruction content is an instruction regarding the processing speed of the CPU 2 itself, the CPU 2 sets and controls the clock timing of the clock control circuit 5 according to the instruction content, and the CPU 2
U2 controls the processing speed of its own CPU through the clock control circuit 5.

Further, if the specific key input is an instruction regarding the processing speed of the bus 1, the CPU 2 sets and controls the bus timing of the bus timing control circuit 6 according to the contents of the instruction, and the CPU 2
2 controls the processing speed of the bus, such as access to an option board via the connector 4, through the bus timing control circuit 6.

By having such an independent timing setting control mechanism for the CPU and the bus, even in the case of an option card that cannot withstand high-speed access, only the access can be slowed down and subsequent processing can be sped up. Furthermore, if fast processing is not required during execution, unnecessary time during access can be omitted by slowing down the CPU speed and increasing access speed. That is, depending on the situation,
By choosing a bus/CPU environment that takes advantage of these characteristics, you can speed up the entire process.

[Effects of the Invention] As explained above, according to the present invention, the CPU and the CP
A clock control circuit that determines the processing speed of U, and the CP
In a data processing device comprising a bus control circuit that controls bus timing under the control of a U, means for setting and controlling a CPU processing speed of the clock control circuit in accordance with a specific key input, and another specific key input. A means for setting and controlling the bus timing of the bus control circuit according to the input is provided, and the CPU recognizes the key input and has the function of independently setting the bus and CPU environments. Even in the case of an option card that cannot withstand fast access, only access can be slowed down and subsequent processing can be sped up. Further, even when fast processing is not required during execution, unnecessary time during access can be omitted by slowing down the CPU and speeding up access. In other words, it is possible to select a bus/CPU environment that takes advantage of the characteristics depending on the situation, improving system throughput.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Bus, 2... CPU, 3... Standard input/output device, 4... Option card connector, 5... Clock control circuit, 6... Bus timing control circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A data processing device comprising a CPU, a clock control circuit that determines the processing speed of the CPU, and a bus control circuit that controls bus timing under the control of the CPU, the data processing device controlling the clock according to a specific key input. Control circuit C
It is equipped with means for setting and controlling the PU processing speed, and means for setting and controlling the bus timing of the bus control circuit according to other specific key inputs, so that the CPU recognizes the key inputs and the environments of the bus and CPU are independent. A data processing device characterized in that it is configured as follows.