JPH05289713A - Programmable controller - Google Patents

Abstract

PURPOSE:To fetch an input signal through a reset input terminal of a counter when the terminal is not used. CONSTITUTION:A counter circuit 6 which can decide the input or the non-input of the reset input signal, an E<2>PROM 5 which decides whether a reset input terminal X6 to which the reset input signal of the circuit 6 is supplied is used as a normal input terminal or not are provided. Then a CPU 1 fetches the signal of the terminal X6 as an input signal when the circuit 6 decides the non-input of the reset input signal and when the E<2>PROM 5 decides to use the terminal X6 as a normal input terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter referred to as a PC) having a built-in counter, and more particularly to use of a reset input terminal of the counter.

[0002]

2. Description of the Related Art Conventionally, a reset signal and a counter signal are input to a high-speed counter incorporated in a PC of this type, but they are taken from dedicated terminals. However, depending on the application of the system, the reset input may not be used even if the high speed counter is used. Even in such a case, the terminal took in only the reset input and the user could not use it as a normal input terminal. Therefore, this is inconvenient for a small-scale PC in which the number of input signal terminals is limited.

The present invention has been made in order to solve such a problem, and provides a PC capable of taking in an input signal from the terminal when the reset terminal of the counter is not used. The purpose is to do.

[0004]

A PC according to the present invention uses a counter circuit which can select whether to input a reset input signal and a reset input terminal to which the reset input signal of the counter circuit is supplied as a normal input terminal. When the storage means to be used is set and the counter circuit is selected not to input the reset input signal, and the storage means is set to use the reset input terminal as a normal input terminal, the input transfer is performed. At the same time, it has an arithmetic means for taking in the signal of the reset input terminal as an input signal.

[0005]

In the present invention, when the counter circuit is selected not to input the reset input signal and the storage means is set to use the reset input terminal as a normal input terminal, the signal of the reset input terminal is changed. It can be captured as an input signal. Therefore, the number of terminals of the input signal can be substantially increased without mechanically increasing it.

[0006]

1 is a block diagram showing the configuration of a PC according to an embodiment of the present invention. This PC is C
PU1, ROM2, RAM3, I / O port ^{4, E} 2 P
It is composed of a ROM 5 and a counter circuit 6. R
The OM 2 stores a system program that controls the arithmetic processing of the CPU 1, and the RAM 3 stores input / output data and the like. The I / O port 4 is an interface for inputting a signal from the outside or outputting an execution result of a calculation. In this embodiment, for example, 16 output terminals and 6 input terminals (X0 to X5) are provided. There is.
Since the data stored in the E ² PROM 5 is not erased even when the power is turned off, continuously used data, programs and the like are stored. The counter circuit 6 inputs a reset signal from the reset input terminal (X6) and a count signal from the count input terminal (X7).
The signal line from the reset input terminal (X6) is also connected to the input terminal side of the I / O port 4. The counter circuit 6 has a function of selecting whether or not to input the reset force signal as described later.

FIG. 2 is a diagram showing the data stored in the register 5a of the E ² PROM 5. This register 5
In a, data for selecting whether to use the reset input terminal as a reset input or a normal input terminal is stored. For example, when using the reset input terminal as a normal input terminal, set code "3",
Set code "4" when used as the original reset input terminal. Although a numerical value is set for this data in order to avoid setting mistakes, a flag may be set.

FIG. 3 is a block diagram showing the configuration of the input portion of the counter circuit 6. A flag that determines whether to input a reset signal is set in the register 61. For example, "0" is set when the reset input signal is not input, and "1" is set when the reset input signal is input. It This setting is written in the register 61 from the CPU 1. The AND gate 62 inputs the setting signal and the reset input signal of the register 61, blocks the reset input signal when "0" is set in the register 61,
When “1” is set, the reset input signal is output to the reset terminal R of the counter 63.

FIG. 4 is a flow chart showing the overall processing steps of the PC, and FIG. 5 is a flow chart showing the details of the input transfer. Before starting the operation, it is determined in advance whether the reset input terminal is used as the reset input terminal of the main body or the normal input terminal, and when the reset input terminal is used as the normal input terminal, FIG.
The code "3" is stored in the data register 5a. Data register 5 when used as a reset input terminal
The code “4” is stored in a. Further, "0" is stored in the register 61 of the counter circuit 6 when the reset signal is not fetched and "1" is stored when the reset signal is fetched.

When the operation is started, as shown in FIG.
The PU1 takes in an input signal through the I / O port 4 by input transfer and stores it in the RAM 3 (S1). CPU
1 takes in all input signals, then ROM2 or E
² Based on the program stored in the PROM 5, the arithmetic processing is performed using the input data that has already been fetched, and the calculation result is temporarily stored in the RAM 3 (S2). Next, CPU1
Reads out the calculation result and outputs it through the I / O port 4 (S3). The above arithmetic processing is cyclically repeated until the power is turned off or there is a stop command.

In input transfer, as shown in FIG.
The CPU 1 fetches the input signals of the input terminals X0 to X5 via the I / O port 4 and stores it in the RAM 3 (S1
1). This process is the same as the conventional process. Then E ²
The code stored in the register 5a of the PROM 5 is read (S12). Then, it is determined whether or not the code is "4" (S13), and if it is determined to be "4", the reset input terminal X6 is processed as the original reset input terminal of the counter 6 (S14). , No processing is performed in this input transfer (S14). When it is determined that the code is not "4" (S13), that is, when it is "3", "0" is set in the register 61 at this time and the reset signal is processed so as not to be taken in. Therefore, the reset input terminal (X6) is processed as a normal input terminal, and the data of the reset input terminal X6 is fetched through the P / O port 4 and stored in the RAM 3 (S15).

[0012]

As described above, according to the present invention, the signal of the reset input terminal can be taken in as an input signal under a certain condition, so that the number of input terminals can be increased without mechanical increase. Can be increased substantially,
A PC having a limited number of input terminals can be used for many user applications.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PC according to an embodiment of the present invention.

FIG. 2 is a diagram showing data stored in an E ² PROM.

FIG. 3 is a block diagram showing a configuration of an input portion of a counter circuit 6.

FIG. 4 is a flowchart showing the overall processing steps of the PC.

5 is a flowchart showing details of the input transfer of FIG.

Claims (1)

[Claims] 1. A counter circuit capable of selecting whether or not to input a reset input signal, and storage means for setting whether or not to use a reset input terminal supplied with the reset input signal of the counter circuit as a normal input terminal. When the counter circuit is selected not to input the reset input signal and the storage means is set to use the reset input terminal as a normal input terminal, the signal of the reset input terminal is transferred at the time of input transfer. A programmable controller having an arithmetic means for receiving as an input signal.