JPS63305450A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To reduce overhead at the time of simultaneous transfer of the same message to plural processors by storing a message and the number of receiving processors at the tie of transmission, and at the time of reception, reading out the message and then updating a processor counter. CONSTITUTION:Communication buffers 410 are formed in a common memory 400 correspondingly to respective processors 200a-200c. At the time of transmission, a message and the number of receiving processors are recorded in the communication buffer 410 of a self processor, an interruption is simultaneously generated in plural processors and an instruction for informing processor numbers is executed. The receiving processor reads out a message from the communication buffer 410 of the transmitting processor, subtracts '1' from the number of processors stored in the buffer 410 and stores the processor No. of the self processor. Since the communication buffer 410 is formed in each processor, and at the time of communication to plural processors, a message is stored in the communication buffer of the self-processor, message storage overhead can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a communication method for a loosely coupled multiprocessor system, and in particular, an inter-processor communication method suitable for reducing CPU overhead in inter-processor communication [Prior art] Processor The communication method between computer systems each having an independent main memory was to communicate using a channel coupling device in the same way as input/output, as in Japanese Patent Laid-Open No. 60-84658. This method requires a large processor overhead for one communication.

Although different from main memory, there is a method in which a storage device that can be directly accessed by processor instructions is shared among multiple processors and used as a communication buffer. Japanese Patent Application Publication No. 1983-
56063 provides a common memory within the system monitor, and divides this memory for each processor to use as a communication buffer. Communication involves storing a message in a communication buffer corresponding to the other processor, causing an interrupt to the other processor, and transferring the message.

In addition, in the inter-processor communication method described in JP-A-60-237566, a memory is shared between processors, and a part of this memory is divided for each processor and used as a communication buffer with a predetermined address. The message was retrieved from the communication buffer of its own processor by storing the message in the communication buffer and notifying an interrupt.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration the case where the same message is simultaneously transferred to multiple processors.

Since message copying and communication interrupts are performed for each processor, there is a problem in that communication overhead becomes large. In particular, shared storage devices take longer to access than main storage, which causes overhead.

An object of the present invention is to reduce the overhead when transferring the same message to multiple processors.

[Means for Solving the Problems] The above object is achieved by the following communication buffer access method and interrupt method.

A communication buffer is provided for each processor on shared memory,
When sending, it records the message and the number of receiving processors in its own processor's communication buffer, and executes an instruction to simultaneously generate interrupts to multiple processors and notify them of their processor numbers.

The receiving processor reads the message from the communication buffer of the transmitting processor, subtracts 1 from the number of processors in the communication buffer, and stores the number of its own processor.

[Effect]

A communication buffer is provided for each processor, and when communicating with multiple processors, the message is stored in the communication buffer of the processor itself, so the message storage overhead is reduced.

The reason why the above-mentioned interrupt instructions are used is that the overhead is smaller than when interrupts are generated for each processor.

The receiving processor can know the address of the communication buffer from the number of the transmitting processor and can read the message.

The reason why the number of processors in the communication buffer is subtracted by 1 is to determine that the message has been read by all receiving processors when this value becomes 0. Also, a processor that cannot read messages due to a failure!
! To identify the message, record the number of the processor that read the message. Whether a failure has occurred or not is determined by the fact that the number of processors in the communication buffer does not reach O even after a certain period of time.
The faulty processor can be identified because the processor number is not registered.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 1 shows the system configuration in this embodiment. In FIG. 1, processors a 200a to c 200c share a shared memory 400 via a shared memory control device 300. Further, these processors are connected to one interrupt control device 100 so that they can mutually generate interrupts. The shared memory has
The communication buffer 410 provided corresponding to the processor consists of a message storage area 411 and a processor counter 412.

Inter-processor communication is achieved by the sending processor storing a message in its own communication buffer, causing the other processor to generate an interrupt from an interrupt control device, and the other processor reading the message.

2 to 4 show the functions and operations of the interrupt control device.

In Figure 2, 6511 indicates an instruction to be executed by the processor, the instruction code, R1 (512) indicates that the first operand specifies a general-purpose register, and R2 (513) indicates that the second operand specifies a general-purpose register. It means to do something.

FIG. 3 shows an instruction for generating an interrupt.

5IGNAL instruction code 521 operand is Al (
52? , ), A,2 (523), the function code is set in At and the processor number is set in A2. A function code is a number used by software, and allows basic communication even without a communication buffer.

The processor number turns on the bit position corresponding to the processor number so that multiple processors can be communicated to simultaneously. This method makes it easy to specify simultaneous interrupts from one processor to all processors.

FIG. 4 shows an overview of the interrupt control device 100. When a processor executes the 5IGNAL instruction,
Function code and processor number are 112 and 1 respectively
20. Further, the number of the processor that executed the 5IGNAL instruction is stored in 111. Each bit of the processor number becomes an input to AND circuits 130a to 130c, and for processors whose bits are on, the source processor address and function code 112 are notified to the processor along with an interrupt.

In this way, simultaneous interrupts to multiple processors are performed.

FIG. 5 shows a flowchart of the communication method.

The transmission 610 first checks whether the processor counter 412 is 0 or not 611. If it is not 0, the previous message cannot be deleted because it has not been read by all receiving processors yet, so a WAIT is performed at 612.

If the processor counter is O, the message is stored 613, and the number of partner processors is stored in the processor counter 4.
12 614° Then, specify the target processor number and execute the 5IGNAL command.

Next, the case of reception 620 will be explained. 5IGNAI, when an interrupt occurs due to an instruction, the number of the processor executing the instruction is communicated, so the communication buffer address of the other processor is determined from this 621° Next, the message is read 622 and the processor counter is decremented by 1 62
3. Determine whether this value has become 0 (623). If it is 0, the transmitting processor may be WAIT at 612, so execute the 5IGNAL command to the transmitting processor (625). When the function code is 61
Specify a code indicating that it is PO8T for WAIT 2.

The reason for using function codes is that using communication buffers can lead to deadlock.

According to this embodiment, simultaneous interrupts to any number of processors can be easily realized. Furthermore, when one communication buffer cannot be used, WAIT allows other processing to be executed without lowering the efficiency of the processor.Furthermore, by using function codes, deadlock can be prevented.

〔Effect of the invention〕

According to the present invention, since a message is simultaneously interrupted to multiple processors and stored in the communication buffer only once, it is possible to reduce the overhead when transferring the same message to multiple processors at the same time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system that is an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing interrupt instructions to the processor, FIG. 4 is a detailed diagram of one interrupt control device, and FIG. , is a diagram showing a flowchart of inter-processor communication. 100... Interrupt control device, 200... Processor. 400... shared memory, 410... communication buffer,
411...Message storage area, 412...Processor counter.

Claims (1)

[Claims] 1. In a computer system in which multiple processors share a storage device that can be directly accessed by instructions from the processors, the present invention has an instruction that simultaneously generates interrupts to multiple processors and notifies them of the processor number of the sender. , a communication buffer is provided for each processor in the storage device, a message storage area and a processor counter area are provided in the communication buffer, and at the time of transmission, the message and the number of receiving processors are stored in the communication buffer, and at the time of reception, after reading the message, the processor An inter-processor communication method characterized by updating a counter. 2. After the receiving processor reads the above message,
2. The inter-processor communication system according to claim 1, wherein an identifier of the receiving processor is stored in the communication buffer.