JPH034348A - Control adapter for input/output device - Google Patents

Abstract

PURPOSE:To execute a final data transfer ion a short data length by generating a final data instructing signal based on an output to distinguish the word data number of the first-in-first-out buffer of a control adapter, etc., and supplying it to a bus control part. CONSTITUTION:The word data from an input/output device are transferred through a first-in-first-out buffer 410 to distinguish that the effective word data number of an input/output device control adapter in plural, 1 or 0, a register 400 for one word and a bus control part 100 to a high order device. The final data instructing signal is generated by an AND gate 04 by means of a signal to invert an output ready signal ORDY 1 inverted to an L from the buffer 410 with the lack of the word by means of an inverter 03, an output ready signal ORDY 0 at an H in which the word exists in the register 400 and a transfer completion signal 502 at an H from the input/output device and it is supplied to the bus control part 100. Thus, the final word shorter than a set length can be smoothly transferred, a compulsory interruption by a microprocessor is made unnecessary, and a hardware increase portion is made small.

Description

[Detailed description of the invention] [Industrial application field] The present invention is utilized for hardware data transfer.

The present invention relates to an input/output device control adapter that transfers data.

〔overview〕

The present invention provides an input/output device control adapter that transfers data using a hardware data transfer method, and when the input/output device ends the data transfer with a data length shorter than a preset data length, the bus controller By giving an instruction that is the final data in synchronization with the data, it is possible to eliminate the need for the microprocessor to forcibly terminate the bus control unit and hardware transfer control circuit, and to reduce the increase in hardware. This is what I did.

[Conventional technology]

The output adapter that controls the input/output device is controlled by the 71-ware data transfer (not a method in which data is transferred by firmware, but once the data transfer is started until it is finished), and the firmware control is required during that time. When performing a data transfer method (without data transfer), it is common to set the data length to be transferred to the adapter's /XI bus control unit or input/output device in advance, and then start the data transfer.

In this case, the bus control unit and the human output control device subtract the given data length while executing the data transfer, and when the remaining data length becomes 0, recognize the end of the data transfer and enter the end process.

For example, if there is a microprocessor inside the adapter,
In the case of a system that controls an input/output device, when the microprocessor recognizes a data transfer end signal from the input/output device, it executes post-processing and notifies the host device of the end of data transfer. Normally, when the microprocessor recognizes the end of data transfer, it immediately clears a register indicating the start of data transfer and inhibits the operation of the hardware that controls data transfer.

[Problem that the invention seeks to solve]

As mentioned above, hardware transfer usually ends when the data length set before data transfer is completed, but in some cases, data transfer from an input/output device to a host device is completed. When the transfer direction is manual direction), depending on the situation on the input/output device side, the input/output device side may terminate the data transfer at a count shorter than the preset data length.

In this case, since the remaining data length is not 0, the adapter side hardware, bus control unit, etc. prepare to receive the next data and go into a waiting state. When a data transfer end signal is sent from the input/output device in this state, the microprocessor recognizes the end signal and starts the end process, but the hardware that executes data transfer control, such as the bus control unit, is in a data waiting state. Therefore, the microprocessor must instruct the termination of data transfer by some means.

Also, depending on the status of the host device, data may remain in the first-in, first-out buffer or bus control unit in the adapter when the transfer end signal is sent from the input/output device, and the timing of the abort instruction by the microprocessor may also be a problem. becomes.

To avoid such complexity, prepare a memory in the adapter that can store data for the length of one transfer, and store all the data sent in a series of data transfers once in the adapter. In this case, even if the data length is smaller than the initially set value, data transfer between the adapter and the host device can be started using the actually sent data length, but this method requires a large amount of memory. This has the disadvantage that the amount of hardware increases.

The present invention eliminates such drawbacks, and even if the data transfer is completed with a data length shorter than the preset data length from the input/output device side, the final data is synchronized with the bus control unit and the final data is transferred. It is an object of the present invention to provide an adapter that does not require a microprocessor to execute forced termination processing by giving an instruction, and can reduce the amount of additional hardware required.

[Means for solving problems]

The present invention includes a first-in, first-out buffer that receives a data bus between it and an input/output device, a bus control unit that controls data transfer with a host device, and a control means that controls data transfer with the input/output device. In the input/output device control adapter connected to the internal bus, the above first-in first-out buffer is
It is configured to be able to distinguish between cases in which there is no valid data at all, cases in which only one word of valid data exists, and cases in which two or more words of valid data exist, and in response to data requests from the bus control unit. On the other hand, when two or more words of data exist in the first-in, first-out buffer, an instruction is given to output the data to the bus control unit, and a data transfer end signal from the input/output device is valid, and only one word is valid in the first-in, first-out buffer. means for instructing the bus control unit that the data is the final data when such data exists, and for instructing the data to be output from the first-in, first-out buffer to the bus control unit; It is characterized by

[Effect]

It distinguishes between cases where there is no valid data, cases where there is one word, and cases where two or more words exist, and when there are two or more words of data in the first-in, first-out buffer in response to a data request from the bus control unit. Instructs data output, and when the data transfer end signal from the input/output device is valid and 1 word of data exists in the first-in, first-out buffer, it instructs the bus control unit that it is the final data and outputs the final data. instruct what to do.

As a result, even if data transfer is completed with a data length shorter than the preset data length from the input/output device side, the final data instruction can be given to the bus control unit in synchronization with the final data, and then the microprocessor As a result, there is no need to forcibly terminate the bus control unit and the hardware transfer control circuit, and the amount of additional hardware can be reduced.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

The figure is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention includes a first-in, first-out buffer 410 that receives a data bus 500 connected to an input/output device (not shown), a bus control unit 100 that controls data transfer with a host device (not shown), and an input/output device. A microprocessor 200 that controls data transfer is connected to the internal bus 110, and the first-in, first-out buffer 410 is connected to the internal bus 110 when there is no valid data, only one word of valid data exists, and It is configured to be able to distinguish when two or more words exist, and instructs to output data to the bus control unit 100 when two or more words of data exist in the first-in, first-out buffer 410 in response to a data request from the bus control unit 100. , the data transfer end signal from the input/output device is valid and the first-in first-out buffer 410
a gateway 03 constituting means for instructing the bus control unit 100 that the data is the final data when only one word of valid data exists in the data, and instructing the first-in, first-out buffer 410 to output the data to the bus control unit 100;
．． 04.05.06.

A bus control unit 100 controls data transfer with a higher-level device (not shown). The microprocessor 200 has a register port 310
Enable hardware transfer related circuits by setting . Thereafter, the microprocessor 200 sends a command to an input/output device (not shown) to the register CM port 30.
It is set to 0 and sent to the input/output device via data bus 500, and then data transfer is performed.

In the case of data transfer in the manual direction, the manual data valid signal 50
1, data enters the register 0R400 from the first-in, first-out buffer 410 via the data bus 500, and is sent to the bus control unit 100 via the internal bus 110.

Gate 0~06 manages the presence or absence of data in register 0R400 and first-in first-out buffer 410, receives data request signal RQ from bus control unit 100, transfer end signal 5'02 from human output device, and receives data reception instruction signal. AC and final data instruction signal LT are output to the bus control section 100.

Next, the operation of each part configured in this way will be explained. First, microprocessor 200 sets register D310 via internal bus 110 when data transfer is required. When register 0310 becomes 1, the output IRDY from first-in first-out buffer 410.

Signals such as 0RDY become valid, and each gate 01 to 06
The operation is also effective (not particularly shown).

Below, first-in first-out buffer 410, register 0R40
The operation will be explained assuming that modes such as 0 and gate old to 06 are valid modes.

The microprocessor 200 writes a command (which may be accompanied by a data length) to an input/output device (not shown) to the register CMD 300 via the internal bus 110.

This sends a command to the input/output device and initiates data transfer.

If the data transfer is in the manual direction (from the input/output device to the host device), when data transfer from the input/output device is started, data is sent from the data bus 500 in synchronization with the manual data valid signal 501. It will be done.

Output signal IRDYI of first-in first-out buffer 410
When (input Ready) is 1, it indicates that there is an empty area in the first-in, first-out buffer 410, and in this case, a clock enters the input [N1 of the first-in, first-out buffer 410, data from the input/output device is taken into the first-in, first-out buffer 410, and the gate 01 creates the input clock for the first-in, first-out buffer 410.

Similarly, data from the input/output device is taken into the first-in, first-out buffer 410 when the output signal IRDY 1 =1.

When there is one word or more of data in the first-in, first-out buffer 410, the output of the first-in, first-out buffer 410 is 0RD.
When Y 1 (output Ready) becomes 1 and the output signal IRDY O of the register 0R400 is 1, that is, there is no valid data in the register 0R400, the clock is input to the first-in, first-out buffer 410 and the data is transferred from the first-in, first-out buffer 410. At the same time as the output, the input 180 of the register 0R400 becomes valid, so that the data is taken into the register 0R400, and the data is transferred to the first-in, first-out buffer 410 by the gate 02.
The input of 0IJT 1 and the manual IS of register 0R400
O is created.

When data enters register 0R400, register 0R4
00 output 0RDY O becomes 1 and register 0R40
0 indicates that valid data exists. First-in, first-out buffer 410 can store a plurality of data, but register 0R 400 can store only one word.

When the register D310 becomes 1, the bus control unit 100 prepares to receive data, and when the data can be received, it makes the data request signal RQ valid. When there is data in the first-in, first-out buffer 410, there is also data in the register QR400, and in this state, when the data request signal RQ becomes 1, the output of the first-in, first-out buffer 410 is 0RDY. Then, the signal OMIT O of the register 0R400 becomes valid, and at the same time, the data reception instruction signal AC to the bus control unit 100 also becomes valid, so that the contents of the register 0R400 are sent to the bus control unit 1000 through the internal bus 110.

This causes the output of register 0R400 to be [1ROY
(Since l becomes 0 and IROY O = 1, there is data in the first-in first-out buffer 410 and 0RDY l =
When it is 1, data is similarly sent from the first-in first-out buffer 410 to the register 0R400 by the output of gate 02.

Similarly, the data from the input/output device is in register 0R40.
0, when the data is in the first-in, first-out buffer 410, the data reception instruction signal AC is returned in response to the data request signal RQ from the bus control unit 100, and the data is stored in the register 0R.
400 to the bus control unit 100.

Assuming that the input/output device ends the data transfer at a certain point thereafter and activates the sender transfer end signal 502 to transmit the final data, the output of the first-in first-out buffer 410 is 0.
While RDY 1 = 1, data is sent in response to a data request from the bus control unit 100, but when the data in the first-in, first-out buffer 410 runs out, 0RDY 1 = 0.
This results in a state where 0RDY O=1, that is, there is no data in the first-in, first-out buffer 410 and one word of data is in the register 0R400.

In this state, when the transfer end signal 502 from the input/output device becomes 1 and the data request signal RQ becomes 1, the final data instruction signal LT is inputted to the bus control unit 100 by the gate 03.04, and further by the gate 05.06. The data reception instruction signal AC and the input OUTO of register 0R400 become valid. As a result, the final data is sent to the bus control unit 100, and the output of the register 0R400 becomes 0RDY O=0, and the data transfer ends.

[Effects of the Invention] As explained above, according to the present invention, even if data transfer is terminated with a data length shorter than the preset data length from the input/output device side, the bus control unit can synchronize with the final data. The final data instruction can be given by the microprocessor, and there is no need for the microprocessor to forcibly terminate the bus control unit and hardware transfer control circuit, and furthermore, the amount of additional hardware can be reduced. be.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of an embodiment of the present invention. 01.02.03.04.05.06...Gate, 1
00...Bus control unit, 110...Internal bus, 200
...Microprocessor, 300...Register CM
D, 310...Register D1400...Register OR, 410...First-in first-out buffer, 500...
...Data bus.

Claims (1)

[Claims] 1. A first-in, first-out buffer that receives a data bus between it and an input/output device, a bus control unit that controls data transfer with a host device, and a bus control unit that controls data transfer with the input/output device. In an input/output device control adapter in which a control means is connected to an internal bus, the first-in, first-out buffer is configured to store only one word of valid data when there is no valid data.
It is configured to be able to distinguish between a case where only one word exists and a case where two or more words of valid data exist, and when two or more words of data exist in the first-in, first-out buffer in response to a data request from the bus control unit, the bus Instructs the control unit to output data, and when a data transfer end signal from the input/output device is valid and only one word of valid data exists in the first-in, first-out buffer, the data is the final data to be sent to the bus control unit. An input/output device control adapter characterized in that the input/output device control adapter further comprises means for instructing to output data from the first-in, first-out buffer to the bus control unit as hardware.