JPS61250762A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To start immediately the necessary data transmission without in terrupting a microprogram and to prevent the occurrence of over-run by interpreting the type of interruption in terms of hard ware when other data transmission equipment interrupts. CONSTITUTION:When the other data transmission equipment 2 interrupts in order to start a command chain, a parameter outputted by an interruption accepting circuit 5 equals the one set to an expectation register 7. When the coincidence of both parameters are is detected by a comparator 6, a coincidence signal occurs. Said signal is inputted to a gate circuit 8 through a signal line 18 to cause the gate circuit 8 inoperable. When the gate circuit 8 is inoperable, a CCW address set to a control information buffer 9 is outputted to a data transmission circuit 4. As a result, the CCW address is given to the data transmission circuit 4, and the CCW is transferred to other data transmission equipment 2 from a main memory device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device, and particularly to a data transfer device controlled by a microprogram.

[Conventional technology]

Conventionally, in this type of data transfer device, when an interrupt from another device is detected, an interrupt is generated to the microprogram, and processing is performed after the interrupt type is interpreted by the microprogram. For example, even when data transfer is started by an interrupt from another device, the microprogram is once interrupted, the interrupt type is interpreted by the microprogram, and then the start of data transfer is instructed.

[Problem that the invention seeks to solve]

Therefore, even if the control information such as the data address necessary for data transfer is already prepared, if the microprogram is performing other processing, the acceptance of the interrupt will have to wait, delaying the data transfer and causing an overrun. The disadvantage was that it was easy for this to occur.

[Means for solving problems]

An object of the present invention is to provide a data transfer device that solves the above drawbacks.

The present invention provides, in a data transfer device controlled by a microprogram, a means for transferring data between a main storage device and another data transfer device, and a means for accepting an interrupt from the other data transfer device and interrupting the data transfer device. means for outputting a parameter indicating the type of interrupt, a first storage means capable of setting a parameter indicating the type of predetermined interrupt by a microprogram, and a second memory means capable of setting control information necessary for data transfer by a microprogram. storage means, means for comparing the parameters output by the interrupt accepting means and the parameters set in the first storage means, and a means for comparing the parameters output by the interrupt reception means with the parameters set in the first storage means, and when the parameters match, the method The apparatus is characterized in that it includes means for providing control information set in the second storage means to the data transfer means, and performs data transfer between the main storage device and the other data transfer device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This data transfer device 1 includes a data transfer circuit 4 that transfers data between another data transfer device 2 and a main memory device 3, and the main memory device 3 is connected to the data transfer circuit through signal lines 10 and 11. 4, and the other data transfer devices 2 are connected to the data transfer circuit 4 via signal lines 12.13.

The data transfer device 1 further includes an interrupt reception circuit 5 that accepts interrupts from other data transfers 2 and outputs information (parameters) indicating the type of interrupt. It is connected to another data transfer device 2 via a line 14. The interrupt acceptance circuit 5 is connected to one input terminal of a comparator 6 via a signal line 15, and the other input terminal of the comparator 6 is connected to an expected value register 7 via a signal line 16.

An arbitrary value (parameter) is set in this expected value register 12 through a signal line 17 by a microprogram.

The comparator 6 is connected to a gate circuit 8 via a signal line 18, which is connected to the data transfer circuit 4 via a signal line 19, and to the control information buffer 9 via a signal line 20. Control information necessary for data transfer, such as a data address, is set in this control information buffer via a signal line 21 by a microprogram. Comparator 6
compares the parameters output from the interrupt reception circuit 5 with the parameters set in the expected value register 7, transmits the comparison result to the gate circuit 8, and the gate circuit 8 converts the contents of the control information buffer 9 into data. output to the transfer circuit 4,
or control to deter.

Next, the operation of the data transfer device configured as above will be explained. Now, a parameter indicating an interrupt necessary to start a command chain is set in the expected value register 7 by the microprogram, and the address of the CCW to be executed by the command chain is set in the control information buffer 9. shall be. When the interrupt receiving circuit 5 receives an interrupt from another data transfer device 2 as described above, it outputs a parameter indicating the type of the interrupt to the signal line 15. The comparator 6 compares the parameters output from the interrupt reception circuit 5 with the parameters set in the expected value register 7.

When an interrupt to start a command chain occurs from another data transfer device 2, the parameters output by the interrupt reception circuit 5 become equal to the parameters set in the expected value register 7, and the comparator 6 When a match of parameters is detected, a match signal is generated. This match signal is input to the gate circuit 8 via the signal line 18 and enables the gate circuit. When the gate circuit 8 is enabled, the CCW address set in the control information buffer 9 is output to the data transfer circuit 4. As a result, the CCW address is given to the data transfer circuit 4, and the CCW is transferred from the main storage device 3 to another data transfer device 2. On the other hand, if the accepted interrupt is not an interrupt for starting a command chain, the output of the interrupt acceptance circuit 5 does not match the contents of the expected value register 7, and therefore the comparator 6 does not generate a match signal. , therefore, the contents of the control information buffer 9 are not output from the gate circuit 8.

As is clear from the above embodiments, when data transfer is performed by an interrupt from another data transfer device, the microprogram is not interrupted and the microprogram does not interpret the interrupt type. Data transfer can be started even when the computer is performing other processing.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and it goes without saying that various modifications and changes can be made within the scope of the present invention.

〔Effect of the invention〕

As explained above, the data transfer device of the present invention interprets the interrupt type in hardware when there is an interrupt from another data transfer device. Even if the microprogram is executing other processing, necessary data transfer can be started immediately without interrupting the microprogram, and there is an advantage that overruns can be prevented from occurring.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer device of the present invention. 1...Data transfer device of the present invention 2...Other data transfer device 3...Main storage device 4...Data transfer circuit 5...Interrupt reception Circuit 6...Comparator 7...Expected value register 8...Gate circuit 9...Control information buffer 7Furthers 10-21/Signal line

Claims (1)

[Claims] (1) In a data transfer device controlled by a microprogram, a means for transferring data between the main storage device and another data transfer device, and a means for accepting interrupts from the other data transfer device and processing the interrupts. means for outputting a parameter indicating the type of interrupt; a first storage means capable of setting a parameter indicating the type of predetermined interrupt by a microprogram;
a second storage means in which control information necessary for data transfer can be set by a microprogram; means for comparing parameters output by the interrupt reception means with parameters set in the first storage means; means for supplying the control information set in the second storage means to the data transfer means according to the output from the comparison means when the parameters match, the main storage device and the other data A data transfer device characterized by transferring data to and from a transfer device.