JPH01233544A - Data transfer system - Google Patents

Abstract

PURPOSE:To execute a transfer processing at a high speed by constituting the title system so that at the time of transferring the same data to the respective shared memories of two systems, a shared memory adaptor precedes before a transfer of one data is ended and obtains the next data from a CPU. CONSTITUTION:In case when data is transferred to shared memories C, C' from a CPU A, first of all, the CPU A sends the data to a share memory adaptor B, and the adaptor B sends its data to a shared memory adaptor B'. In this case, a Q output of an FF 2 becomes ON, and an inversion Q output of an FF 5 is reset. Subsequently, the adaptor B sends the data to a shared memory C. Next, after an operation (c) has been ended, if the next transfer use data exists in the CPU A, the adaptor B inputs the next data from the CPU A without waiting for an end informing signal E from the adaptor B'. In the adaptor B, therefore, a signal for showing a start of an operation b' of the next sequence is turned ON, but since the inversion Q output of the FF 5 is OFF, the Q output of the FF 2 is not turned ON, and the operation b' is inhibited. In this state, when the signal E from the adaptor B' is inputted, the Q output of the FF 2 becomes ON and the operation b' is started.

Description

[Detailed Description of the Invention] [Summary] Two devices each having a shared memory that holds the same data.
This is a system that transfers data to shared memory with the aim of eliminating wasted waiting time in data transfer and increasing the transfer speed. The completion of one data transfer sequence is defined as the point in time when the transfer process to the shared memory of that system is completed, and the shared memory adapter is instructed to transfer the next data to the other system at the same time as the previous data in the other system. The configuration is provided with a sequence inhibiting means that pushes up until the end of processing.

[Industrial application field]

TECHNICAL FIELD The present invention relates to data transfer in two independent information processing systems having shared memories holding identical data to each other.

In two independent information processing systems, necessary data is stored with the same contents in mutually held shared memories, thereby facilitating maintenance when a failure occurs in one of the memories or the like. However, this means that data transfer for data security is frequently performed between two systems, and speeding up the data transfer will lead to improving the actual processing capacity of the system.

[Conventional technology]

Conventional data transfer in the above system will be explained with reference to conventional operation time charts shown in FIGS. 3 and 4. Figure 3 is a basic configuration diagram of the system. In two independent systems α and β, A and A' are CPUs each including a main storage device, B and B' are each system α,
Shared memory adapters c and c' for transferring and controlling shared memory between systems β are shared memories that hold the same data between systems.

In this system, when data is transferred from CPUA of system α to two shared memories c and c', the data is first sent from CPUA to shared memory adapter B. Assuming that this action is a, the action a takes a predetermined amount of time to be performed, as shown in FIG. 4, where time is plotted on the horizontal axis. Shared memory adapter B sends the sent data to shared memory adapter B'. If this action is b, then the action is also the fourth
Spend a certain amount of time as shown in the diagram. Next, shared memory adapter B sends the sent data to shared memory C.

Assuming that this operation is C, operation C requires a predetermined time as shown in FIG. Shared memory adapter B' sends the sent data to shared memory C'. Assuming that this operation is d, operation d is also performed at a predetermined time as shown in FIG. In this way, after the operation d, the data transfer to the shared memories c and c' is completed, and as shown in FIG. 4, the transfer is completed at the transfer cycle time P, and the next transfer becomes possible. Such data transfer is performed by system β
The same holds true when data is transferred from the CPU UA' to the two shared memories C2C'.

[Problem to be solved by the invention]

However, in the conventional technology described above, the shared memory adapter B of system α is connected to the shared memory adapter B of system β.
If shared memory adapter B' is in a busy state performing other processing when data is sent to shared memory adapter B', the data is not transferred from shared memory adapter B' to shared memory C' immediately.

The data transfer is executed when other processing is completed and a request for execution of action d is selected from among a plurality of processing requests. In this way, the operation d is started after the waiting time m in the shared memory adapter B' has elapsed after the end of the operation as shown in FIG. After the shared memory adapter B sends the data to the shared memory C, the shared memory adapter B receives the transfer end notification signal (
The process is stopped for a time n until the operation d (end notification signal) is detected. Therefore, the transfer cycle time P becomes longer, and the start of the next data transfer, a data transfer operation a' from the CPUA to the shared memory adapter B, is delayed.

That is, in an independent type system consisting of systems α and β, if data in the shared memories c and c' of both systems are to be guaranteed at the same time, the next process cannot be started until the processes of both operations c and d are completed.

Therefore, a problem arises in that the waiting time until the start of the next process becomes long and the data transfer speed of the system becomes slow.

The present invention was devised in view of the above problems, and aims to provide a data transfer method that eliminates wasted waiting time in data transfer and increases the transfer speed.

[Means to solve the problem]

In order to achieve the above object, the data transfer method of the present invention includes a shared memory that holds the same data as other systems, and a shared memory adapter that controls data transfer to the shared memory of the own system and other systems. In the data transfer method of the information processing system provided with the system, the completion of one data transfer sequence in the system that transfers data to the shared memory is defined as the point in time when the transfer process to the shared memory of that system is completed, and the shared memory adapter , a sequence inhibiting means is provided for inhibiting the transfer of the next data to the other system until the processing of the previous data in the other system is completed.

[Effect]

When the CPU of one system attempts to transfer data to the shared memory of its own system and other systems, the shared memory adapter of the own system receives and receives the data from the CPU, transfers the data to the other system, and then Transfer data to the shared memory of the host system.

At this point, in the present invention, one data transfer sequence in the own system is completed. Therefore, the next transfer sequence immediately starts, and the shared memory adapter receives the next data from the CPU. If the process of transferring the previous data to the shared memory has not been completed in the other system, the sequence inhibiting means inhibits the transfer of the next data to the other system.

As a result, the next transfer sequence is started in the local system without waiting for the completion of transfer to the shared memory in the other system, so the waiting time in the local system sequence is reduced and speed is increased.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing essential parts of shared memory adapters B and B' that transfer data between the systems shown in FIG. 3. In the first death, 1 is a data bus control circuit between shared memory adapters, 2 is a flip-flop, and its Q
When the output is input to the data bus control circuit 1 and the J input is turned ON, the Q output is turned ON and data is output on the data bus, and when the K input is turned ON, the Q output is turned OFF. Therefore, data output is suppressed. Conventionally, operation b shown in FIG. 3, that is, a signal (SETb) indicating the start of data transfer between adapters was
A signal (R3Tb) indicating the end is input to K to control data output. In this embodiment, the input is the same as the conventional one (signal indicating termination (R5Tb)).
is connected. 3.4 is a flip-flop that synchronizes the completion notification signal E from the partner system, which is issued upon completion of operation d shown in FIG.

The above configuration is conventionally provided, but in this embodiment, a flip-flop 5 and an AND gate 6 are added as sequence inhibiting means. The J input of the flip-flop 5 is connected to the Q output of the flip-flop 2, the K input is connected to the Q output of the flip-flop 4, and the input of the AND gate 6 receives a signal indicating the start of the aforementioned operation. (SETb) is connected to the output of the flip-flop 5 on the other side, and the output is connected to the J input of the flip-flop 2.

Furthermore, with this shared memory adapter, in the case of transfer from the CPU of the own system, one data transfer sequence is completed when writing to the shared memory of the own system (operation C) is completed, and the CPU If there is data that requires transfer, the shared memory adapter immediately starts executing the next transfer sequence (operation a').

The operation of the above configuration will be explained with reference to the time chart shown in FIG. 2 and FIG. 3. When trying to transfer data from CPUA to two shared memories c and c', first
PUA sends data to shared memory adapter B (operation a
), shared memory adapter B sends the data to shared memory adapter B' (action b). At this time, the Q output of the flip-flop 2 is turned ON, and the output of the flip-flop 5 is reset.The zero-order shared memory adapter B sends data to the shared memory C (operation C). The steps up to this point constitute one transfer sequence in the own system α.

After this, shared memory adapter B uses CPU after operation C is completed.
If there is data for the next transfer, shared memory adapter B'
The next data is sent to the CPU while waiting for the completion notification signal E from
(operation a/).

On the other hand, the shared memory adapter B' is in a busy state when data is fetched during operation, and after h hours, the priority is taken and the data is sent to the shared memory C' (operation d). Further, the shared memory adapter B' sends a completion notification signal E to the shared memory adapter B after the operation d is completed. In the shared memory adapter B, after the next data is fetched from the CPUA (operation a'), the signal (SETb) indicating the start of the next sequence, operation b', is turned ON, which is the sequence inhibiting means. Since the 100 output of the flip-flop 5 is OFF, the AND circuit 6 is gated and the Q output of the flip-flop 2 is not turned ON, and data is not sent from the data bus control circuit 1, that is, operation b. ' execution is inhibited. In this state, when the end notification signal E from the shared memory adapter B' is input, the 100 output of the flip-flop 5 is turned ON and the gate of the AND circuit 6 is released, so that the Q of the flip-flop 2 is turned on. Output is ON
Then, data is sent from the data bus control circuit 1,
Operation b' is started. Thereafter, operations c' and d' are executed and repeated in the same manner as the sequence of operations a to d described above.

In the above operation, the data transfer time is affected by the waiting time h', . . . because the shared memory adapter B' is in the busy state, as shown in FIG. When the waiting time, h', . . . becomes large to a certain extent, the waiting time tt, p,', .
will occur. However, in this case, in this embodiment, operations a', a'', . . . , which are the next data transfer cycle, are completed before operations d, d', . The second and subsequent data transfers are performed earlier than the first data transfer of d by the time that shared memory adapter B obtains the data from the CPUA.In other words, in one data transfer after the second, the shared memory Since the cycle in which adapter B obtains data from CPUA is performed in parallel with the previous data transfer, the data transfer time is shortened and the speed is increased.

Also, the time required is relatively small, and the operations a', a''.

If operations d, d', . . . are completed by the time . becomes zero.

In other words, there is no waiting time for the shared memory adapter B, and data transfer is performed at the highest speed.

In this way, in this embodiment, when the same data is transferred to the shared memory of each of the two systems, the shared memory adapter first transfers the C
Since the next data is obtained from the PU, the wasted waiting time of the shared memory adapter is reduced and the speed is increased.

In the above embodiment, a flip-flop 5 and an AND circuit 6 are added as cycle inhibiting means, but the present invention is not limited to this. The own system's operation b' continues until

Any configuration is sufficient as long as it suppresses b'', . It is something.

〔Effect of the invention〕

As explained above, according to the present invention, the next transfer sequence is started without waiting for the completion of other systems, and data processing is performed in advance, thereby eliminating the waste of waiting time and transferring A data transfer method with increased speed can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a main part of a shared memory adapter in an actual cross-sectional example of the present invention, Fig. 2 is a time chart of the operation of the embodiment, Fig. 3 is a basic configuration diagram of the system, and Fig. 4 is a diagram of a conventional shared memory adapter. It is a time chart of the operation. 1; Data bus control circuit; 2-4; Flip-flop 5; Flip-flop (sequence inhibiting means); 6; AND circuit (sequence inhibiting means); α, β; Information processing system; A, A'; CPU. B, B' i shared memory adapter, c, c'; shared memory. Diagram 1 of the 1st chapter of the 1st edition of this essay

Claims (1)

[Claims] Shared memory (C
, C') and the shared memory of the own and other systems (C
, C')).
, B'), the completion of one data transfer sequence in the system that transfers data to the shared memory (C, C') is defined as A sequence in which the shared memory adapter (B, B') suppresses the transfer of the next data to the other system until the completion of the processing of the previous data in the other system. A data transfer method characterized in that a deterrent means (5, 6) is provided.