JPS5958518A - Input and output control system - Google Patents

Input and output control system

Info

Publication number
JPS5958518A
JPS5958518A JP16998482A JP16998482A JPS5958518A JP S5958518 A JPS5958518 A JP S5958518A JP 16998482 A JP16998482 A JP 16998482A JP 16998482 A JP16998482 A JP 16998482A JP S5958518 A JPS5958518 A JP S5958518A
Authority
JP
Japan
Prior art keywords
input
output
priority
level
levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16998482A
Other languages
Japanese (ja)
Inventor
Tetsuya Hagiwara
哲也 萩原
Kiyouko Harada
原田 協子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16998482A priority Critical patent/JPS5958518A/en
Publication of JPS5958518A publication Critical patent/JPS5958518A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To perform operations, unit by unit, according to priority and to change the priority easily by providing an input/output control system with priority levels classified into two, i.e. one for interruption acceptance from an input/output device group and the other for control over the input/output device group. CONSTITUTION:An input/output controller 3 is connected to a main storage device 1, processor 2, and input/output devices 10, and a microprocessor operates at plural priority levels. A level #0 is a top priority level for machine checking processing, a level #1 is for handling external interruption acceptance, and levels #2-#4 are for input/output control. Respective processes of the input/output devices 10 are stored in a control storage 8 by the levels and a processor performs operations of input/output devices with high levels in the storage 8. For example, the input/output devices 10-1 and 10-2 perform the same operation and their priority levels of the operation processing can be made different.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明はマイクロプロセッサが複数の優先順位レベルに
て入出力装置群の制御を行う入出力制御シヌテムにおけ
る入出力制御方式に関し、特に入出力装置の動作単位に
優先順位をf\Jして処理を行う入出力制御方式に関す
るものである。
Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an input/output control system in an input/output control system in which a microprocessor controls a group of input/output devices at a plurality of priority levels, and in particular, This relates to an input/output control method that performs processing by assigning priority f\J to each operation unit.

(ハ)従来技術と問題点 複数の入出力装置を制御するのに、これら入出力装置の
処理をイテうのに優先順位を定めてそれぞれの処理を行
うことが一般に行われている。ところが入出力装置の優
先順位は装置各々に応じた順位に固定されておシ順位を
変更することが容易でないという問題があり、−万人出
力装置単位に優先順位を決定しても当該入出力装置にて
取扱う制御の中でも時間的に速く処理したいデータ例え
ばチェンデータとか或は多少遅れてもよい制御例えばチ
ェンコマンドの処理があり、他の入出力装置の速く処理
するチェンテ゛−夕は実行中の入出力装置の処理が終了
するまで待たされ、又同一装置を読み書き動作を行う場
合には上位装置でさえ下位装置の動作が終了するまで待
たされ処理時間がかかるとともに所要の処理が有効適切
な画先順位になされないといった欠点があった。
(C) Prior Art and Problems When controlling a plurality of input/output devices, it is common practice to prioritize the processing of these input/output devices and perform each process. However, there is a problem in that the priority order of input/output devices is fixed according to each device, and it is not easy to change the priority order. Among the controls handled by the device, there is data that needs to be processed quickly in terms of time, such as chain data, or control that can be delayed to some extent, such as chain command processing. It is necessary to wait until the processing of the input/output device is completed, and when reading and writing from and to the same device, even the higher-order device has to wait until the operation of the lower-order device is completed, which takes processing time and makes it difficult for the necessary processing to be performed effectively and properly. There was a drawback that he was not given priority.

(C)発明の目的 本発明は上記従来の欠点に鑑み、入出力装置は勿論入出
力装置の動作単位に優先順位に従った処理が行えるとと
もに優先順位変更が容易に行え能率のよい入出力側御方
式を提供することを目的とするものである。
(C) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides an efficient input/output side that can perform processing according to priority order for each operation unit of the input/output device as well as the input/output device, and can easily change the priority order. The purpose of this is to provide a method of control.

((1)  発明の構成 簡単に述べると本発明は、複数の優先順位レベ/しを入
出力装置群よりの割込み受付用の第1の優先順位レベル
と入出力装置群の制御を行う第2の優先順位レベlし群
とに分割し、入出力装置の動作単位に1身先順位を付し
て記憶域に備え、マイクロプロセッサが第1の優先順位
レベpで入出力装置の?i;II込みを受付は記憶域の
内容に基づいて第2の優先順位レベル群にて動作単位の
制御を行うよってしたことを特徴とするものであり、効
率のよい入出力制御を行うことが可能となる。
((1) Structure of the Invention Briefly stated, the present invention has a plurality of priority levels: a first priority level for accepting interrupts from a group of input/output devices, and a second priority level for controlling the group of input/output devices. i; of the input/output device at the first priority level p; The feature of the II-inclusive reception is that the unit of operation is controlled at the second priority level group based on the contents of the storage area, and it is possible to perform efficient input/output control. Become.

(e)発明の実施例 以下本発明の実施例を図によって詳細に説明する。(e) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は本発明の入出力制御装置を示す一実施例のブロ
ック図、第2図は本発明による入出力装置の動作を説明
するためのタイムチャート図、第3図は本発明による上
記1.ホ装置の動作を説明するためのタイムチャー1−
図である。
FIG. 1 is a block diagram of an embodiment of the input/output control device according to the present invention, FIG. 2 is a time chart diagram for explaining the operation of the input/output device according to the present invention, and FIG. 3 is a block diagram of an embodiment of the input/output control device according to the present invention. .. Time chart 1 to explain the operation of the device
It is a diagram.

図において、1は主記憶装置、2は処理装置。In the figure, 1 is a main storage device, and 2 is a processing device.

3は転送バッファ4とアクセス制御部5とcpuインタ
フェース部6とマイクロプロセッサ7とコントロールス
トレジ8 、!: I/リインターフエーヌ部9とから
構成される入出力制御装置、1o−iないし10−nは
入出力装置をそれぞれ示す。
3 is a transfer buffer 4, an access control unit 5, a CPU interface unit 6, a microprocessor 7, a control storage 8, ! : An input/output control device consisting of an I/reinterface unit 9; 1o-i to 10-n indicate input/output devices, respectively.

マイクロプロセッサ7はコントロールストレジの内容に
よりその処理を突付しCPUインタフェース部6を介し
て処理装置2と接続され、又アクセス制御部5を介して
主記憶装置1と接続される。
The microprocessor 7 determines its processing based on the contents of the control storage, and is connected to the processing device 2 via the CPU interface section 6 and to the main storage device 1 via the access control section 5.

更にマイクロプロセッサ7は工10インターフェース部
9を介し入出力装置10−1ないし10−nと接続され
ている。転送バッファ4は主記憶装置1と入出力装置1
0−1ないし10 nと間の転送デ°−夕を一時保持す
る。マイクロプロセッサ7は複数の陽光11頁位しベ〜
に動作を行う例えばパ#0 レベル、#1  レベル 
 # 2 レベル、 # 3 レベル。
Further, the microprocessor 7 is connected to input/output devices 10-1 to 10-n via an interface section 9 of the processor 10. Transfer buffer 4 has main storage device 1 and input/output device 1
Temporarily holds transfer data between 0-1 to 10n. The microprocessor 7 has about 11 pages of sunlight.
For example, PA #0 level, #1 level
#2 level, #3 level.

#4レペlしの陽光順位レベルで動作する。#0レヘ/
L’ カ最iμ先しベ)Vであり、#Oレベルはマシン
チェック処理用のものであり一般に用いられている。#
ルベル ツノ装置1 0−1ないし10−nの割込みは必ず#■
レペ/しにて取扱う、#2ないし#4レベルは入出力制
御用に分割しである。入出力装置10−1ないし10−
nの処理即ち動作及び次に処理する処理即ち動作もコン
トロールストレジ8にレベ/し別で格納されている。こ
の格納する手段はマイクロプロセッサ7用のマイクロプ
ログラムによって行う。従ってコントロールストレジ8
を処理するマークロプロセッサ7の処理依頼により例え
ば入牙 出力装置10−1が処理即ち動作本終了すると入出力装
置10−1は:l′#:ルぺμに割込む、結果としてコ
ントロールストレジ8に格納しである高順位の入出力裂
1Mの動作がマイクロプロセッサ7によって処理される
こととなる。従って入出力装置の動作別に順位レベルを
設定しておけば高能率の入出力装置が可能となる、 以上を第2図を用いて説明する。縦軸のLo 。
#4 Operates at the sunshine ranking level of rep. #0 lehe/
The #O level is for machine check processing and is generally used. #
Rubertsuno device 1 Interrupts from 0-1 to 10-n must be #■
Levels #2 to #4, which are handled by Rep/Shi, are divided for input/output control. Input/output device 10-1 to 10-
The process or action of n and the next process or action are also stored separately in the control storage 8. This storing means is performed by a microprogram for the microprocessor 7. Therefore, control storage 8
For example, when the input/output device 10-1 completes the processing, that is, the main operation, in response to a processing request from the mark processor 7, which processes The operations of the high-order input/output split 1M stored in the microprocessor 8 will be processed by the microprocessor 7. Therefore, if a ranking level is set for each operation of the input/output device, a highly efficient input/output device will be possible.The above will be explained using FIG. 2. Lo on the vertical axis.

LlないしL4はそれぞれ#0ないし#4レベ/しの優
先順位を示す。横軸は入出力装置の動作を示す。
Ll to L4 indicate priority levels #0 to #4, respectively. The horizontal axis shows the operation of the input/output device.

入出力装置10−1と10−2との動作単位の順位レベ
lしを下表に示すように定める。
The ranking level of the operation unit of the input/output devices 10-1 and 10-2 is determined as shown in the table below.

入出力装置10−1と10−2の動作は同一動作であっ
ても表に示すように異なっている。即ち表中に付した苦
とり印は入出力装置によって動作処理の優先順位が異な
っている。以上の状態における入出力装置10−1と1
0−2の単独動作は第2図(a)と(b)に示しておる
。従来の方式であれば装置ごとに入出力装fa 10−
1はレベル#2.入出力装置10−2はレベ/し#8と
処理レベルが固定されており、2装置が同時稼動されれ
ば入出力装置10−2のチェーンデ−タ動作よりも入出
力装置10−1のチェインコマンド処理が優先されてし
まう。本発明の場合には第3図(Qに示すように動作す
る。例えば入出力装置10−1が既に起動状態にありチ
ェーンデータ動作、チェンコマンド動作、チェーンデー
タ動作を行わしめる場合に、入出力装置10−2は入出
力装置10−1がチェーンテ゛−タ動作終了後に起動動
作を開始させるとすると入出力装置10−1のチェンデ
−タ動作時先ず#ルべ/しの割込み受付A−0続いて同
一レベ/しのチェーンデータ処理A−2.終了後アイド
lし状態の#4レベル、勿論このアイドル状態の時には
デ°−夕が転送されている。この時に入出力装[10−
2を起動する場合#ルべlしでB−0割込み受付人に#
3レベルの起動処理B−1.起動処理中に入出力装置1
0−1の割込み受1−jA−0起動処理B−4終了後入
出力装置10−1のチェーンコマンドA−3の処理の如
く動作が制御される。この結果、各装置の各処理単位に
優先順位を変化させることができる。
The operations of the input/output devices 10-1 and 10-2 are different as shown in the table even though they are the same. That is, the priority marks of the operation processing shown in the table are different depending on the input/output device. Input/output devices 10-1 and 1 in the above state
The independent operation of 0-2 is shown in FIGS. 2(a) and (b). In the conventional system, each device has input/output devices fa 10-
1 is level #2. The processing level of the input/output device 10-2 is fixed at level #8, and if the two devices are operated simultaneously, the chain data operation of the input/output device 10-1 will be faster than the chain data operation of the input/output device 10-2. Command processing takes priority. In the case of the present invention, the operation is as shown in FIG. Assuming that the device 10-2 starts the startup operation after the input/output device 10-1 finishes the chain data operation, when the input/output device 10-1 operates the chain data, the device 10-2 first receives the interrupt reception A-0 of #rube/2. Chain data processing at the same level A-2. After completion, the #4 level is in the idle state. Of course, data is being transferred during this idle state. At this time, the input/output device [10-
When starting 2, use the # rubel to the B-0 interrupt acceptor #
3-level startup processing B-1. Input/output device 1 during startup processing
0-1 interrupt reception 1-jA-0 After completion of the start processing B-4, the operation is controlled as in the processing of the chain command A-3 of the input/output device 10-1. As a result, the priority order can be changed for each processing unit of each device.

主記憶装置1のデータを読書き動作する場合も同様に行
われ、マイクロプロセッサは割込み受イ」を#ルベルテ
行い、コン1〜ロー7レヌトレジ8によってこの処理を
行い次の処理をコントロールレストレン8より指定され
た順位レベ/しで処理を行うとともに直ちに#ルべ/し
を開放する。従って常時#ルベル みが可能となり、運用効率が向上する。第3図は左記・
世装置の動作を示しくa)は従来(b)は本発明を示す
、動作は前記した入出力装置の場合と同様であるので省
略する。
When reading and writing data from the main memory device 1, the same process is carried out. Processing is performed at the specified ranking level and the # rube is immediately released. Therefore, it is possible to always perform #rubel checking, which improves operational efficiency. Figure 3 is shown on the left.
(a) is the conventional device; (b) is the present invention; the operation is the same as that of the input/output device described above, and will therefore be omitted.

(f)発明の効果 以上詳細に説明したように、本発明の人出力制御方式は
マイクロプロセッサのプロクラムを父型するのみにて人
出ツノ装置の動作単位の1功先順位を容易に行えるとと
も1・て能率のよい入出力制御が行え、入出力装置を運
用する上で利点の多いものとなる。
(f) Effects of the Invention As explained in detail above, the human output control method of the present invention can easily prioritize the operation units of the human output horn device simply by programming the microprocessor program. In both cases, efficient input/output control can be performed, which has many advantages when operating input/output devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の入出力制御方式を示す一実施例のブロ
ック図.第2図は本発明による入出力装置の動作を説明
するためのタイムチャート図,第8図は本発明による主
記憶装置の動作を説明するためのタイムチャート図であ
る。 図において、3は入出力制御装置,7はマイクロプロセ
ッサ、10−1ないし10−nは入出力装置をそれぞれ
示す。
FIG. 1 is a block diagram of an embodiment showing the input/output control method of the present invention. FIG. 2 is a time chart diagram for explaining the operation of the input/output device according to the present invention, and FIG. 8 is a time chart diagram for explaining the operation of the main memory device according to the present invention. In the figure, 3 indicates an input/output control device, 7 indicates a microprocessor, and 10-1 to 10-n indicate input/output devices, respectively.

Claims (1)

【特許請求の範囲】[Claims] マイクロプロセッサが複数の優先順位レベルにて入出力
装置群の制御を行う入出力制御システムにおける入出力
制御方式であって、前記複数の優先順位レベルを前記入
出力装置群よりの割込み受付用の第1の優先順位レベル
と該入出力装置群の制御を行う第2の優先順位レベル群
とに分割し、該各々の入出力装置の動作単位に優先順位
を付して記憶域に備え、前記マイクロプロセッサが前記
第1の優先順位レベルで前記入出力装置群の割込みを受
C寸は前記記憶域の内容に基づいて的記第2の優先順位
レベlし群にて前記動作単位の制御を行うようにしたこ
とを特徴とする入出力制御方式。
An input/output control method in an input/output control system in which a microprocessor controls a group of input/output devices at a plurality of priority levels, wherein the plurality of priority levels are used as a priority level for accepting interrupts from the input/output device group. The microprocessor is divided into a first priority level group and a second priority level group for controlling the input/output device group. The processor receives an interrupt from the input/output device group at the first priority level and controls the operation unit at a second priority level based on the contents of the storage area. An input/output control method characterized by:
JP16998482A 1982-09-28 1982-09-28 Input and output control system Pending JPS5958518A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16998482A JPS5958518A (en) 1982-09-28 1982-09-28 Input and output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16998482A JPS5958518A (en) 1982-09-28 1982-09-28 Input and output control system

Publications (1)

Publication Number Publication Date
JPS5958518A true JPS5958518A (en) 1984-04-04

Family

ID=15896439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16998482A Pending JPS5958518A (en) 1982-09-28 1982-09-28 Input and output control system

Country Status (1)

Country Link
JP (1) JPS5958518A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008053639A1 (en) * 2006-10-31 2010-02-25 デンゲン株式会社 Sheet metal repair jig, sheet metal repair apparatus using the same, and sheet metal repair method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008053639A1 (en) * 2006-10-31 2010-02-25 デンゲン株式会社 Sheet metal repair jig, sheet metal repair apparatus using the same, and sheet metal repair method

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