JP2000148524A - Fail-safe collating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simple fail-safe data collating device capa-ble of driving high speed microprocessor units(MPUs) independently of the operation speed of a data collation part. SOLUTION: High speed MPUs 1, 2 respectively include data cache memories 1a, 2a for storing data and instruction cache memories 1b, 2b for storing the instructions of the MPUs 1, 2. A data collation part is provided with a tinning generation part 10 for generating a control signal for processing data by instructions accessed from respective memories 1b, 2b at the time of processing data transferred from respective memories 1a, 2a to respective data buses 5, 8, IFO buffers 11, 12 for writing data in the trans-fer order of data to the data buses 5, 8 based on the control signal generated by the timing generation means 10 and reading out data in the written order of data and a comparator 13 for compar-ing and judging whether data read out from the buffers 11, 12 coincide with each other or not by the control signal generated by the timing generation part 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fail-safe verification apparatus for monitoring the operation of a high-speed microprocessor in a railway signal information processing system.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a block configuration of a conventional fail-safe collating apparatus. In FIG. 5, the fail-safe verification device includes two microprocessors (hereinafter, referred to as “MPU”) 50 and 51, memories 53 and 56 such as a main storage device and an auxiliary storage device, and an input / output device 5.
Peripherals such as 4, 57 and two data buses 55, 5
Data collating circuit 5 for monitoring the data supplied via 8
9 is comprised.

[0003] The data collating circuit 59 includes a timing generator 5.
2. It is composed of data holding units 60 and 61 and a comparison circuit 62, and performs data collation for each data transfer cycle of the MPUs 50 and 51. This data matching circuit 59
The PUs 50 and 51, the memories 53 and 56 or the input / output devices 54 and 57 predict the timing of acquiring data, store the two data at the same timing, and determine the coincidence of the two data. The timing generation unit 52 uses M
The desired timing signal 201 is generated by the bus cycle timing signal 200 output from the PUs 50 and 51, and the data holding units 60 and 61 and the comparison circuit 62 are operated.

[0004] The timing generator 52 comprises, for example, a clock generator and a clock controller (not shown) for generating a clock signal. When the bus cycle timing signal 200 output from the MPUs 50 and 51 is input to the clock controller, the clock generator 52 generates a clock. In response to a clock control signal from the control unit, the timing signal 201 is stored in the data holding unit 6.
0, 61 and the comparison circuit 62.

The data holding units 60 and 61 are constituted by, for example, a register comprising a flip-flop circuit and a gate circuit, and take in data on a data bus at a certain moment by a timing signal 201 which is a latch signal from a timing generation unit 52. Remember. Comparison circuit 62
The data holding unit 6 uses the timing signal 201 output from the timing generation unit 52 as a comparison start trigger signal.
Compare the data lengths of the data stored in 0 and 61,
If they match, a pulse signal indicating a match signal is output,
If they do not match, a high level (H level) or low level (L level) signal is output.

FIG. 6 shows the operation of each block in the block configuration of FIG. 6 will be described with reference to the configuration of FIG. Data A to C shown in FIG. 6A correspond to MPUs 50 and 51 and memories 53 and 56 shown in FIG.
Alternatively, the data buses 55, 5
The data is transferred to the data collating circuit 59 through the step 8. At this time, the timing generation unit 52 of the data matching circuit 59 creates a latch signal as a data holding trigger signal in response to the bus cycle timing signal 200 output from the MPU 50, 51, and the data holding unit 60, 61 converts the data. Hold temporarily.

Next, the data holding units 60 and 61 are shown in FIG.
Data is read out by the timing signal 201 from the timing generation unit 52 shown in FIG. When the comparison circuit 62 receives the comparison start trigger signal as the timing signal 201 from the timing generation section 52, the comparison circuit 62 determines whether data taken in from the two data buses 55 and 58 match or not, and when they match, outputs a pulse signal. And outputs a high-level signal or a low-level signal when they do not match, and fixes the output. Once the data matching circuit 59 has made a mismatch check, the data matching device 59 stores the state so that it cannot return to the alternate output signal again. As a result, the conventional fail-safe data collating device, once determining that there is a mismatch between the two systems of data in the data collating circuit 59, stores the mismatch status to indicate that there is a failure in the fail-safe collating device. A fail-safe is realized by notifying a display device or the like that does not operate so as not to operate it with a failure.

On the other hand, in this type of fail-safe collating apparatus, when the MPUs 50 and 51 are compatible with high speed,
Since the operating speed of the MPU 51 may limit the operating speed of the MPUs 50 and 51 due to the influence of a delay circuit (not shown) inside the data matching circuit 59, it is demanded that the MPUs 50 and 51 be operated at high speed.

As a measure for responding to such a demand, a conventional fail-safe collation device includes a data collation circuit corresponding to a microprocessor MPU having a high-speed performance, for example, a “Kyosan Circular VOL.
No. 1 (1993)) using a bus comparison circuit. In this bus comparison circuit, when data is transferred to a data compression circuit (not shown) from an A / B 32-bit data bus, the data is compressed by a data compression circuit and then compared by a comparison circuit CMP (not shown). The data is judged to be normal or abnormal. By processing data with the data compression circuit, the MPU can operate at high speed.

[0010]

However, the conventional fail-safe verification device requires a complicated circuit configuration such as a data compression circuit, which complicates data processing. There is a problem that processing becomes complicated, a problem that operation speed becomes slow, and a problem that it becomes difficult to provide a highly versatile device applied to various railway signal information systems.

The present invention has been made in view of the above demands and problems, and a first object is to store data read from a first internal memory in a buffer based on an instruction read from a second internal memory. It is an object of the present invention to provide a fail-safe collating apparatus that can operate a microprocessor with high priority without being affected by the operation speed of a data collating unit when writing or reading from a buffer.

A second object of the present invention is to simplify data processing in a fail-safe collating device,
A general-purpose fail-safe that simplifies arithmetic processing for data collation and can be easily applied to devices such as electronic interlocking devices, electronic terminal devices, electronic level crossing control devices, ATCs, and transponders as various railway signal information systems. A collation device is provided.

[0013]

According to a first aspect of the present invention, there is provided a fail-safe collating apparatus, comprising: a high-speed processor connected to each of at least two buses; and a control signal generated by an instruction from the high-speed processor. And a data collating unit for performing a write / read command of data transferred via the buses and collating whether or not the read data match each other. A first or second internal memory for storing instructions, wherein the data collating unit comprises:
When processing data transferred from the first internal memory to each bus, a signal generation unit for generating a control signal for processing data in accordance with an instruction called from the second internal memory, and a control generated by the signal generation unit A data comparison in which data is written in the order in which the data is transferred to each bus according to a signal, and each buffer memory for reading in the order of the written data is compared with each data read from the buffer memory. And a determining unit.

According to the first aspect of the present invention, the first internal memory and the second internal memory are respectively disposed in the high-speed processors connected to the respective buses.
The data is stored in the internal memory, and the instruction is stored in the second internal memory.

The data collating unit comprises a signal generating unit, first and second buffer memories, and a data comparing and judging unit. When the signal generating unit processes data transferred from the first internal memory to the first bus, 2 Generate a control signal for processing data according to an instruction called from the internal memory. The data collating unit creates a control signal in accordance with an instruction from each high-speed processor, issues a write instruction for data transferred from each high-speed processor via each bus, and issues a read instruction for the written data. The collation is performed to determine whether each set of data matches.

The first buffer writes data in the order in which the data is transferred to the first bus according to the control signal generated by the signal generation unit, and reads out the data in the order of the written data. Second
The buffer is controlled by the control signal generated by the signal generation unit.
The data is written in the order in which the data is transferred to the bus, and the data is read in the order of the written data. Further, the data comparison determination unit performs a comparison determination as to whether the data read from the first and second buffer memories match.

According to the first aspect of the present invention, the operation speed of the data collating unit is controlled by using the first and second buffers while the second internal memory for storing instructions of the high-speed processor is operating. By making the speed lower than the speed, the microprocessor can be independently operated at a high speed regardless of the operation speed of the data collating unit.

More specifically, the control is performed such that frequently used data and instructions are left in the first or second internal memory of the microprocessor, and the number of accesses to the external main storage device is reduced, so that the effective number of accesses is reduced. Access time is reduced. As a result, the microprocessor can be operated at high speed, and the ability of each high-speed processor can be maximized even when performing two-system data collation. In addition, the present invention assigns priorities to frequently used data and instructions stored in the first or second internal memory data of the microprocessor and writes or reads them to the first and second buffers to store two systems of data. Since the configuration of the data comparison / determination unit configured to perform the comparison can be simplified, the processing load on the data comparison unit can be further reduced by simplifying the processing.

[0019] The fail-safe collating apparatus according to claim 2 more specifically includes first and second high-speed processors connected to the first and second data buses, respectively, and the first and second high-speed processors.
A control signal is generated by a command from the high-speed processor, and a write command for data transferred from the first or second high-speed processor via the first or second bus, and a read command for the written data, and a read command. A first or second high-speed processor comprising: a data cache memory for storing data; a first or second high-speed processor, wherein the first or second high-speed processor includes a data cache memory for storing data. An instruction cache memory for storing instructions of the high-speed processor; and a data collating unit, when processing the data transferred from the data cache memory to the first data bus, processes the data by the instruction called from the instruction cache memory. A signal generation unit for generating a control signal to be generated, and a first or second signal generated by the control signal generated by the signal generation unit. Writes the data in the order in which they are transferred to the data bus, the first or second 2FIFO buffer read in the order of written data, the first and second 2F
A data comparison / determination unit that performs a comparison determination as to whether data read from the IFO buffer matches, and outputs a signal indicating the match or mismatch.

According to the second aspect of the present invention, the operation speed of the data collating unit is controlled using the first and second FIFO buffers while the data cache memory for storing the instruction of the first or second high-speed processor is operating. Accordingly, by making the operation speed slower than the operation speed of the microprocessor, the operation control and the like of the microprocessor can be operated at high speed regardless of the operation speed of the data collating unit. The entire configuration can be simplified by making the most of it, and simplifying the processing in the data collating unit.

According to a third aspect of the present invention, there is provided a fail-safe matching apparatus according to the second aspect,
The first and second high-speed processors are high-speed microprocessors used for communication equipment for driving security and communication equipment for passenger business.

According to the third aspect of the present invention, the information system for various railway signals can be used for general purposes by being applied to devices such as an electronic interlocking device, an electronic terminal device, an electronic level crossing control device, an ATC, and a transponder.

According to a fourth aspect of the present invention, there is provided the fail-safe collating apparatus according to the second or third aspect, wherein the first and second high-speed processors normally connect the first or second data bus. Via the first or second F
Data is written to the I / O buffer, and the first or second FIFO buffer is reused by an instruction called from the instruction cache memory of the first or second high-speed processor at the time of restart.

According to the fourth aspect of the present invention, the first and second high-speed processors are provided with the first or second FI through the first or second data bus during normal times.
Data is written to the FO buffer, and the first or second FIFO buffer is reused by an instruction called from the instruction cache memory of the first or second high-speed processor at restart. This simplifies the data processing in the data collating unit, so that the data processing of the entire apparatus can be made simple and efficient.

According to a fifth aspect of the present invention, there is provided the fail-safe collation device according to any one of the second to fourth aspects, wherein the signal generation unit converts the data into the first or second FIFO. When the data is stored in the buffer, a trigger signal for holding data is output, and data transmitted from the first and second high-speed processors via the data bus is transmitted to the first and second FIFO buffers by the trigger signal for holding data. It is stored in the specified order.

According to a fifth aspect of the present invention, in the fail-safe collation device, the signal generation unit outputs a trigger signal for holding data when storing the data in the first or second FIFO buffer, and outputs the first and second trigger signals. The data transmitted from the high-speed processor via the data bus is stored in the order of transmission to the first and second FIFO buffers by the trigger signal for holding data. Thereby, the data processing can be made efficient by simplifying the data processing.

According to a sixth aspect of the present invention, there is provided the fail-safe collating apparatus according to any one of the second to fifth aspects, wherein the signal generation unit performs a comparison when judging data. A trigger signal for determination is output to the comparison / determination unit, and the comparison / determination unit compares and reads the data read from the first and second FIFO buffers, respectively, based on the trigger signal.

In the fail-safe collating device according to the sixth aspect, when comparing and judging data in the signal generating section, a trigger signal for coincidence judgment is output to the comparing and judging section, and the comparison judging section outputs the trigger signal in accordance with the trigger signal. 1st and 2nd FI
The data read from the FO buffer is compared and determined. This simplifies the data processing, thereby simplifying the data collation processing.

According to a seventh aspect of the present invention, there is provided the fail-safe collating apparatus according to any of the second to sixth aspects, wherein when the instruction cache memories of the first and second high-speed processors are hit, , Access to the first or second FIFO buffer via the first or second data bus is interrupted.

According to the seventh aspect of the present invention, when the instruction caches of the first and second high-speed processors are hit, the first or second FIFO buffer via the first or second data bus is provided. , The processing in the data matching circuit is simplified.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a fail-safe collating device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration of a fail-safe collation device according to an embodiment of the present invention.

The first and second high-speed processors MP
U1 and U2 are high-speed microprocessors used for operation security communication equipment and passenger business communication equipment. MPU1,
2 is connected to the data buses 5 and 8, respectively. MPU
Data cache memories 1 and 2 are internal data cache memories 1
a, 2a and instruction cache memories 1b, 2b. The data is temporarily stored in the data cache memories 1a, 2a before being transferred to the data buses 5, 8, and the timing of instructions to the MPUs 1, 2 is generated. Before being sent to the section 10, it is stored in the temporary instruction cache memories 1b and 2b.

The data collating circuit 9, which is a data collating unit,
It comprises a timing generation unit 10 as a signal generation unit, FIFO buffers 11 and 12 as buffer memories, and a comparison circuit 13 as a data comparison determination unit, and performs data collation for each data transfer cycle of the MPUs 1 and 2. The data collating circuit 9 predicts when the MPUs 1 and 2 and the memories 3 and 6 or the input / output devices 4 and 7 will acquire data, stores the two data at the same timing, and determines the coincidence of the two data. Perform

When processing the data transferred from the data cache memories 1a and 2a to the data buses 5 and 8, the timing generation unit 10 executes the instruction cache memories 1b and 2
A control signal for processing data is generated by the instruction called from b. The input terminal of the timing generation unit 10
Connected to the output terminals of MPU1 and MPU1, respectively.
2 when an operation waiting signal is input from a circuit (not shown) to M
Bus cycle timing signal 1 from PU 1 and PU 2
Enter 00.

One output of the timing generator 10 is F
The input side of the IFO buffer 11 is connected, and the other output side of the timing generation section 10 is connected to the input side of the comparison circuit 13. The timing generator 10 generates M based on a bus cycle timing 100 which is an output signal from the MPUs 1 and 2.
PU buffers 11 and 12 from PUs 1 and 2, memories 3 and 6 or input / output devices 4 and 7 via data buses 5 and 8.
Write data in sequence to the FIFO buffer 1
Read in the order in which they were written to 1,12.

The FIFO buffers 11 and 12 store the FIFOs in response to a write or read instruction from the timing generator 10.
Data is output to the comparison circuit 13 in order from the one written in the FO buffers 11 and 12 first. The comparison circuit 13
The outputs of the FIFO buffers 11 and 12 are compared based on the output of the timing generator 10 and the comparison result is output.

FIG. 2 is a block diagram showing a specific example of the data matching circuit according to the embodiment of the present invention. 2, a data collating circuit 9 includes a control signal generator 20, a general-purpose comparator 21, a control signal generator 22, FIFO buffers 11 and 12, a two-wire code checker 23, and a pendulum circuit 2.
4 and a narrowing-down circuit 25. Circuits other than the FIFO buffer of these circuits are packaged in an LSI element.

The control signal generator 22 responds to the output signal of the general-purpose comparator 21 by using the FIFO buffers 11, 12
And a control signal for operating the two-wire code checker 23.

The FIFO buffers 11 and 12 have an MPU
When the signals output from 1, 2 are input, data transmitted from MPUs 1, 2, memories 3, 6 or input / output devices 4, 7 via data buses 5, 8 shown in FIG. The data is read out in the order stored in the FIFO buffers 11 and 12 based on the control signals output from the control signal generator 20.

The two-wire code checker 23 checks the output data of the two systems A and B read from the FIFO buffers 11 and 12. The pendulum circuit 24 smoothes the output of the two-wire code checker 23. When the output of the pendulum circuit 24 is input to the narrowing-down circuit 25, the two signals are compared and examined, and the FS which is a coincidence or non-coincidence signal is output.
Output CP.

FIG. 3 shows a FIFO according to the embodiment of the present invention.
FIG. 3 is a conceptual diagram illustrating an example of a buffer. The data processing structure of the FIFO buffer shown in FIG. 3 consists of a queue (queue) represented in a row, a memory area for storing data for processing the queue, and two pointers indicating the beginning and end of the queue. , Using the last.
In the two-wire code checker 23, the pendulum circuit 24, and the narrowing-down circuit 25 constituting the comparison circuit in FIG. 2, each data read out by the FIFO buffers 11, 12 is compared, and a comparison result output FSCP is output.

Next, the operation of the embodiment of the present invention will be described with reference to the timing chart of FIG. In the description of FIG. 4, reference is made to FIGS.

FIG. 4A shows a data string transferred to the A-system data bus 5, and FIG. 4B shows a data string transferred to the B-system data bus 8. FIG.
FIG. 4C shows an example of data stored in the FIFO buffer 11, and FIG. 4D shows an example of a data string stored in the FIFO buffer 12. FIG. 4E shows an example of a data string input to the comparison circuit 13, and FIG. 4F shows an example of a match signal of the comparison circuit 13.

First, when the MPUs 1 and 2 operate, M
The data of the data string in FIG. 4A is transferred from the data cache memories 1a and 2a of the PUs 1 and 2 to an internal bus (not shown) by M.
In response to a PU bus transfer command, data transfer is performed between the peripheral devices mainly including the memories 3 and 6 via the data buses 5 and 8. In accordance with this data transfer, FIFO buffer 1
Transfer data is stored in 1 and 12.

Here, data A to E in FIG.
The upward arrow indicates the acquisition timing of the MPU data, and the data C to E indicate the timing indicating the reuse. FIG. 4B is a timing example showing an example of data transfer on the data buses 5 and 8, in which timing to data E to F indicates interruption of bus access due to a cache hit, and downward arrows of data A to F indicate timing generation units. Is a data holding trigger signal input to the FIFO buffers 11 and 12 from.

The FIFO buffers 11 and 12 use an area in which data can be stored and two pointers (top and last) indicating the beginning and end of the queue in order to implement queue processing. As a result, the data is stored in the buffer in order from the data that is put first, and the timing generation unit 10 in FIG. 1 (the control signal generation unit 2 in FIG. 2).
0) based on the timing signal (control signal).
The data is stored in the FO buffers 11 and 12 in order from the data put first. When data is read from the FIFO buffers 11 and 12, the data is read in the order in which the data is stored in the FIFO buffers 11 and 12 by a timing signal from the timing generation unit 10.

FIG. 4E shows the input timing of the comparison circuit 13 in which the data A to F are stored in the FIFO.
Input from buffers 11 and 12. The downward arrow in FIG. 4E is a comparison start trigger signal. The comparison is made by the comparison start trigger signal. FIG. 4 (F) shows data A
ＦF are represented by a pulse signal which is a coincidence signal when two data coincide. In the case of a mismatch, it is indicated by a high-level signal or a low-level signal.
The comparison circuit 13 synchronizes the data read from the FIFO buffers 11 and 12 with a comparison start trigger, which is a timing signal 101 output from the timing generation unit 10, and outputs a comparison result.

In this embodiment, as shown in FIG. 1, every time data is transferred on the data buses 5, 8, the data contents are compared by the data collating circuit 9, and if they match, 1 and 0 are compared. The output of the alternate output signal is fixed to 1 or 0 when they do not match. Once a mismatch occurs, the data matching circuit 9
Stores the state and prevents the output from returning to the alternate output signal again, thereby realizing fail-safe. The data matching circuit 9 predicts when the MPUs 1 and 2 or peripheral devices will acquire data, stores the data at the same time, and passes the stored data to the comparison circuit 13 to perform matching.

(Modified Embodiment 1) In the above embodiment, processing is performed by a queue which is a FIFO as a data processing structure. However, it is needless to say that the present invention is not limited to this. For example, a stack which is a LIFO can be used. It is. The stack is different from the queue in that the last entry comes out first, but the data processing structure is simple and easy to use.

[0050]

As described in detail above, the present invention stores frequently used data and instructions in an internal memory of a microprocessor, and reduces the number of accesses to a main storage device.
By shortening the effective access time, the microprocessor operates at high speed, and based on the data or instructions stored in the internal memory, the data is prioritized and stored in the buffer, and each data is read out and read. Since the collation unit can collate and determine whether or not they match, the configuration and control can be simplified.

Further, according to the present invention, by simplifying the data processing in the data collating unit, it is possible to simplify the processing at the time of data collation and to provide a device suitable as an information system for various railway signals.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a data matching circuit in FIG. 1;

FIG. 3 is a conceptual diagram of a FIFO buffer in FIGS. 1 and 2;

FIG. 4 is a timing chart illustrating an operation according to an embodiment of the present invention.

FIG. 5 is a block diagram showing the configuration of a conventional apparatus.

FIG. 6 is a timing chart showing the operation in FIG.

[Explanation of symbols]

1, 2, high-speed MPU, 1a, 2a, data cache memory, 1b, 2b, instruction cache memory, 3, 6, memory, 4, 7, input / output device, 5, 8, data bus, 9,
Data collating circuit, 10 ... Signal generation unit (timing generation unit), 11, 12 ... FIFO buffer, 13 ... Data comparison judgment unit (comparison circuit).

Claims (7)

[Claims] 1. A high-speed processor connected to each of at least two buses, and a control signal generated by a command from the high-speed processor, and a write / read command for data transferred from the high-speed processor via each bus. And a data collating unit for collating whether or not each of the read data coincides with each other. The processor includes a first or second internal memory for storing data or instructions. The data collating unit, when processing data transferred from the first internal memory to each of the buses, generates a control signal for processing the data according to an instruction called from the second internal memory. And writing the data in the order in which the data is transferred to each of the buses according to the control signal generated by the signal generating unit. Fail-safe collation, comprising: a buffer memory for reading data in the order of data stored therein; and a data comparison / determination unit for comparing / determining whether or not the data read from the buffer memory match. apparatus. 2. A high-speed processor connected to a first or second data bus and a control signal generated by an instruction from the high-speed processor, and a control signal generated by the high-speed processor via the data bus. A fail-safe collating device including a write command, a read command for the written data, and a data collating unit for collating whether or not each of the read data coincides with each other. A data cache memory that stores data, and an instruction cache memory that stores instructions of the high-speed processor. A control signal for processing the data by an instruction called from the instruction cache memory. A signal generator for generating a said by the generated control signal by the signal generating unit writes the data in the order in which they are transferred to the data bus, the first or second 2F read each in the order of the written data
An IFO buffer; and a comparison / determination unit that performs a comparison determination as to whether or not the respective data read from the first and second FIFO buffers match, and outputs a signal indicating match or mismatch. Fail-safe verification device. 3. The high-speed microprocessor according to claim 2, wherein the first and second high-speed processors are high-speed microprocessors used for operation security communication equipment and passenger business communication equipment.
The fail-safe verification device as described. 4. The first and second high-speed processors normally operate via a first or a second data bus.
Data is written into a FIFO buffer, and the first or second FIFO is executed by an instruction called from the instruction cache memory of the first or second high-speed processor upon restart.
4. The fail-safe collating device according to claim 2, wherein the O-buffer is reused. 5. The signal generator outputs a trigger signal for holding data when storing data in the first or second FIFO buffer, and transmits the signal via the data bus from the first and second high-speed processors. The first and second FIFOs are stored in the first and second FIFOs by the data holding trigger signal.
5. The fail-safe matching device according to claim 2, wherein the data is stored in a buffer in the order of transmission. 6. The signal generation unit outputs a trigger signal for match determination to the comparison determination unit when performing data comparison determination, and the first and second FIFO buffers are used in the comparison determination unit according to the trigger signal. 3. A comparison judgment is made on data read out from each of
The fail-safe verification device according to claim 5. 7. An access in said first or second FIFO buffer via said first or second data bus is interrupted when the instruction caches of said first and second high speed processors are hit. The fail-safe verification device according to any one of claims 2 to 6.