JPH0528093A - Circuit for generating burst transfer end interrupt signal - Google Patents

Abstract

PURPOSE:To prevent an interrupt signal of burst transfer end from being erroneously given to a processor from a burst transfer end interrupt signal generating circuit. CONSTITUTION:An interrupt signal S62 is outputted from an AND circuit 62 and is given to a processor 2 on conditions that a memory empty signal 85 of a FIFO memory 5 for temporary data storage is turned on and a data transfer end signal Sb4 indicating the burst transfer end from a DMA control circuit 4 is turned on and a write signal S4 a given from the DMA control circuit 4 to the FIFO memory 5 does not exist for a certain time by delay of a timer 61, that is, a timer output signal S61 is turned on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst transfer end interrupt signal generating circuit in a burst data transfer processing device or the like having a first-in first-out memory (hereinafter referred to as a FIFO memory) for temporary storage on a data transfer path. Is.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of the construction of a conventional burst data transfer processing device incorporating a burst transfer end interrupt signal generating circuit.

This burst data transfer processing device has a data transfer bus 1 in which a processor 2 for controlling the entire device, a memory 3 for storing data, a direct memory access control circuit (hereinafter, a DMA control circuit). , And the FIFO memory 5 are connected. DMA
The control circuit 4 performs burst transfer in which data is read from the memory 3, the write signal S4a is supplied to the FIFO memory 5 and the read data is written to the FIFO memory 5, without passing through the processor 2, and burst transfer is performed. It has a function of outputting the data transfer end signal S4b after the end.
The FIFO memory 5 has a function of outputting a memory empty signal S5 when its memory area becomes empty.

A burst transfer end interrupt signal generation circuit (hereinafter, this circuit may be simply referred to as an interrupt signal generation circuit) 6 is connected to the DMA control circuit 4 and the FIFO memory 5, and the FIFO memory is further provided. A data transfer circuit 7 is connected to 5. The interrupt signal generation circuit 6 has a memory empty signal S5 indicating that the memory area of the FIFO memory 5 for temporary storage of data is empty, and the DMA control circuit 4
Has a function of notifying the processor 2 of the end of burst transfer in the form of an interrupt signal S6 when the data transfer end signal S4b indicating the end of burst transfer is on. The data transfer circuit 7 has a function of spontaneously taking out the data written in the FIFO memory 5 and sending it to the outside (not shown).

Here, it is assumed that the DMA control circuit 4 realizes high-speed burst transfer by repeating reading and writing of a unit word every tens to hundreds of nanoseconds, for example.

Next, the operation will be described.

When the processor 2 commands the DMA control circuit 4 to perform burst transfer, the DMA control circuit 4
The data is read from the memory 3 and the read data is written to the FIFO memory 5 by the write signal S4a. The data written in the FIFO memory 5 is spontaneously taken out by the data transfer circuit 7 and sent to the outside.

The processor 2 does not participate in the burst transfer and performs a completely different process to improve the processing efficiency of the entire system. The interrupt signal generation circuit 6 is DM
The data transfer end signal S4b from the A control circuit 4 is turned on,
When the memory empty signal S5 of the FIFO memory 5 is on, the interrupt signal S6 is supplied to the processor 2. As a result, the processor 2 can recognize that the data transfer is completed.

As described above, the processor 2 can determine the timing of the end of burst transfer by monitoring the interrupt signal S6 from the interrupt signal generation circuit 6, and immediately notify the timing to the outside. it can. Since the external device receiving the notification from the processor 2 matches the timing of receiving the last data of the burst data with the timing of the notification, efficient processing can be realized.

[0010]

However, the conventional burst transfer end interrupt signal generation circuit 6 has the following problems.

(A) Generally, the number of words to be burst-transferred is variable each time, and it is necessary to guarantee the timing by an external device that receives a notification regardless of the length. However, in the conventional configuration, an erroneous interrupt signal S6 is generated under the condition that the number of burst words is extremely small, although the data to be transmitted to the outside remains in the FIFO memory 5.

That is, for example, when one piece of data is entered from an empty state, the FIFO memory 5 notifies the outside of the FIFO memory 5 with a certain time delay that one piece of data has been entered. Therefore, the memory empty signal S5 may be momentarily turned on even though the data to be transmitted remains in the FIFO memory 5, which causes the interrupt signal generation circuit 6 to generate an erroneous interrupt signal. There is a risk of generating S6. When such an erroneous interrupt signal S6 is generated,
On the device side receiving an external notification, it is difficult for the processor 2 to notify the external device so as to guarantee the timing.

(B) Even under the special condition that the number of burst words is extremely small, during burst data transfer, the flow of burst data is temporarily on the data transfer bus 1 due to congestion of the data transfer bus 1 or the like. Stop, FI
When an empty state occurs at the end of the burst data in the FO memory 5, the same phenomenon as (a) above occurs.

(C) As a general phenomenon, a burst
During the data transfer, when the speed at which the data transfer circuit 7 sends the data to the outside is slightly higher than the transfer speed of the DMA control circuit 4 and the transfer condition is such that the FIFO memory 5 is often empty, burst data transfer A phenomenon similar to the above occurs at the tail of the.

(D) In the conventional interrupt signal generation circuit 6,
When the empty signal S5 of the FIFO memory 5 is turned on and the data transfer end signal S4b of the DMA control circuit 4 is turned on, the interrupt signal S6 given to the processor 2 is generated. Therefore, the DMA control circuit 4 sends the last burst data to the FIFO.
When writing to the O memory 5, the DMA control circuit 4 turns on the data transfer end signal S4b, but since the operation of the FIFO memory 5 is delayed, the memory empty signal S5 does not turn off immediately. It remains on for a while. As a result, an erroneous interrupt signal S6 may be output even when there is data in the FIFO memory 5.

The present invention provides a burst transfer end interrupt signal generation circuit which solves the problem that the interrupt signal S6 is erroneously supplied to the processor 2 as a problem that the above-mentioned prior art has.

[0017]

In order to solve the above-mentioned problems, a first aspect of the present invention is a FIFO for temporarily storing data in a burst by a DMA control circuit without a processor for performing a burst transfer termination process. A burst transfer end interrupt signal generation circuit for notifying the processor of the end of the burst transfer in the form of an interrupt signal when the burst transfer is performed by writing in the memory is configured as follows.

That is, the memory empty signal indicating that the memory area of the FIFO memory is empty is ON, the data transfer end signal indicating that the DMA control circuit is terminating data transfer is ON, and the DMA control circuit indicates that the FIFO memory is ON. Condition that the write signal given to
The interrupt signal is supplied to the processor.

In the second invention, the burst transfer end interrupt signal generating circuit of the first invention delays a write signal supplied to the FIFO memory for a predetermined time, the memory empty signal and the data transfer end signal. , And an AND circuit that obtains the logical product of the outputs of the timer and outputs the interrupt signal.

[0020]

According to the first aspect of the present invention, an erroneous interrupt signal is prevented from being supplied to the processor by adding one simple input condition for defining the output condition of the conventional burst transfer end interrupt signal generating circuit. is doing. That is, in addition to the two signals of turning on the memory empty signal of the FIFO memory and turning on of the data transfer end signal of the DMA control circuit, there is a fixed time from when the DMA control circuit finishes giving the write signal to the FIFO memory. A condition is added that the output of the burst transfer end interrupt signal generation circuit is not turned on.

As a result, when the processor gives a burst transfer instruction to the DMA control circuit, thereafter, another processing which is not directly related to the burst transfer is executed. During the burst transfer, the data is FI by the DMA control circuit.
Written to FO memory. The data written in the FIFO memory is read by a data transfer circuit or the like and transferred to the outside.

The data end signal output from the DMA control circuit is turned on, the memory empty signal of the FIFO memory is turned on, and further, it is turned on after a fixed time from the time when the DMA control circuit has finished giving the write signal to the FIFO memory. The burst transfer end interrupt signal generation circuit outputs an interrupt signal to the processor in accordance with the three signals. As a result, the processor recognizes that the burst transfer has ended, and the accuracy of the burst transfer end determination is improved.

According to the second aspect of the invention, the write signal given to the FIFO memory is delayed by the timer for a certain period of time, the memory empty signal, the output signal of the timer, and the data transfer end signal are given to the AND circuit, and the AND circuit inputs three signals. An interrupt signal is generated by obtaining a logical product. This improves the accuracy of burst transfer end determination with a simple circuit. Therefore, the above problem can be solved.

[0024]

1 is a block diagram showing the construction of a burst data transfer processing device incorporating a burst transfer end interrupt signal generating circuit according to an embodiment of the present invention. Elements common to those shown in FIG. Are assigned common reference numerals.

This burst data transfer processing device is provided with a data transfer bus 1, a processor 2, a memory 3, a DMA control circuit 4, a FIFO memory 5 and a data transfer circuit 7, which are the same as those in the conventional case. 4 and F
Only the circuit configuration of the burst transfer end interrupt signal generation circuit 60 connected to the output side of the IFO memory 5 is different from the conventional one.

The interrupt signal generating circuit 60 is provided with a write signal S4 supplied from the DMA control circuit 4 to the FIFO memory 5.
It is composed of a timer 61 for delaying a for a certain time and a 3-input AND circuit 62 connected to the output side thereof. The AND circuit 62 receives the data transfer end signal S4b from the DMA control circuit 4 and the output signal S61 of the timer 61.
And a memory empty signal S5 from the FIFO memory 5 are input, the logical product of them is calculated to generate an interrupt signal S62,
This is a circuit for giving the interrupt signal S62 to the processor 2.

Next, the overall operation of the apparatus shown in FIG. 1 will be described. When the processor 2 gives a burst transfer command to the DMA control circuit 4, the DMA control circuit 4 reads data from the memory 3 without passing through the processor 2 and gives a write signal S4a to the FIFO memory 5, Burst transfer of writing the read data into the FIFO memory 5 is performed. The data written in the FIFO memory 5 is
The data is taken out by the data transfer circuit 7 and sent to an external device (not shown).

At this time, in order to notify the processor 2 of the end of the burst transfer, the interrupt signal generation circuit 60 uses the DMA
The data transfer end signal S4b of the control circuit 4 is ON,
The three signals that the memory empty signal S5 of the FIFO memory 5 is on and the write signal S4a to the FIFO memory 5 exists (that is, the output signal S61 of the timer 61) are monitored, and the logical product of them is obtained. When all three inputs are turned on, an interrupt signal S62 is output. Thus, the processor 2 can know the timing of the end of burst / transfer by monitoring the interrupt signal S62 from the interrupt signal generation circuit 60, and immediately and accurately notify the external device of the timing. be able to.

Next, the operations (I) and (II) of FIG. 1 will be described with reference to FIG.
This will be described in more detail with reference to (a) and (b).

FIG. 3A shows an example in which writing to the FIFO memory 5 during burst transfer is performed without stagnation, and FIG. 3B.
Shows an example in which the writing to the FIFO memory 5 during the burst transfer is waited for the convenience of the data transfer bus 1.

(I) The operation DMA control circuit 4 shown in FIG. 3 (a) finishes outputting a prescribed number of write signals S4a consisting of pulse signals given to the FIFO memory 5, and at the same time, the DMA control circuit 4 transfers data. The end signal S4b is output to the AND circuit 62. After that, FIFO
There is no writing in the memory 5. Since the data transfer circuit 7 independently retrieves the data from the FIFO memory 5,
When the data stored in the FIFO memory 5 becomes empty, the memory empty signal S5 turns on.

On the other hand, the timer 61 turns on the timer output signal S61 after a certain time T _{w has} elapsed after the write signal S4a consisting of the pulse signal to the FIFO memory 5 disappeared. For this fixed time T _w , the write signal S4a is set to F
When the IFO memory 5 is given when it is empty, it is necessary to make it slightly longer than the time until the FIFO memory 5 turns off the memory empty signal S5, which is described later in (II). The operation will be described.

The AND circuit 62 has a data transfer end signal S.
4b, the timer output signal S61, and the memory empty signal S5 are all on, the interrupt signal S62 is given to the processor 2. Therefore, at this point, all the data in the FIFO memory 5 is transferred to the outside via the data transfer circuit 7. Have been transferred to.

(II) The operation DMA control circuit 4 shown in FIG. 3 (b) finishes outputting a prescribed number of write signals S4a consisting of pulse signals given to the FIFO memory 5, and at the same time, the DMA control circuit 4 transfers data. The end signal S4b is turned on. After that, there is no writing in the FIFO memory 5. The data transfer circuit 7 has its own FIFO memory 5
Since the data is taken out from the FIFO memory 5,
When the data stored in is empty, the memory empty signal S5 is turned on.

The difference from FIG. 3A is that during burst transfer,
Writing to the FIFO memory 5 is not performed at equal intervals, and the intervals of write pulses are widened at the time of final writing. Therefore, F
3A in that the IFO memory 5 is once emptied, then the final write is performed, the memory empty signal S5 of the FIFO memory 5 is turned off, and then turned on again.

In FIG. 3B, the time T _e is the time until the FIFO memory 5 turns off the memory empty signal S5 when the write signal S4a is given when the FIFO memory 5 is empty. Which is a unique value of the FIFO memory 5. Regarding the output signal S61 of the timer 61, the FI
For a certain time T after the writing pulse to the FO memory 5 disappears
_This signal is turned on after the elapse of _w , and in the case of FIG. 3B, there are two portions that are turned on due to the difference in write pulse intervals.

The AND circuit 62 receives the data transfer end signal S.
4b, the timer output signal S61, when the memory space signal S5 are all turned on, is configured to provide an interrupt signal S62 to the processor 2, the time T _w is managed by the timer 61 to be longer than the time T _e. Therefore, when the data transfer end signal S4b and the memory empty signal S5 are turned on, the interrupt signal S62 is not output from the AND circuit 62, and the data transfer end signal S4b, the timer output signal S61, and the memory empty signal S5 are turned on. Then, the AND circuit 62 gives an interrupt signal S62 to the processor 2. At this point, it is guaranteed that all the data in the FIFO memory 5 has already been transferred to the outside via the data transfer circuit 7.

As described above, this embodiment has the following advantages. In addition to the data transfer end signal S4b and the memory empty signal S5, a write signal S4a to the FIFO memory 5
The AND circuit 62 does not output the interrupt signal S62 for a certain period of time when the timer output signal S61 is turned on via the timer 61. Therefore, the interrupt signal S62 given to the processor 2 is transmitted from the FIFO memory 5 through the data transfer circuit 7 at the burst transfer end timing, no matter how the timing of the burst transfer changes or the number of burst words changes. It is possible to guarantee that the processor 2 accurately informs the external device of the timing when the data is transmitted to the outside. Therefore, the external device that receives the data via the data transfer circuit 7 can accurately recognize the timing that receives the last data of the burst data, so that, for example, the external receiving device is highly efficient and reliable. Highly efficient processing is possible.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications.

(I) In the above embodiment, the burst transfer end interrupt signal generating circuit 60 is provided with the timer 61 and the AND circuit 6.
Although the timer 61 is configured by other delay means, or by changing the polarities of the data transfer end signal S4b, the timer output signal S61 and the memory empty signal S5, the AND circuit 62 is configured by another gate circuit or the like. It is also possible to configure with.

(Ii) Various data transfer systems may be constructed by adding other functional blocks to the burst data transfer processing device of FIG. For example, F
The above-described embodiment can be applied to a general data transfer system in which the burst data transfer circuit using the IFO memory 5 and the processor 2 are combined, whereby the versatility of burst data transfer can be expanded.

[0042]

As described above in detail, according to the first aspect of the invention, the memory empty signal is on, the data transfer end signal is on, and the write signal does not exist for a certain period of time. Since the interrupt signal is supplied to the processor, the interrupt signal is not erroneously supplied to the processor, no matter how the timing of burst transfer changes or the number of burst words can be changed. It is possible to accurately notify the processor of the end of the burst transfer. Therefore, for example, an external receiving side device or the like can perform highly efficient and highly reliable processing.

According to the second aspect of the invention, since the burst transfer end interrupt signal is constituted by the timer and the AND circuit, the write signal is properly delayed by the timer, and the data transfer end signal, the timer output signal, and the memory empty signal. When all the signals are turned on, the AND circuit can accurately supply the interrupt signal to the processor with a simple structure.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a burst data transfer processing device incorporating a burst transfer end interrupt signal generation circuit showing an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a burst data transfer processing device incorporating a conventional burst transfer end interrupt signal generation circuit.

FIG. 3 is a timing chart showing the operation of FIG.

[Explanation of symbols]

1 data transfer bus 2 processors 3 memory 4 DMA control circuit 5 FIFO memory 7 Data transfer circuit 60 Burst transfer end interrupt signal generation circuit 61 timer 62 AND circuit S4a Write signal S4b Data transfer end signal S5 Memory empty signal S61 Timer output signal S62 interrupt signal

Claims (2)

[Claims] 1. When performing burst transfer by writing data in a burst into a first-in first-out memory for temporary storage of data by a direct memory access control circuit without passing through a processor for performing burst transfer termination processing, In the burst transfer end interrupt signal generation circuit for notifying the processor of the end of burst transfer in the form of an interrupt signal, a memory empty signal indicating that the memory area of the first-in first-out memory is empty is ON, and the direct memory access If the data transfer end signal indicating the end of data transfer by the control circuit is on, and the write signal given to the first-in first-out memory by the direct memory access control circuit does not exist for a certain period of time, the division Burst transfer end interrupt signal generation characterized by supplying an interrupt signal to the processor Road. 2. The burst transfer end interrupt signal generation circuit according to claim 1, wherein a timer for delaying a write signal supplied to the first-in first-out memory by a predetermined time, the memory empty signal, the data transfer end signal, and A burst transfer end interrupt signal generation circuit comprising: an AND circuit for obtaining a logical product of outputs of the timers and outputting the interrupt signal.