JPH04335458A - Information processor - Google Patents

Abstract

PURPOSE:To unitedly control the wait cycle to plural LSIs, and to eliminate the need of providing separately the wait cycle at every LSI. CONSTITUTION:When a CPU 1 leads out an address signal for selecting an LSI to an address 2, a chip enable signal corresponding to this address signal is generated from a decoder circuit 3. Based on a partial signal of this chip enable signal, a logic circuit 5 generates the number of waits peculiar to the selected LSI, and gives it to a counter 7 for executing a down-count operation. The counter 7 decreases the given number of waits, based on a clock signal phito the CPU 1. Subsequently, when a counting value is zero at the time when a clock is inputted, an acknowledge signal DTACK given to the CPU 1 from a borrow signal output terminal is inverted to a low level, and it is informed to the CPU 1 that the selected LSI becomes an operable state.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, such as a home controller, having a central processing unit and a plurality of integrated circuits.

0002

[Background Art] Conventionally, equipment control functions that control various electrical devices inside and outside the house, monitoring functions that issue various commands based on information from various sensors placed inside the house, and A home controller is used that centrally manages multiple functions, such as a schedule management function that records schedules and the like.

[0003] Such a home controller uses a CPU
(central processing unit) and multiple peripheral LSIs that handle individual functions
(large-scale integrated circuit). Peripheral LSIs include, for example, RAM (random access memory).
The number of peripheral LSIs is increasing as home controllers become more multifunctional. For example, the main board of the home controller "Gourmet Robot HAS-G200" (product name) manufactured by Sanyo Electric Co., Ltd. is 100
It is composed of more than one integrated circuit (including LSI and MSI (medium-scale integrated circuit)), and has a large-scale circuit configuration.

By the way, when a CPU accesses a peripheral LSI, a wait cycle occurs, which is a waiting time until each LSI becomes operational, and this wait cycle is unique to each LSI. For this reason, in the conventional home controller, a wait circuit is individually provided for each LSI to ensure a unique wait cycle for each LSI.

[0005]

[Problem to be Solved by the Invention] However, providing a separate wait circuit for each LSI in this way
This results in an increase in the number of parts, an increase in the scale of the circuit configuration, and an increase in cost. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned technical problems, to make it possible to handle wait cycles of multiple integrated circuits in a unified manner, to reduce the number of parts, and to downsize the circuit configuration. The object of the present invention is to provide an information processing device that can perform the following functions.

[0006]

[Means for Solving the Problems] To achieve the above object, an information processing device of the present invention includes a central processing unit, a plurality of integrated circuits selected by the central processing unit and made operable, and the above-mentioned integrated circuits. and chip enable signal generation means for generating a chip enable signal for enabling an integrated circuit selected by a central processing unit, in response to a chip enable signal from the chip enable signal generation means. , a wait number generating means for generating a unique wait number of the integrated circuit corresponding to the chip enable signal; a counting means for counting the number of waits generated by the wait number generating means based on a predetermined clock signal; means for setting a period before the counting means finishes counting the number of waits as a wait cycle; and canceling means for canceling the wait cycle in preparation for the next machine cycle when the counting means finishes counting the number of waits. This includes:

[0007]

According to the above structure, the wait number unique to the integrated circuit to be enabled by the chip enable signal is generated by the wait number generating means. and,
When the counting means performs a counting operation based on a predetermined clock signal, a period before the counting means finishes counting the wait number is defined as a wait cycle. Moreover, when this counting means finishes counting the above-mentioned weight cycles,
The canceling means cancels the wait cycle.

Since the wait number generation means generates the wait number corresponding to the chip enable signal, as a result,
Wait cycles corresponding to a plurality of integrated circuits can be uniformly controlled.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples will be explained in detail below with reference to the accompanying drawings showing examples. Note that in the accompanying drawings, an overline attached to a symbol representing a signal indicates that the signal is a negative logic signal, and the description of the overline is omitted in the specification. FIG. 1 is a block diagram showing the basic configuration of main parts of a home controller, which is an information processing device according to an embodiment of the present invention. This home controller has a CPU (Central Processing Unit) and multiple integrated circuits such as peripheral LSIs and MSIs that implement various functions based on commands from the CPU, and each integrated circuit has a unique wait cycle. are uniformly controlled.

[0010] For example, a CPU 1 such as Motorola's MC68000 uses a RAM (random access memory),
Among a plurality of peripheral LSIs (not shown) such as a ROM (read-only memory) and a clock LSI, an LSI to be enabled for operation is selected. In this embodiment, for example, the wait cycles of eight types of LSIs are controlled, and the LSI
The selection of I is based on some signals AB20 and A of the address bus 2.
This is performed by B21 and AB22. This signal AB20,
AB21 and AB22 are applied to the decoder circuit 3 which generates a chip enable signal to enable the selected LSI. This decoder circuit 3 is a CPU
In response to the signal AS indicating that the address signal from 1 has been determined, a logic "0" signal is derived from one of the eight output terminals Y0 to Y7, and a logic "0" signal is derived from the remaining terminals. Derive a signal of "1". The eight output terminals Y0 to Y7 are connected to the chip enable signal input terminal of each LSI via line 4, and only the LSI corresponding to the chip enable signal derived to the terminals Y0 to Y7 is in an operable state. Become.

Of the output terminals Y0 to Y7 of the decoder circuit 3, signals from terminals Y1, Y2, and Y3 are applied to a logic circuit 5, which is a wait number generating means. This logic circuit 5 includes four AND gates 11 to 14, an OR gate 21 that takes the logical sum of the outputs of the AND gates 11 and 12, and an
It has an OR gate 22 that takes the logical sum of the outputs of the ND gates 13 and 14. The chip enable signal from the output terminal Y1 is inverted and input to the AND gate 11, and is input to the AND gate 12 as is. Also, the chip enable signal from output terminal Y3 is AND
It is given as is to gate 11, and AND
The signal is inverted and inputted to the gate 12. Furthermore, the chip enable signal from this output terminal Y3 is input as is to one terminal of the AND gate 13, and is inverted and input to one terminal of the AND gate 14. The chip enable signal from output terminal Y2 is applied to AND gate 1.
The signal is inverted and inputted to the other terminal of the AND gate 14, and is further applied as is to the other terminal of the AND gate 14.

Since only one of the chip enable signals from the output terminals Y0 to Y7 becomes logic "0",
If a logic "0" signal is derived from either terminal Y1 or Y3, the output of the OR gate 21 becomes logic "1". Furthermore, if a logic "0" signal is derived from either terminal Y2 or Y3, the output of the OR gate 22 becomes a logic "1".
becomes.

The logic circuit 5 converts the outputs of the OR gates 21 and 22 into a wait number expressed in two bits, and this wait number is sent from a line 6 to a counter 7 which functions as a counting means and a canceling means. given to. on the other hand,
Chip enable signals from output terminals Y0 to Y7 of the decoder circuit 3 are applied to a NOR gate 8. This N
The output of the OR gate 8 is sent to a delay circuit 9 composed of an inverting circuit.
The signal is inputted to the counter 7 as a data write signal via. This counter 7 calculates the wait number from line 6 at terminals D0 and D in synchronization with the falling edge of the data write signal.
Incorporate into 1. Then, a down-count operation is performed in synchronization with the rise of the clock signal φ applied to the clock input terminal CLK, and the wait number applied from the terminals D0 and D1 is decreased by one.

Since the clock signal φ is a clock for the CPU 1, it corresponds to its basic cycle. Therefore, after the counter 7 first performs a down-count operation, the count value of the counter 7 passes through a state of zero, and then
Furthermore, the time until the next clock is input corresponds to a wait cycle specific to the selected LSI. The signal derived from the borrow signal output terminal Borrow of the counter 7 is outputted to the CP as an acknowledge (response) signal DACK.
It is given to U1. That is, the signal derived from this borrow signal output terminal Borrow is at a high level when the counter 7 holds a value of zero or more, and when the clock signal φ rises, the count value of the counter 7 becomes zero. is inverted to low level. Therefore, when a low level signal is derived from the borrow signal output terminal Borrow, the LSI is in an operable state because the wait cycle specific to the peripheral LSI selected by the CPU 1 has elapsed. Therefore, if the signal from the borrow signal output terminal Borrow is given to CPU1 as an acknowledge signal, CPU1
can be kept in a waiting state for only the time necessary for the selected LSI.

The counter 7 is kept in a clear state when the signal applied from the NOR gate 8 to the borrow clear terminal Borrow Clear is at high level, and when this signal becomes low level, it latches and counts the wait number from terminals D0 and D1. Operation is allowed. Therefore, if all of the chip enable signals derived on line 4 are logic "0", counter 7 will be in a clear state. Immediately before the data write signal is applied from the delay circuit 4, latching and counting are allowed.

Table 1 below shows the wait numbers of the eight types of LSIs ■ to ■ to be selected by the CPU 1, and the wait numbers derived to the output terminals Y0 to Y7 of the decoder circuit 3 when these peripheral LSIs are selected. 2 is a truth table showing the relationship between a signal, a 2-bit signal representing the number of waits given to data terminals D0 and D1 of a counter 5, and a decoder circuit 3. In this example, the wait number of LSI ■ is "0",
The weight number of LSI■ is "1", the weight number of LSI■ is "2", and the weight number of LSI■ is "3".
, and the weight numbers of the remaining LSIs ■～■ are all ``
0".

[0017]

[Table 1]

It is understood from Table 1 that the LSI wait number corresponding to the chip enable signal is generated from the logic circuit 5 and given to the counter 7. It goes without saying that the logic circuit 5 may be changed as appropriate depending on the number of waits required in each LSI. Figure 2
is a timing chart to explain the operation,
When operating LSI ■, that is, the number of waits is "2".
” is shown. 2(a) shows the clock signal φ, FIG. 2(b) shows the address signal derived to the address bus 2, and FIG. 2(c) shows the signal AS indicating that the address has been determined. Furthermore, Figure 2 (
d) shows the output signal from the terminal Y2 from which a logic "0" signal is derived corresponding to LSI ■ in the decoder circuit 3, and FIG. 2(e) shows the output signal from the NOR gate 8 to the borrow clear terminal of the counter 7. 2(f) shows the number of waits given to the terminals D0 and D1, and FIG. 2(g) shows the clear signal given to the delay circuit 4.
From the data load terminal of counter 7 DATA Load
FIG. 2(h) shows the acknowledge signal DTACK given to the CPU 1 from the borrow signal output terminal Borrow.

The basic instructions of CPU1 are eight states S0.
- S8, and SW0 and SW1 in FIG. 2 are wait cycles. During the period from time t1, the CPU 1 derives an address signal corresponding to LSI ■ to the address bus 2, and further, at time t2, sets the signal AS to a low level to notify the decoder circuit 3 that the address has been determined. In response to this, the decoder circuit 3 outputs a logic "0" to the terminal Y2 corresponding to the LSI ■, as indicated by the reference symbol A1.
A signal of logic "1" is derived from the remaining terminals Y0, Y1, Y3 to Y7. As a result, the output of the NOR gate 8 becomes low level, and this NOR gate 8
By applying the output as a clear signal to the borrow clear terminal Borrow Clear of the counter 7, the counter 7 becomes capable of latching and counting data from the terminals D0 and D1.

On the other hand, the terminals Y1, Y2,
The logic circuit 5, to which the signal from Y3 is applied, outputs logic signals to the terminals D1 and D2 of the counter 7 via the line 6, respectively.
Input the signals of "0" and "1". Borrow clear terminal Bo
At time t3, after the delay time in the delay circuit 9 has elapsed since the input signal to rrow Clear became low level, the data load terminal DATA L of the counter 7
The input signal to oad will fall. In synchronization with this, the counter 7 internally takes in the wait number ("2" in the present example) from the data input terminals D0 and D1.

From this state, the counter 7 decrements the count at times t4, t5, and t6 when the clock signal φ rises. As a result, at time t6, the acknowledge signal DTACK derived from the borrow signal output terminal Borrow falls, and the CPU 1 is notified that the LSI ■ is in an operable state. In the CPU 1, the acknowledge signal DTACK is determined at the falling edge of the clock signal φ (time t10) at the end of the state S4. That is, at time t10, the acknowledge signal DTACK is at a high level, so the CPU 1 enters a wait state (wait cycle SW0). Then, a similar determination is made at the next time t11 when the clock signal φ falls, and even at this time, the acknowledge signal DTACK is
Since is at a high level, the CPU 1 continues to be kept in a waiting state (wait cycle SW1).

At time t12 when the clock signal φ falls at the end of the wait cycle SW1, the acknowledge signal DTACK is at a low level, so at this point the wait cycle is canceled in preparation for the next machine cycle. The next state is S5. In this way, wait cycles SW0 and SW1 for two periods of the clock signal φ from time t10 to time t12 can be secured.

As described above, according to the configuration of this embodiment, the logic circuit 5 generates a unique wait number for the selected LSI in response to the chip enable signal generated from the decoder circuit 3. This wait number is given to a counter 7 that performs a down-count operation. Then, at the point when the clock signal φ falls after the count value of the counter 7 becomes zero, the acknowledge signal DTACK derived from the borrow signal output terminal Borrow is inverted to low level, and the selected LSI becomes operational. Being in a state is C
PU1 is notified. In this way, a wait cycle specific to each LSI can be generated uniformly without providing a separate wait circuit for each LSI. As a result, the number of parts of the home controller can be significantly reduced and the circuit configuration can be downsized, and the circuit configuration can be simplified and costs can be significantly reduced.

It should be noted that the present invention is not limited to the above embodiments. For example, in the above embodiment, a home controller was taken as an example, but the present invention also includes a central processing unit,
The present invention can be widely implemented in information processing apparatuses that include a plurality of integrated circuits and selectively enable the integrated circuits. In addition, various design changes can be made without changing the gist of the present invention.

[0025]

As described above, according to the information processing apparatus of the present invention, wait cycles corresponding to a plurality of integrated circuits can be uniformly controlled. This eliminates the need to provide a separate wait circuit for each integrated circuit, so the number of parts of the information processing device can be significantly reduced and the circuit configuration can be made smaller. As a result, the configuration becomes simple and can also contribute to reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of main parts of a home controller that is an embodiment of an information processing device of the present invention.

FIG. 2 is a timing chart for explaining the operation.

[Explanation of symbols]

1 CPU (Central Processing Unit)

Claims (1)

[Claims] Claims: 1. A central processing unit, a plurality of integrated circuits selected by the central processing unit to be enabled, and a chip enable signal for enabling the integrated circuits selected by the central processing unit to be enabled. In an information processing apparatus having a chip enable signal generating means for generating a chip enable signal, in response to a chip enable signal from the chip enable signal generating means, a wait number that generates a unique wait number of an integrated circuit corresponding to the chip enable signal. generating means; counting means for counting the number of waits generated by the wait number generating means based on a predetermined clock signal; and means for defining a period before the counting means finishes counting the number of waits as a wait cycle. and a canceling unit for canceling the wait cycle in preparation for the next machine cycle when the counting unit finishes counting the number of waits.