JPS6235143B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an information processing device having a signal generation circuit that receives a signal from an external circuit and generates an internal signal based on the input signal.

Conventionally, in an information processing device controlled by a microprogram, a change in a signal from an external circuit is detected, an internal control signal (for example, an interrupt signal, etc.) is generated at the time of this change, and this interrupt signal There is a known processing method in which a central processing unit (hereinafter referred to as CPU) is input to execute interrupt processing. In this process, depending on the differences in external circuits, whether the rising edge, falling edge, or both of the signals are detected and the CPU executes the interrupt processing is controlled differently depending on the function of the device. Not uniform for use as a signal. For this reason, a conventional information processing device has a first input terminal for detecting the rising edge of a signal and generating the first interrupt signal, and a second input terminal for detecting the rising edge of the signal and generating the second interrupt signal. Two input terminals are provided separately, and separate detection circuits are required for each. However, when this is applied to large-scale integrated circuits (hereinafter referred to as LSI), the number of pins and hardware increases, resulting in a lack of versatility.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device having a signal generation circuit that eliminates the above-mentioned drawbacks and can discriminate signals with a small number of pins and a small amount of hardware.

This invention will be explained below with reference to the drawings.

In FIG. 1, which shows a conventional interrupt signal generation circuit, F11 to F14 are D-type flip-flops, N11 and N12 are inverters, and A
11 and A12 are AND gates, C11 is an interrupt control circuit, and φ is a clock. I20 in Figure 2 now
is used as one input signal from an external circuit, changes in both the rising and falling edges are detected to generate an interrupt signal, which is sent via the interrupt control circuit C11.
When inputting to a CPU (not shown) to execute interrupt processing, input signal I20 is introduced to both signal input terminals I11 and I12 shown in FIG. At time t21 shown in FIG. 2, the flip-flop F11 is at a high level (hereinafter referred to as "1").
Since the flip-flop F12 is at a low level (hereinafter referred to as "0"), the AND gate A11 becomes "1" and generates an interrupt signal. After time t21, flip-flops F11 and F12 become "1", so the output of AND gate A11 becomes "0". Therefore, AND gate A11 is A21
This circuit generates the first interrupt signal at the rising edge of the input signal I20 with the waveform shown in FIG. On the other hand, at time t22, flip-flop F13 becomes "0" and flip-flop F14 becomes "1", so AND gate A
12 becomes "1", and an interrupt signal having the waveform shown in A22 is generated. Therefore, AND gate A12 is a circuit that generates a second interrupt signal at the rising edge of input signal I20. That is, conventionally, two types of input terminals I11,
Since it is necessary to provide I12 and add a separate interrupt signal generation circuit to each, when applied to LSI, the number of pins and the number of interrupt signal generation circuits will increase, which will hinder the cost reduction of LSI. There was a drawback.

FIG. 3 is a block diagram showing a reference diagram of the present invention, which includes a circuit for detecting the rising edge of an input signal,
The interrupt signal generation circuit includes a circuit for detecting a falling edge, and inputs an input signal of the detection circuit from the same terminal. F31 and F32 are flip-flops, N31 and N32 are inverters, and A
31 and A32 are AND gates, 31 is an OR gate, and C31 is an interrupt control circuit.

When input signal I20 from the external circuit shown in FIG. 2 is introduced into the input terminal of I31, flip-flop F31 becomes "1" and F3 becomes "1" at time t21.
2 becomes "0", AND gate A31 becomes "1", and OR gate 31 becomes "1", so input signal I
A first interrupt signal is generated when the rising edge of 20 is detected. On the other hand, at time t22, flip-flop F31 becomes "0" and F32 becomes "1".
AND gate A32 becomes "1", OR gate 32 becomes "1", and a second interrupt signal is generated by detecting the fall of input signal I20, and these two interrupt signals are controlled by interrupt control circuit C31. controlled by CPU
sent to. Also, at time t23, time t
This is the same as in case 21. At times other than the above, AND gates A31 and A32 are all "0", so OR gate 31 is "0" and no interrupt signal is generated. Therefore, OR gate 31
The output is the waveform shown in 21, which generates two interrupt signals when both the rising and falling edges of the input signal I20 change.

In this way, two different interrupt signals can be generated using one input signal terminal and one signal generation circuit, which simplifies the circuit configuration and reduces the number of pins, making it very effective for LSI implementation. It is. However, although it is possible to generate two types of signals at the falling edge and rising edge, since signals that were conventionally input from separate terminals are combined into one terminal, the generated signal may be based on the rising edge or the rising edge. There is an inconvenience that it is not possible to determine whether it is based on the downlink. Therefore, even if a signal is generated, the meaning of the signal is unknown, and more complex circuits or functions are required to perform appropriate processing.

FIG. 4 is a block diagram showing an embodiment of the present invention that solves the above problem.
is micro order (micro instruction) M41,
This is a set/reset type flip-flop controlled by M42.

This flip-flop F45 is added to the circuit shown in FIG. 3, and AND gates A41 and A42 are
I'm trying to control it. Now, if the Q output of flip-flop F45 is set to "1" (=0), only the rising edge of the input signal will be detected, and if the output of flip-flop F45 is set to "1" (Q=0), the input signal will be Only the falling edge of can be detected, making it possible to generate either one of the interrupt signals. Also,
After interrupt processing, if the output of flip-flop F45 is controlled to be inverted, it is possible to generate both interrupt signals.

That is, by adding such a selection circuit, it is possible to give meaning to the generated signal, and it is possible to achieve the excellent effect of being able to identify the signal without providing any other additional circuit. . Moreover, since flip-flops can be controlled by microinstructions (software), no complicated control is required.

As is clear from the above explanation, according to the present invention, two meaningful interrupt signals can be generated by detecting each of the rising and falling edges of an input signal using one terminal, and one terminal can generate two meaningful interrupt signals. It is also possible to selectively generate only the

Therefore, according to the present invention, it is possible to reduce the number of pins and hardware, and it is possible to provide an information processing device that is extremely effective and highly versatile, especially for LSI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional information processing device, FIG. 2 is a timing chart for explaining FIGS. 1 and 3, FIG. 3 is a block diagram showing a reference diagram of the present invention, and FIG. The figure is a block diagram showing one embodiment of the present invention. F11, F12, F31, F14, F31, F
32, F41, F42...D type flip-flop, N11, N12, N13, N32, N41,
N42...Inverter, A11, A12, A3
1, A32, A41, A42...AND gate,
31, 41...OR gate, F45...set/reset type flip-flop, C11,C
31, C41...Interrupt control circuit, I11, I1
2, I31, I41...External input signal input terminal,
I20...External input signal, φ...Clock signal.

Claims (1)

[Claims] 1: an input pin to which an input signal is input; a first flip-flop connected to the input pin; a second flip-flop receiving the output of the first flip-flop; a first circuit that detects the rising edge of the input signal based on the output of the flip-flop and generates a first pulse; and a first circuit that detects the rising edge of the input signal based on the output of the first flip-flop and the output of the second flip-flop; a second circuit that detects the falling edge and generates a second pulse; a third flip-flop whose state is set by a command; and a third flip-flop whose state is set according to a command; An information processing device comprising: a selection circuit for selecting one of the pulses; and means for supplying the selected pulse to a processing circuit via a common terminal.