JPS61150062A - Interruption control circuit - Google Patents
Interruption control circuitInfo
- Publication number
- JPS61150062A JPS61150062A JP27713484A JP27713484A JPS61150062A JP S61150062 A JPS61150062 A JP S61150062A JP 27713484 A JP27713484 A JP 27713484A JP 27713484 A JP27713484 A JP 27713484A JP S61150062 A JPS61150062 A JP S61150062A
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- interruption
- terminal
- cpus
- factor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はマイクロコンピュータの割込み制御回路に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interrupt control circuit for a microcomputer.
従来の技術
従来の割込み制御では、第２図に示すように、端子１か
ら入力された割込み要因の信号を割込み検知部７で検出
し１割込み要求信号８を出力する（例えば、特開昭５７
−１６５６５７号公報）。2. Description of the Related Art In conventional interrupt control, as shown in FIG.
-165657).
ＣＰＵ２は割込み要求信号８の受理によって、割込み処
理を行なう。まだ、ＣＰＵ２には割込み要因入力の端子
１が、ＣＰＵ５には割込み要因入力の端子１０が固定さ
れている。Upon receiving the interrupt request signal 8, the CPU 2 performs interrupt processing. The interrupt factor input terminal 1 is still fixed to the CPU 2, and the interrupt factor input terminal 10 is fixed to the CPU 5.
発明が解決しようとする問題点
しかしながら上記の構成では、ひとつのＣＰＵに対して
、割込み要因を入力する端子が固定されているため、割
込み要因入力の端子を複数のＣＰＵに対して任意に割り
当てることができないという問題点を有していた。Problems to be Solved by the Invention However, in the above configuration, the interrupt factor input terminal is fixed for one CPU, so it is not possible to arbitrarily allocate the interrupt factor input terminal to multiple CPUs. The problem was that it was not possible.
そこで本発明は、上記のような、割込み要因を入力する
端子の使用制限を無くし、割込み要因入力の端子を複数
のＣＰＵで共用可能とするだめの割込み制御回路を提供
することを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an interrupt control circuit which eliminates the above-mentioned restrictions on the use of the interrupt factor input terminal and allows the interrupt factor input terminal to be shared by a plurality of CPUs.
問題点を解決するための手段
本発明は、複数のＣＰＵが共用する、割込み要因入力の
端子と、端子から入力した割込み要因によって複数のＣ
ＰＵのうちいずれのＣＰＵで割込みを受理させるかを指
定フラグと、端子からの割込み要因の信号と指定フラグ
の信号とを入力して、複数のＣＰＵに対し、割込みを時
分割で検出して割込み要求信号を分配し出力する割込み
分配手段を備えた割込み制御回路である。Means for Solving the Problems The present invention provides an interrupt factor input terminal that is shared by multiple CPUs, and an interrupt factor input terminal that is shared by multiple CPUs.
By inputting a flag specifying which CPU among the PUs should accept the interrupt, the signal of the interrupt cause from the terminal, and the signal of the specified flag, interrupts can be detected and issued to multiple CPUs in a time-sharing manner. This is an interrupt control circuit equipped with an interrupt distribution means for distributing and outputting request signals.
作 用
本発明は前記した構成により、端子から入力した割込み
要因を、指定フラグの値に基づいて、各ＣＰＵに対応し
たタイミングで検出し、割込み要求信号を複数のＣＰＵ
に分配して出力することによって、複数のＣＰＵで割込
み要因入力の端子を共用することができる。Effect: With the above-described configuration, the present invention detects an interrupt factor input from a terminal at a timing corresponding to each CPU based on the value of a designated flag, and sends an interrupt request signal to multiple CPUs.
By distributing and outputting the interrupt factor to multiple CPUs, the interrupt factor input terminal can be shared by a plurality of CPUs.
実施例
第１図は本発明の割込み制御回路の一実施例を示す図で
ある。第１図において、１は割込み要因を入力する端子
、２及び３は割込み要求によって割込み処理を行なうＣ
ＰＵ、４は端子１からの割込み要因によってＣＰＵ２及
び３のどちらのＣＰＵに割込みを受理させるかを指定す
る指定フラグ、５は端子１からの割込み要因を、指定フ
ラグ４の値に基づき、それぞれのＣＰＵに対応したタイ
ミングで撮り分けるだめのゲート、６はゲート６の出力
信号、７は割込み要因発生の有無を検出する割込み検知
部、８は割込み検知部７より出力される割込み要求信号
、Ｔ１はＣＰＵ２に、Ｔ２はＣＰＵ３にそれぞれ対応し
たタイミングである。Embodiment FIG. 1 is a diagram showing an embodiment of the interrupt control circuit of the present invention. In Figure 1, 1 is a terminal for inputting an interrupt factor, and 2 and 3 are C terminals that perform interrupt processing in response to an interrupt request.
PU, 4 is a designation flag that specifies which of CPUs 2 and 3 will accept the interrupt depending on the interrupt factor from terminal 1, and 5 is a designation flag that specifies the interrupt factor from terminal 1, based on the value of designation flag 4. 6 is an output signal of the gate 6; 7 is an interrupt detection unit that detects whether or not an interrupt factor has occurred; 8 is an interrupt request signal output from the interrupt detection unit 7; Timings corresponding to CPU2 and T2 correspond to CPU3, respectively.
以上のように構成された本実施例の割込み制御回路につ
いて、動作を説明する。指定フラグ４の値が１″のとき
、端子１から入力された割込み要因は、Ｔ１のタイミン
グで、そのままゲート５の出力信号６に出力され、出力
信号６を入力した割込み検知部７は割込み発生を検出し
割込み要求信号８を出力する。Ｔ１のタイミングで割込
み要求信号８はＣＰＵ２に伝達され、ＣＰＵ２は割込み
処理を行なうことになる。−Ｔ２のタイミングでは、指
定７ラグ４の値が”１”なのでゲート５は開かず、割込
み要因は割込み検知部に伝達されない。従って指定フラ
グの値が“１″のとき、Ｔ２のタイミングでは、ＣＰＵ
３に割込みはかからない。同様に、指定フラグの値がＩ
Ｉ ｏＩＩのとき、Ｔ２のタイミングで、割込み要因が
検出され、割込み要求信号８はＣＰＵａに伝達される。The operation of the interrupt control circuit of this embodiment configured as described above will be explained. When the value of the designated flag 4 is 1'', the interrupt factor input from the terminal 1 is output as is to the output signal 6 of the gate 5 at the timing of T1, and the interrupt detection section 7 that inputs the output signal 6 generates an interrupt. is detected and outputs the interrupt request signal 8. At the timing T1, the interrupt request signal 8 is transmitted to the CPU 2, and the CPU 2 performs the interrupt processing. - At the timing T2, the value of the specified 7 lag 4 is "1". ”, so gate 5 does not open and the interrupt factor is not transmitted to the interrupt detection unit. Therefore, when the value of the designated flag is “1”, at timing T2, the CPU
3 is not interrupted. Similarly, the value of the specified flag is I
At the time of IoII, an interrupt factor is detected at timing T2, and the interrupt request signal 8 is transmitted to the CPUa.
つまり、指定フラグ４の値が“１”のとき、端子１はＣ
ＰＵ２の割込み要因入力の端子となり、また指定フラグ
４の値が′○”のとき、端子１はＣＰＵ３の割込み要因
入力の端子となる。In other words, when the value of designation flag 4 is "1", terminal 1 is connected to C
The terminal 1 becomes the interrupt factor input terminal for the PU2, and when the value of the designation flag 4 is '○'', the terminal 1 becomes the interrupt factor input terminal for the CPU3.
以上のように本実施例によれば１割込み要因を２つのＣ
ＰＵに対応したタイミングで検出することにより、割込
み検知部の数を増やすことなくひとつの割込み要因入力
の端子を２つのＣＰＵで共用することができる。As described above, according to this embodiment, one interrupt factor is divided into two C
By detecting at a timing corresponding to the PU, one interrupt factor input terminal can be shared by two CPUs without increasing the number of interrupt detection units.
なお、本実施例において、ひとつの割込み要因によって
２つのＣＰＵのうちどちらか一方のＣＰＵに割込みを受
理させるとしたが、ひとつの割込み要因によって、同時
に２つのＣＰＵに割込みを受理させることもできる。ま
た、本実施例を、ひとつの端子と２つのＣＰＵで構成し
たが、端子及びＣＰＵの数を２つ以上として、複数のＣ
ＰＵが、ひとつもしくは複数の端子を共用してもよい。In this embodiment, one interrupt factor causes one of the two CPUs to accept an interrupt, but one interrupt factor can also cause two CPUs to accept an interrupt at the same time. In addition, although this embodiment is configured with one terminal and two CPUs, it is also possible to configure the number of terminals and CPUs to be two or more.
PUs may share one or more terminals.
発明の詳細
な説明したように、本発明によれば、ひとつのＣＰＵに
対して割込み要因入力の端子が固定されているという従
来の使用制限を無くし、割込み要因入力の端子を複数の
ＣＰＵで共用させることができる。As described in detail, according to the present invention, the conventional usage restriction that the interrupt factor input terminal is fixed for one CPU is eliminated, and the interrupt factor input terminal can be shared by multiple CPUs. can be done.
第１図は本発明の一実施例における割込み制御回路を示
す図、第２図は従来の割込み制御を示すブロック図であ
る。
１・・・・・・割込み要因入力の端子、２，３・・・・
・・ＣＰＵ、 ′４・・−・・・・指定フラグ、
９・・・・・・割込み分配手段。FIG. 1 is a diagram showing an interrupt control circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing conventional interrupt control. 1... Interrupt factor input terminal, 2, 3...
...CPU, '4...Specified flag,
9... Interrupt distribution means.
Claims (1)
Ｕと、前記複数のＣＰＵが共用する割込み要因入力の端
子と、前記端子からの割込み要因によって前記複数のＣ
ＰＵのうちいずれのＣＰＵに割込みを受理させるかを指
定する指定フラグと、前記端子からの割込み要因の信号
と前記指定フラグの信号とを入力して、前記複数のＣＰ
Ｕにそれぞれ対応したタイミングで、割込み要因発生の
有無を検出し、割込み要求信号を前記複数のＣＰＵに分
配して出力する割込み分配手段とを備えたことを特徴と
する割込み制御回路。Multiple CPs that perform interrupt processing based on interrupt request signals
U, an interrupt factor input terminal shared by the plurality of CPUs, and an interrupt factor input terminal shared by the plurality of CPUs;
A designation flag that designates which CPU among the PUs is to be made to accept an interrupt, a signal of the interrupt cause from the terminal, and a signal of the designation flag are input, and the plurality of CPUs
An interrupt control circuit comprising interrupt distribution means for detecting the occurrence of an interrupt factor at timings corresponding to respective CPUs, and distributing and outputting an interrupt request signal to the plurality of CPUs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27713484A JPS61150062A (en) | 1984-12-24 | 1984-12-24 | Interruption control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27713484A JPS61150062A (en) | 1984-12-24 | 1984-12-24 | Interruption control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61150062A true JPS61150062A (en) | 1986-07-08 |
Family
ID=17579263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27713484A Pending JPS61150062A (en) | 1984-12-24 | 1984-12-24 | Interruption control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61150062A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7150858B2 (en) | 2000-08-18 | 2006-12-19 | Arkray, Inc. | Centrifugal separator |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5556260A (en) * | 1978-10-20 | 1980-04-24 | Nec Corp | Information processor |
-
1984
- 1984-12-24 JP JP27713484A patent/JPS61150062A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5556260A (en) * | 1978-10-20 | 1980-04-24 | Nec Corp | Information processor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7150858B2 (en) | 2000-08-18 | 2006-12-19 | Arkray, Inc. | Centrifugal separator |
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