JPH07295949A - Multi-cpu processing system provided with two system buses - Google Patents

Abstract

PURPOSE:To provide a multi-CPU processing system for which a system bus is divided, plural CPUs are connected to the respective system buses, loads are distributed and functions are distributed. CONSTITUTION:First CPU groups 101, 102,..., 10n are in charge of a processing relating to the system bus 60 based on the mediation of a bus/interruption mediation circuit 20 and second CPU groups 10n+1, 10n+2,..., 10m are in charge of the processing relating to the system bus 70 based on the mediation of the bus/interruption mediation circuit 50. A dual port shared memory 40 is used for the processing when it is needed. When the first CPU groups are required to perform communication with the side of the system bus 70 and when the second CPU groups are required to perform the communication with the side of the system bus 60, the bus/interruption mediation circuits 20 and 50 let the communication be executed through an inter-system-bus communication line 80 and the dual port shared memory 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tightly coupled shared memory multi-CPU processing system.

[0002]

2. Description of the Related Art With the development of microcomputers, distributed processing devices using a plurality of microcomputers are widely used in industry. For example, there is a multi-CPU method to improve the system performance. The multi-CPU system is classified according to the processing system. (1) Each processor has the same function and shares the load evenly. There is a function distribution type that is a system having functions. Further, the classification by the coupling method includes (1) a tight coupling type characterized by bus connection and (2) a loose coupling type characterized by interprocessor communication.

FIG. 2 shows a tightly coupled shared memory type multi-C.
It is a block diagram which shows the prior art example of a PU processing system. C
PU11 ₁ , 11 ₂ , ~, 11 _p , and I / O 31 ₁ , 3
1 ₂ , ..., 31 _q and the shared memory 41 are the system bus 6
1 is connected. In this case, the bus / interrupt arbitration circuit, the CPU 11 _1, 11 _2, ~, are integrated with 11 _p and substrate.

[0004]

In the conventional multi-CPU processing system shown in FIG. 2, the overhead of accessing the shared memory due to the increase in the number of CPUs becomes a problem.
Further, since each CPU is on the same bus, it is necessary to put the bus / interrupt arbitration circuit in the board of each CPU, which makes the arbitration circuit complicated and increases the circuit scale of each board. . Further, in the loosely coupled type, the overhead due to the communication between the CPUs becomes large, so it is necessary to devise a special circuit or the like so as to minimize the overhead. On the other hand, in the two-function distributed type, it is usually necessary to appropriately allocate functions to each dedicated processor.
There were various problems such as the effect of being converted to PU cannot be obtained.

The present invention solves the above-mentioned problems found in load distribution and function distribution by making the bus division and dual port shared memory and the bus / interrupt arbitration circuit independent based on the load distribution type. It is an object of the present invention to provide a multi-CPU processing system having a simple structure with improved processing capability and distributed functions.

[0006]

In order to solve the above problems, a tightly coupled shared memory multi-CPU processing system of the present invention is provided with a first and a second system buses and a first and a second system. First and second input / output devices that are respectively connected to the buses and that make interrupt requests to the first and second system buses, and that are respectively connected to the first and second system buses, and have a tightly coupled configuration. A first and a second CPU group consisting of only a plurality of CPUs, and a first and a second port are connected to a first and a second system bus, respectively.
A dual-port shared memory that functions as a shared memory for the second CPU group, and a bus that is connected to the first and second system buses, respectively, and that the first and second CPU groups perform on the first and second system buses, respectively. Between the first CPU group and the second CPU group while arbitrating the acquisition request and the interrupt request and the interrupt requests made by the first and second input / output devices to the first and second system buses, respectively. And the first and second bus / interrupt arbitration circuits for performing the communication of 1) via the dual port shared memory.

[0007]

The first CPU group shares the processing relating to the first system bus based on the arbitration of the first bus / interrupt arbitration circuit, and the second CPU group the second bus / interrupt arbitration. The processes related to the second system bus are shared based on the arbitration of the circuit. Dual port shared memory is used when needed for this process. When the first CPU group needs to communicate with the second system bus side,
When it becomes necessary for the CPU group of 1 to communicate with the first system bus side, the first and second bus / interrupt arbitration circuits execute this communication via the dual port shared memory.

[0008]

Embodiment 1 Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a multi-CPU processing system of the present invention. CPU10 ₁ ,
10 ₂ , ..., 10 _n , the bus / interrupt arbitration circuit 20, and I
/ O 30 ₁ , 30 ₂ , ..., 30 _i and one port of the dual port shared memory 40 are connected via the system bus 60. Also, CPUs 10 _{n + 1} , 10 _{n + 2} ,
~, 10 _m , bus / interrupt arbitration circuit 50, and I / O3
0 _{i + 1} , 30 _{i + 2} , ..., 30 _j and the other port of the dual port shared memory 40 are connected via the system bus 70. The bus / interrupt arbitration circuits 20 and 50 are connected by a system bus communication line 80.

Next, the multi-CPU operation of the embodiment shown in FIG. 1 will be described. CPU1 connected to system bus 60
A bus acquisition request for 0 ₁ , 10 ₂ , ..., 10 _n to use the system bus 60 is arbitrated by the bus / interrupt arbitration circuit, and the CPU that receives the signal of the arbitration result becomes the bus master and the system bus 60 To use.

After using the system bus 60 of the bus master,
If there is a bus acquisition request from another CPU connected to the system bus 60, the bus / interrupt arbitration circuit 20 notifies the CPU that has requested the bus acquisition of the arbitration result. Also, I / O3
_{0 1, 30 2, ~,} 30 i and CPU10 _1, 10 _2,
~, Also all interrupt request from 10 _n, is processed by the bus / interrupt arbitration circuit 20. CPU10 _1, 10 _2, ~,
For communication during 10 _n , data can be shared and communicated by using the dual port shared memory 40.

The operation on the system bus 70 is CP
U10₁, 10₂, ~, 10_nCPU 10_{n + 1}, 1
0_{n + 2}, ~, 10_mI / O30₁, 30₂, ~, 30_i
I / O30 _{i + 1}, 30_{i + 2}, ~, 30_jOn the bus / interruption
The arbitration circuit 20 to the bus / interrupt arbitration circuit 50, respectively.
Considering it as a replacement, the operation on the system bus 60 is
Easy to understand.

As is clear from the above description of the embodiment, C
PU10 ₁ , 10 ₂ , ~, 10 _n are I / O 30 ₁ , 3
0 _2, -, first the same to accommodate the processing of requests 30 _i
Since the above program can be executed, the load can be shared by a plurality of CPUs. Also, CPU1
0 _{n + 1} , 10 _{n + 2} , ..., 10 _m are also I / O 30 _{i + 1} , 3
Since the same second program that can handle the processing requested by 0 _{i + 2} , ..., 30 _j is made executable, I / O 3
Multi CPU load distribution can be realized corresponding to 0 _{i + 1} , 30 _{i + 2} , ..., 30 _j , and CPUs 10 ₁ , 10 ₂ ,
~, It can work function of different second programs and 10 _n. In other words, by separating the system bus 60 and the system bus 70, a program suitable for I / O-specific processing on each system bus can be applied to the CPU on each system bus.

Due to the aforementioned bus separation, the system bus 60
The load can be distributed between the system side and the system bus 70 side, and the function distribution can be easily achieved by sharing different functions between the system bus 60 side and the system bus 70 side. Further, CPU 10 _1, 10 ₂ and the system bus 60, are separately connected to the system bus 70, ~, 1
Communication between the 0 _n and the CPUs 10 _{n + 1} , 10 _{n + 2} , ..., 10 _m (for example, transfer of control signals) uses a system bus communication line 80 between the bus / interrupt arbitration circuits 20, 50. At the same time, the data can be transmitted at high speed by using the dual port shared memory 4.

[0014]

As described above, according to the present invention, in a tightly coupled multi-CPU processing system, the system buses are divided, and dual port shared memories are connected to the divided system buses to use them. It is possible to share the different functions with each other to realize the function distributed processing and to realize the load distributed processing by connecting a plurality of CPUs on the same bus. In other words, with bus division,
By combining with the tightly-coupled shared memory multi-CPU system, load distribution and function distribution can be realized at the same time by a simple method, and the problems that are problematic in each conventional method can be affected. Not only can it be reduced, but the ability and performance of load distribution and function distribution can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-CPU processing system of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

10 ₁ , 10 ₂ , ~, 10 _n , 10 _{n + 1} , 10 _{n + 2} , ~, 1
0 _m CPU 20,50 Bus / interrupt arbitration circuit 30 ₁ , 30 ₂ , ~, 30 _i , 30 _{i + 1} , 30 _{i + 2} , ~, 3
0 _j I / O 40 dual port shared memory 60, 70 system bus

Claims (4)

[Claims] 1. A tightly coupled shared memory multi-CPU
A processing system, which is connected to the first and second system buses and the first and second system buses, respectively.
A first and a second input / output device for respectively making an interrupt request to the second system bus, and a first CPU comprising a plurality of CPUs respectively connected to the first and second system buses and having a tightly coupled configuration. A second CPU group, a dual port shared memory having first and second ports respectively connected to the first and second system buses, and serving as a shared memory of the first and second CPU groups, , Connected to the second system bus respectively,
A bus acquisition request and an interrupt request that the second CPU group makes to the first and second system buses, respectively, and the first and second
Arbitrates interrupt requests made by the I / O device to the first and second system buses, respectively, and communicates between the first CPU group and the second CPU group via the dual port shared memory. First and second buses to be carried out /
Multi-CP having an interrupt arbitration circuit
U processing system. 2. The first and second bus / interrupt arbitration circuits,
When communication between the first CPU group and the second CPU group is performed via the dual port shared memory, necessary signals are exchanged via a system bus communication line connecting the two. The multi-CPU processing system according to claim 1. 3. The multi-CPU processing system according to claim 1, wherein the first and second CPU groups share different functions. 4. The multi-CPU processing system according to claim 1, wherein the first and second input / output devices are plural.